{"title":"Optimized Multiplier Based upon 6-Input Luts and Vedic Mathematics","authors":"Zulhelmi Zakaria, Shuja A. Abbasi","volume":73,"journal":"International Journal of Electronics and Communication Engineering","pagesStart":26,"pagesEnd":31,"ISSN":"1307-6892","URL":"https:\/\/publications.waset.org\/pdf\/15168","abstract":"
A new approach has been used for optimized design of multipliers based upon the concepts of Vedic mathematics. The design has been targeted to state-of-the art field-programmable gate arrays (FPGAs). The multiplier generates partial products using Vedic mathematics method by employing basic 4x4 multipliers designed by exploiting 6-input LUTs and multiplexers in the same slices resulting in drastic reduction in area. The multiplier is realized on Xilinx FPGAs using devices Virtex-5 and Virtex-6.Carry Chain Adder was employed to obtain final products. The performance of the proposed multiplier was examined and compared to well-known multipliers such as Booth, Carry Save, Carry ripple, and array multipliers. It is demonstrated that the proposed multiplier is superior in terms of speed as well as power consumption.<\/p>\r\n","references":"[1] J.Senthil Kumar , G.Sriram, G.Lakshminarayanan , B.Venkataramani, \"\r\nDesign and Implementation of FPGA based Fast Multipliers with\r\nOptimum Placement & Routing Using Structure Organizer\", National\r\nConference on VLSI design & Testing, PSG College of Technology,\r\nCoimbatore, 21-22 February, 2003\r\n[2] T. V. More and R. V. Kshirsagar, \"Design of low power column bypass\r\nmultiplier using FPGA,\" in Electronics Computer Technology (ICECT),\r\n2011 3rd International Conference on, 2011, pp. 431-435.\r\n[3] G. C. T. Chow, K. Eguro, W. Luk, and P. Leong, \"A Karatsuba-Based\r\nMontgomery Multiplier,\" in Field Programmable Logic and\r\nApplications (FPL), 2010 International Conference on, 2010, pp. 434-\r\n437.\r\n[4] Michael John Sebastian Smith, \"Application-specific integrated\r\ncircuits\", Addison-Wesley, (1997).\r\n[5] S. K. Mangal, R. B. Deshmukh, R. M. Badghare, and R. M. Patrikar,\r\n\"FPGA Implementation of Low Power Parallel Multiplier,\" in VLSI\r\nDesign, 2007. Held jointly with 6th International Conference on\r\nEmbedded Systems., 20th International Conference on, 2007, pp. 115-\r\n120.\r\n[6] S. Bhattacharjee, S. Sil, B. Basak, and A. Chakrabarti, \"Evaluation of\r\npower efficient adder and multiplier circuits for FPGA based DSP\r\napplications,\" in Communication and Industrial Application (ICCIA),\r\n2011 International Conference on, 2011, pp. 1-5.\r\n[7] P. R. Aparna and N. Thomas, \"Design and implementation of a high\r\nperformance multiplier using HDL,\" in Computing, Communication and\r\nApplications (ICCCA), 2012 International Conference on, 2012, pp. 1-5.\r\n[8] S. Akhter, \"VHDL implementation of fast NxN multiplier based on\r\nvedic mathematic,\" in Circuit Theory and Design, 2007. ECCTD 2007.\r\n18th European Conference on, 2007, pp. 472-475.\r\n[9] K. S. Gurumurthy and M. S. Prahalad, \"Fast and power efficient 16 X16\r\nArray of Array multiplier using Vedic Multiplication,\" in Microsystems\r\nPackaging Assembly and Circuits Technology Conference (IMPACT),\r\n2010 5th International, 2010, pp. 1-4.\r\n[10] H. D. Tiwari, G. Gankhuyag, K. Chan Mo, and C. Yong Beom,\r\n\"Multiplier design based on ancient Indian Vedic Mathematics,\" in SoC\r\nDesign Conference, 2008. ISOCC '08. International, 2008, pp. II-65-II-\r\n68.\r\n[11] P. Mehta and D. Gawali, \"Conventional versus Vedic Mathematical\r\nMethod for Hardware Implementation of a Multiplier,\" in Advances in\r\nComputing, Control, & Telecommunication Technologies, 2009. ACT\r\n'09. International Conference on, 2009, pp. 640-642.\r\n[12] V. Kunchigi, L. Kulkarni, and S. Kulkarni, \"High speed and area\r\nefficient Vedic multiplier,\" in Devices, Circuits and Systems (ICDCS),\r\n2012 International Conference on, 2012, pp. 360-364.\r\n[13] L. Sriraman and T. N. Prabakar, \"Design and implementation of two\r\nvariable multiplier using KCM and Vedic Mathematics,\" in Recent\r\nAdvances in Information Technology (RAIT), 2012 1st International\r\nConference on, 2012, pp. 782-787.\r\n[14] Ahmed et. al, \"Architecture-Specific Packing for Virtex-5 FPGAs,\"\r\nFPGA-08, February 24-26, 2008, Monterey, California, USA.\r\n[15] Xilinx, \"ds100, Virtex-5 Family Overview,\" February 6, 2009, Xilinx.\r\nInc.\r\n[16] Xilinx, \"ds150, Virtex-6 Family Overview,\" March 24, 2011, Xilinx.\r\nInc.","publisher":"World Academy of Science, Engineering and Technology","index":"Open Science Index 73, 2013"}