Search results for: digital arithmetic

Authors: Harpreet Singh Dhillon, Abhijit Mitra

Abstract:

A reduced-bit multiplication algorithm based on the ancient Vedic multiplication formulae is proposed in this paper. Both the Vedic multiplication formulae, Urdhva tiryakbhyam and Nikhilam, are first discussed in detail. Urdhva tiryakbhyam, being a general multiplication formula, is equally applicable to all cases of multiplication. It is applied to the digital arithmetic and is shown to yield a multiplier architecture which is very similar to the popular array multiplier. Due to its structure, it leads to a high carry propagation delay in case of multiplication of large numbers. Nikhilam Sutra, on the other hand, is more efficient in the multiplication of large numbers as it reduces the multiplication of two large numbers to that of two smaller numbers. The framework of the proposed algorithm is taken from this Sutra and is further optimized by use of some general arithmetic operations such as expansion and bit-shifting to take advantage of bit-reduction in multiplication. We illustrate the proposed algorithm by reducing a general 4x4-bit multiplication to a single 2 x 2-bit multiplication operation.

Keywords: Multiplication, algorithm, Vedic mathematics, digital arithmetic, reduced-bit.

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Authors: Xing-Jian Li, Shen Qu

Abstract:

The Smith arithmetic determinant is investigated in this paper. By using two different methods, we derive the explicit formula for the Smith arithmetic determinant.

Keywords: Elementary row transformation, Euler function, Matrix decomposition, Smith arithmetic determinant.

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Authors: Haruo Shimada, Akinori Kanasugi

Abstract:

This paper proposes an architecture of dynamically reconfigurable arithmetic circuit. Dynamic reconfiguration is a technique to realize required functions by changing hardware construction during operations. The proposed circuit is based on a complex number multiply-accumulation circuit which is used frequently in the field of digital signal processing. In addition, the proposed circuit performs real number double precision arithmetic operations. The data formats are single and double precision floating point number based on IEEE754. The proposed circuit is designed using VHDL, and verified the correct operation by simulations and experiments.

Keywords: arithmetic circuit, complex number, double precision, dynamic reconfiguration

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Authors: Yukinari Minagi , Akinori Kanasugi

Abstract:

This paper describes about dynamic reconfiguration to miniaturize arithmetic circuits in general-purpose processor. Dynamic reconfiguration is a technique to realize required functions by changing hardware construction during operation. The proposed arithmetic circuit performs floating-point arithmetic which is frequently used in science and technology. The data format is floating-point based on IEEE754. The proposed circuit is designed using VHDL, and verified the correct operation by simulations and experiments.

Keywords: dynamic reconfiguration, floating-point arithmetic, double precision, FPGA

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Authors: Mohamed Al Mahdi Eshtawie, Masuri Bin Othman

Abstract:

Finite impulse response (FIR) filters have the advantage of linear phase, guaranteed stability, fewer finite precision errors, and efficient implementation. In contrast, they have a major disadvantage of high order need (more coefficients) than IIR counterpart with comparable performance. The high order demand imposes more hardware requirements, arithmetic operations, area usage, and power consumption when designing and fabricating the filter. Therefore, minimizing or reducing these parameters, is a major goal or target in digital filter design task. This paper presents an algorithm proposed for modifying values and the number of non-zero coefficients used to represent the FIR digital pulse shaping filter response. With this algorithm, the FIR filter frequency and phase response can be represented with a minimum number of non-zero coefficients. Therefore, reducing the arithmetic complexity needed to get the filter output. Consequently, the system characteristic i.e. power consumption, area usage, and processing time are also reduced. The proposed algorithm is more powerful when integrated with multiplierless algorithms such as distributed arithmetic (DA) in designing high order digital FIR filters. Here the DA usage eliminates the need for multipliers when implementing the multiply and accumulate unit (MAC) and the proposed algorithm will reduce the number of adders and addition operations needed through the minimization of the non-zero values coefficients to get the filter output.

Keywords: Pulse shaping Filter, Distributed Arithmetic, Optimization algorithm.

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Authors: K. Ganesan

Abstract:

By using a new set of arithmetic operations on interval numbers, we discuss some arithmetic properties of interval matrices which intern helps us to compute the powers of interval matrices and to solve the system of interval linear equations.

Keywords: Interval arithmetic, Interval matrix, linear equations.

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Authors: Thomas Behan, Zaiyi Liao, Lian Zhao, Chunting Yang

Abstract:

In this paper, low end Digital Signal Processors (DSPs) are applied to accelerate integer neural networks. The use of DSPs to accelerate neural networks has been a topic of study for some time, and has demonstrated significant performance improvements. Recently, work has been done on integer only neural networks, which greatly reduces hardware requirements, and thus allows for cheaper hardware implementation. DSPs with Arithmetic Logic Units (ALUs) that support floating or fixed point arithmetic are generally more expensive than their integer only counterparts due to increased circuit complexity. However if the need for floating or fixed point math operation can be removed, then simpler, lower cost DSPs can be used. To achieve this, an integer only neural network is created in this paper, which is then accelerated by using DSP instructions to improve performance.

Keywords: Digital Signal Processor (DSP), Integer Neural Network(INN), Low Cost Neural Network, Integer Neural Network DSPImplementation.

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Authors: Erh-Wen Hu, Cyril S. Ku, Andrew T. Russo, Bogong Su, Jian Wang

Abstract:

Unlike general-purpose processors, digital signal processors (DSP processors) are strongly application-dependent. To meet the needs for diverse applications, a wide variety of DSP processors based on different architectures ranging from the traditional to VLIW have been introduced to the market over the years. The functionality, performance, and cost of these processors vary over a wide range. In order to select a processor that meets the design criteria for an application, processor performance is usually the major concern for digital signal processing (DSP) application developers. Performance data are also essential for the designers of DSP processors to improve their design. Consequently, several DSP performance benchmarks have been proposed over the past decade or so. However, none of these benchmarks seem to have included recent new DSP applications. In this paper, we use a new benchmark that we recently developed to compare the performance of popular DSP processors from Texas Instruments and StarCore. The new benchmark is based on the Selectable Mode Vocoder (SMV), a speech-coding program from the recent third generation (3G) wireless voice applications. All benchmark kernels are compiled by the compilers of the respective DSP processors and run on their simulators. Weighted arithmetic mean of clock cycles and arithmetic mean of code size are used to compare the performance of five DSP processors. In addition, we studied how the performance of a processor is affected by code structure, features of processor architecture and optimization of compiler. The extensive experimental data gathered, analyzed, and presented in this paper should be helpful for DSP processor and compiler designers to meet their specific design goals.

Keywords: digital signal processors, DSP benchmark, instruction level parallelism, modified cyclomatic complexity, performance analysis.

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Authors: Vishal Awasthi, Krishna Raj

Abstract:

Any digital processing performed on a signal with larger nyquist interval requires more computation than signal processing performed on smaller nyquist interval. The sampling rate alteration generates the unwanted effects in the system such as spectral aliasing and spectral imaging during signal processing. Multirate-multistage implementation of digital filter can result a significant computational saving than single rate filter designed for sample rate conversion. In this paper, we presented an efficient cascaded integrator comb (CIC) decimation filter that perform fast down sampling using signed digit adder algorithm with compensated frequency droop that arises due to aliasing effect during the decimation process. This proposed compensated CIC decimation filter structure with a hybrid signed digit (HSD) fast adder provide an improved performance in terms of down sampling speed by 65.15% than ripple carry adder (RCA) and reduced area and power by 57.5% and 0.01 % than signed digit (SD) adder algorithms respectively.

Keywords: Sampling rate conversion, Multirate Filtering, Compensation Theory, Decimation filter, CIC filter, Redundant signed digit arithmetic, Fast adders.

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Authors: Dhruba Das

Abstract:

In this paper, a method has been developed to construct the membership surfaces of row and column vectors and arithmetic operations of imprecise matrix. A matrix with imprecise elements would be called an imprecise matrix. The membership surface of imprecise vector has been already shown based on Randomness-Impreciseness Consistency Principle. The Randomness- Impreciseness Consistency Principle leads to defining a normal law of impreciseness using two different laws of randomness. In this paper, the author has shown row and column membership surfaces and arithmetic operations of imprecise matrix and demonstrated with the help of numerical example.

Keywords: Imprecise number, Imprecise vector, Membership surface, Imprecise matrix.

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Authors: Yong-Je Choi, Moo-Seop Kim, Hang-Rok Lee, Ho-Won Kim

Abstract:

Polynomial bases and normal bases are both used for elliptic curve cryptosystems, but field arithmetic operations such as multiplication, inversion and doubling for each basis are implemented by different methods. In general, it is said that normal bases, especially optimal normal bases (ONB) which are special cases on normal bases, are efficient for the implementation in hardware in comparison with polynomial bases. However there seems to be more examined by implementing and analyzing these systems under similar condition. In this paper, we designed field arithmetic operators for each basis over GF(2233), which field has a polynomial basis recommended by SEC2 and a type-II ONB both, and analyzed these implementation results. And, in addition, we predicted the efficiency of two elliptic curve cryptosystems using these field arithmetic operators.

Keywords: Elliptic Curve Cryptosystem, Crypto Algorithm, Polynomial Basis, Optimal Normal Basis, Security.

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Authors: José M. Merigó, Anna M. Gil-Lafuente

Abstract:

Different types of aggregation operators such as the ordered weighted quasi-arithmetic mean (Quasi-OWA) operator and the normalized Hamming distance are studied. We introduce the use of the OWA operator in generalized distances such as the quasiarithmetic distance. We will call these new distance aggregation the ordered weighted quasi-arithmetic distance (Quasi-OWAD) operator. We develop a general overview of this type of generalization and study some of their main properties such as the distinction between descending and ascending orders. We also consider different families of Quasi-OWAD operators such as the Minkowski ordered weighted averaging distance (MOWAD) operator, the ordered weighted averaging distance (OWAD) operator, the Euclidean ordered weighted averaging distance (EOWAD) operator, the normalized quasi-arithmetic distance, etc.

Keywords: Aggregation operators, Distance measures, Quasi- OWA operator.

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Authors: Driss Kettani

Abstract:

In this paper, we shed light on the “Digital Divide 2.0,” which we see as COVID-19’s version of the digital divide. We believe that “fighting” against digital divide 2.0 necessitates for a country to be seriously advanced in the global digital transformation that is, naturally, a complex, delicate, costly and long-term process. We build an argument supporting our assumption and, from there, we present the foundations of a computational framework to guide and streamline digital transformation at all levels.

Keywords: Digital divide 2.0, digital transformation, ICTs for development, computational outcomes assessment.

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Authors: Mehdi Hosseinzadeh, Somayyeh Jafarali Jassbi, Keivan Navi

Abstract:

Residue Number System (RNS) is a modular representation and is proved to be an instrumental tool in many digital signal processing (DSP) applications which require high-speed computations. RNS is an integer and non weighted number system; it can support parallel, carry-free, high-speed and low power arithmetic. A very interesting correspondence exists between the concepts of Multiple Valued Logic (MVL) and Residue Number Arithmetic. If the number of levels used to represent MVL signals is chosen to be consistent with the moduli which create the finite rings in the RNS, MVL becomes a very natural representation for the RNS. There are two concerns related to the application of this Number System: reaching the most possible speed and the largest dynamic range. There is a conflict when one wants to resolve both these problem. That is augmenting the dynamic range results in reducing the speed in the same time. For achieving the most performance a method is considere named “One-Hot Residue Number System" in this implementation the propagation is only equal to one transistor delay. The problem with this method is the huge increase in the number of transistors they are increased in order m² . In real application this is practically impossible. In this paper combining the Multiple Valued Logic and One-Hot Residue Number System we represent a new method to resolve both of these two problems. In this paper we represent a novel design of an OHRNS-based adder circuit. This circuit is useable for Multiple Valued Logic moduli, in comparison to other RNS design; this circuit has considerably improved the number of transistors and power consumption.

Keywords: Computer Arithmetic, Residue Number System, Multiple Valued Logic, One-Hot, VLSI.

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Authors: Amandeep Singh, Mandeep Kaur

Abstract:

Error correcting codes are used for detection and correction of errors in digital communication system. Error correcting coding is based on appending of redundancy to the information message according to a prescribed algorithm. Reed Solomon codes are part of channel coding and withstand the effect of noise, interference and fading. Galois field arithmetic is used for encoding and decoding reed Solomon codes. Galois field multipliers and linear feedback shift registers are used for encoding the information data block. The design of Reed Solomon encoder is complex because of use of LFSR and Galois field arithmetic. The purpose of this paper is to design and implement Reed Solomon (255, 239) encoder with optimized and lesser number of Galois Field multipliers. Symmetric generator polynomial is used to reduce the number of GF multipliers. To increase the capability toward error correction, convolution interleaving will be used with RS encoder. The Design will be implemented on Xilinx FPGA Spartan II.

Keywords: Galois Field, Generator polynomial, LFSR, Reed Solomon.

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Authors: Marios Poulos, George Bokos

Abstract:

This paper makes an attempt to solve the problem of searching and retrieving of similar MRI photos via Internet services using morphological features which are sourced via the original image. This study is aiming to be considered as an additional tool of searching and retrieve methods. Until now the main way of the searching mechanism is based on the syntactic way using keywords. The technique it proposes aims to serve the new requirements of libraries. One of these is the development of computational tools for the control and preservation of the intellectual property of digital objects, and especially of digital images. For this purpose, this paper proposes the use of a serial number extracted by using a previously tested semantic properties method. This method, with its center being the multi-layers of a set of arithmetic points, assures the following two properties: the uniqueness of the final extracted number and the semantic dependence of this number on the image used as the method-s input. The major advantage of this method is that it can control the authentication of a published image or its partial modification to a reliable degree. Also, it acquires the better of the known Hash functions that the digital signature schemes use and produces alphanumeric strings for cases of authentication checking, and the degree of similarity between an unknown image and an original image.

Keywords: Computational Geometry, MRI photos, Image processing, pattern Recognition.

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Authors: Sattar B. Sadkhan, Najlae Falah Hameed

Abstract:

The Elliptic Curve Digital Signature Algorithm (ECDSA) is the elliptic curve analogue of DSA, where it is a digital signature scheme designed to provide a digital signature based on a secret number known only to the signer and also on the actual message being signed. These digital signatures are considered the digital counterparts to handwritten signatures, and are the basis for validating the authenticity of a connection. The security of these schemes results from the infeasibility to compute the signature without the private key. In this paper we introduce a proposed to development the original ECDSA with more complexity.

Keywords: Elliptic Curve Digital Signature Algorithm, DSA.

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Authors: Azali Saudi, Jumat Sulaiman

Abstract:

Harmonic functions are solutions to Laplace’s equation that are known to have an advantage as a global approach in providing the potential values for autonomous vehicle navigation. However, the computation for obtaining harmonic functions is often too slow particularly when it involves very large environment. This paper presents a two-stage iterative method namely Modified Arithmetic Mean (MAM) method for solving 2D Laplace’s equation. Once the harmonic functions are obtained, the standard Gradient Descent Search (GDS) is performed for path finding of an autonomous vehicle from arbitrary initial position to the specified goal position. Details of the MAM method are discussed. Several simulations of vehicle navigation with path planning in a static known indoor environment were conducted to verify the efficiency of the MAM method. The generated paths obtained from the simulations are presented. The performance of the MAM method in computing harmonic functions in 2D environment to solve path planning problem for an autonomous vehicle navigation is also provided.

Keywords: Modified Arithmetic Mean method, Harmonic functions, Laplace’s equation, path planning.

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Authors: Santanu Santra, Utpal Roy

Abstract:

The most important mathematical operation for any computing system is addition. An efficient adder can be of greater assistance in designing of any arithmetic circuits. Quantum-dot Cellular Automata (QCA) is a promising nanotechnology to create electronic circuits for computing devices and suitable candidate for next generation of computing systems. The article presents a modest approach to implement a novel XOR gate. The gate is simple in structure and powerful in terms of implementing digital circuits. By applying the XOR gate, the hardware requirement for a QCA circuit can be decrease and circuits can be simpler in level, clock phase and cell count. In order to verify the functionality of the proposed device some implementation of Half Adder (HA) and Full Adder (FA) is checked by means of computer simulations using QCA-Designer tool. Simulation results and physical relations confirm its usefulness in implementing every digital circuit.

Keywords: Clock, Computing system, Majority gate, QCA, QCA Designer.

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Authors: Davod Khojasteh Salkuyeh

Abstract:

An important task in solving second order linear ordinary differential equations by the finite difference is to choose a suitable stepsize h. In this paper, by using the stochastic arithmetic, the CESTAC method and the CADNA library we present a procedure to estimate the optimal stepsize hopt, the stepsize which minimizes the global error consisting of truncation and round-off error.

Keywords: Ordinary differential equations, optimal stepsize, error, stochastic arithmetic, CESTAC, CADNA.

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Authors: Abhijit Mitra

Abstract:

This paper proposes an efficient finite precision block floating point (BFP) treatment to the fixed coefficient finite impulse response (FIR) digital filter. The treatment includes effective implementation of all the three forms of the conventional FIR filters, namely, direct form, cascaded and par- allel, and a roundoff error analysis of them in the BFP format. An effective block formatting algorithm together with an adaptive scaling factor is pro- posed to make the realizations more simple from hardware view point. To this end, a generic relation between the tap weight vector length and the input block length is deduced. The implementation scheme also emphasises on a simple block exponent update technique to prevent overflow even during the block to block transition phase. The roundoff noise is also investigated along the analogous lines, taking into consideration these implementational issues. The simulation results show that the BFP roundoff errors depend on the sig- nal level almost in the same way as floating point roundoff noise, resulting in approximately constant signal to noise ratio over a relatively large dynamic range.

Keywords: Finite impulse response digital filters, Cascade structure, Parallel structure, Block floating point arithmetic, Roundoff error.

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Authors: Lidia Obojska

Abstract:

This paper has, as its point of departure, the foundational axiomatic theory of E. De Giorgi (1996, Scuola Normale Superiore di Pisa, Preprints di Matematica 26, 1), based on two primitive notions of quality and relation. With the introduction of a unary relation, we develop a system totally based on the sole primitive notion of relation. Such a modification enables a definition of the concept of dynamic unary relation. In this way we construct a simple language capable to express other well known theories such as Robinson-s arithmetic or a piece of a theory of concatenation. A key role in this system plays an abstract relation designated by “( )", which can be interpreted in different ways, but in this paper we will focus on the case when we can perform computations and obtain results.

Keywords: language, unary relations, arithmetic, computability

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Authors: Shiv Shankar Mishra, S. Wairya, R. K. Nagaria, S. Tiwari

Abstract:

New methodologies for XOR-XNOR circuits are proposed to improve the speed and power as these circuits are basic building blocks of many arithmetic circuits. This paper evaluates and compares the performance of various XOR-XNOR circuits. The performance of the XOR-XNOR circuits based on TSMC 0.18μm process models at all range of the supply voltage starting from 0.6V to 3.3V is evaluated by the comparison of the simulation results obtained from HSPICE. Simulation results reveal that the proposed circuit exhibit lower PDP and EDP, more power efficient and faster when compared with best available XOR-XNOR circuits in the literature.

Keywords: Exclusive-OR (XOR), Exclusive-NOR (XNOR), High speed, Low power, Arithmetic Circuits.

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Authors: Hossein Khademolhosseini, Mehdi Hosseinzadeh

Abstract:

The residue number system (RNS), due to its properties, is used in applications in which high performance computation is needed. The carry free nature, which makes the arithmetic, carry bounded as well as the paralleling facility is the reason of its capability of high speed rendering. Since carry is not propagated between the moduli in this system, the performance is only restricted by the speed of the operations in each modulus. In this paper a novel method of number representation by use of redundancy is suggested in which {rn- 2,rn-1,rn} is the reference moduli set where r=2k+1 and k =1, 2,3,.. This method achieves fast computations and conversions and makes the circuits of them much simpler.

Keywords: Binary to RNS converter, Carry save adder, Computer arithmetic, Residue number system.

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Authors: Gurinder Singh, Kulbir Singh

Abstract:

Digital multimedia contents such as image, video, and audio can be tampered easily due to the availability of powerful editing softwares. Multimedia forensics is devoted to analyze these contents by using various digital forensic techniques in order to validate their authenticity. Digital image forensics is dedicated to investigate the reliability of digital images by analyzing the integrity of data and by reconstructing the historical information of an image related to its acquisition phase. In this paper, a survey is carried out on the forgery detection by considering the most recent and promising digital image forensic techniques.

Keywords: Computer forensics, multimedia forensics, image ballistics, camera source identification, forgery detection.

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Authors: Anod H. Alhazmi, Hanaa A. Yamani

Abstract:

The lack of digital transformation professionals could prevent Saudi Arabia’s universities from providing digital services. The task of understanding what digital skills are needed within an organization, measuring the existing skills, and developing or attracting talents is a complex task. This paper provides a comprehensive analysis of the digital transformation skills needed in the organizations who seek digital transformation and identifies the skills and competencies framework DigSC built on Skills Framework for the Informational Age (SFIA) framework that is adopted by the Ministry of Communications and Information Technology (MCIT) in Saudi Arabia. The framework adopted identifies the main digital transformation skills clusters, categories and levels of responsibilities for each job description to fill the gap between this requirement and the digital skills supplied by the Umm Alqura University (UQU).

Keywords: Competencies, digital transformation, framework, skills, Umm Alqura University.

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Authors: Hui Liu, Haiyang Quan

Abstract:

This paper To get the angle value with a MEMS rate gyroscope in some specific field, the usual method is to make an integral operation to the rate output, which will lead the error cumulating effect. So the rate gyro is not suitable. MEMS rate integrating gyroscope (MRIG) will solve this problem. A DSP system has been developed to implement the control arithmetic. The system can measure the angle of rotation directly by the control loops that make the sensor work in whole-angle mode. Modeling the system with MATLAB, desirable results of angle outputs are got, which prove the feasibility of the control arithmetic.

Keywords: Rate gyroscope, Rate integrating gyroscope, Whole angle mode, MATLAB modeling, DSP control.

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Authors: Sarah E. Stief, Anne Theresa Eidhoff, Markus Voeth

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Despite all progress firms are facing the increasing need to adapt and assimilate digital technologies to transform their business activities in order to pursue business development. By using new digital technologies, firms can implement major business improvements in order to stay competitive and foster new growth potentials. The corresponding phenomenon of digital transformation has received some attention in previous literature in respect to industries such as media and publishing. Nevertheless, there is a lack of understanding of the concept and its organization within firms. With the help of twenty-three in-depth field interviews with German experts responsible for their company’s digital transformation, we examined what digital transformation encompasses, how it is organized and which opportunities and challenges arise within firms. Our results indicate that digital transformation is an inevitable task for all firms, as it bears the potential to comprehensively optimize and reshape established business activities and can thus be seen as a strategy of business development.

Keywords: Business development, digitalization, digital strategies, digital transformation.

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Authors: Vishal Awasthi, Krishna Raj

Abstract:

In this paper, firstly, we present the mathematical modeling of finite impulse response (FIR) filter and Cascaded Integrator Comb (CIC) filter for sampling rate reduction and then an extension of Canonical signed digit (CSD) based efficient structure is presented in framework using hybrid signed digit (HSD) arithmetic. CSD representation imposed a restriction that two non-zero CSD coefficient bits cannot acquire adjacent bit positions and therefore, represented structure is not economical in terms of speed, area and power consumption. The HSD based structure gives optimum performance in terms of area and speed with 37.02% passband droop compensation.

Keywords: Multirate filtering, compensation theory, CIC filter, compensation filter, signed digit arithmetic, canonical signed digit.

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Authors: Ayman El-Garem, Riham Adel

Abstract:

Digital transformation is about identifying the necessary changes of the entire business model, rethinking how to transform the traditional operations into digital ones that can create better value to its customers. Efforts are common across industries, but they often fail due to a lack of understanding of the factors required to focus on and change to be able to embark in digital transformation successfully. Further research is required to bridge the knowledge gap between academia and industry to support companies starting their digital transformation journey. To date there is no consensus on digital transformation key success factors. Therefore, the aim of this paper is to identify the success factors in digital transformation journey, throughout conducting a systematic literature review of 134 peer-reviewed articles to get better insights regarding the research progress in this field.  After completing the systematic literature review it will be followed by Delphi study to get experts consensus on the most significant factors affecting digital transformation implementation. The findings indicate that organizations undergoing digital transformation should focus mainly on (1) well managed digital transformation activities; (2) digital business strategy; (3) supportive culture; (4) top management support; (5) organizational change capabilities.

Keywords: Digital transformation, key success factors, literature review, Delphi study.

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