Search results for: Complementary Metal Oxide Semiconductor (CMOS)
1292 Green Prossesing of PS/Nanoparticle Fibers and Studying Morphology and Properties
Authors: M. Kheirandish, S. Borhani
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In this experiment Polystyrene/Zinc-oxide (PS/ZnO) nanocomposite fibers were produced by electrospinning technique using limonene as a green solvent. First, the morphology of electrospun pure polystyrene (PS) and PS/ZnO nanocomposite fibers investigated by SEM. Results showed the PS fiber diameter decreased by increasing concentration of Zinc Oxide nanoparticles (ZnO NPs). Thermo Gravimetric Analysis (TGA) results showed thermal stability of nanocomposites increased by increasing ZnO NPs in PS electrospun fibers. Considering Differential Scanning Calorimeter (DSC) thermograms for electrospun PS fibers indicated that introduction of ZnO NPs into fibers affects the glass transition temperature (Tg) by reducing it. Also, UV protection properties of nanocomposite fibers were increased by increasing ZnO concentration. Evaluating the effect of metal oxide NPs amount on mechanical properties of electrospun layer showed that tensile strength and elasticity modulus of the electrospun layer of PS increased by addition of ZnO NPs. X-ray diffraction (XRD) pattern of nanopcomposite fibers confirmed the presence of NPs in the samples.
Keywords: Electrospininng, nanoparticle, polystyrene, ZnO.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 22331291 Novel Linear Autozeroing Floating-gate Amplifier for Ultra Low-voltage Applications
Authors: Yngvar Berg, Mehdi Azadmehr
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In this paper we present a linear autozeroing ultra lowvoltage amplifier. The autozeroing performed by all ULV circuits is important to reduce the impact of noise and especially avoid power supply noise in mixed signal low-voltage CMOS circuits. The simulated data presented is relevant for a 90nm TSMC CMOS process.
Keywords: Low-voltage, trans conductance amplifier, linearity, floating-gate.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 13771290 Laboratory Evaluation of the Flotation Response of a Copper Cobalt Oxide Ore to Gasoil-Rinkalore Mixtures
Authors: M. B. Kime, J. Ntambwe, J. Mwamba
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Froth flotation remains to date as one of the most used metallurgical processes for concentrating metal-bearing minerals in ores. Oxide ores are relatively less amenable to froth flotation and require a judicious choice of reagents for the recovery of metals to be optimised. Laboratory batch flotation tests were conducted to determine the effect of two types of gasoil-rinkalore mixtures on the flotation response of a copper cobalt oxide ore sample. The head assay conducted on the initial ore sample showed that it contained about 2.90% of Cu, 0.12% of Co. Upon the flotation test work, the results obtained indicated that the concentrate obtained with use of the mixture gazoil-rinkalore RX yielded 8.24% Cu and 0.22% Co concentrate grades with recoveries of 76.0% Cu and 78.0% Co respectively. But, the concentrate obtained by use of the mixture gazoil-rinkalore RX3 yielded relatively bad results with 5.92% Cu and 0.18% Cu concentrate grades with recoveries of 70.3% Cu and 65.3% Co respectively.Keywords: Cobalt, copper, froth flotation, Rinkalore RX, Rinkalore RX3, Shangolowe.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 28741289 A Unity Gain Fully-Differential 10bit and 40MSps Sample-And-Hold Amplifier in 0.18um CMOS
Authors: Sanaz Haddadian, Rahele Hedayati
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A 10bit, 40 MSps, sample and hold, implemented in 0.18-μm CMOS technology with 3.3V supply, is presented for application in the front-end stage of an analog-to-digital converter. Topology selection, biasing, compensation and common mode feedback are discussed. Cascode technique has been used to increase the dc gain. The proposed opamp provides 149MHz unity-gain bandwidth (wu), 80 degree phase margin and a differential peak to peak output swing more than 2.5v. The circuit has 55db Total Harmonic Distortion (THD), using the improved fully differential two stage operational amplifier of 91.7dB gain. The power dissipation of the designed sample and hold is 4.7mw. The designed system demonstrates relatively suitable response in different process, temperature and supply corners (PVT corners).
Keywords: Analog Integrated Circuit Design, Sample & Hold Amplifier and CMOS Technology.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 41501288 Design and Analysis of a Low Power High Speed 1 Bit Full Adder Cell Based On TSPC Logic with Multi-Threshold CMOS
Authors: Ankit Mitra
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An adder is one of the most integral component of a digital system like a digital signal processor or a microprocessor. Being an extremely computationally intensive part of a system, the optimization for speed and power consumption of the adder is of prime importance. In this paper we have designed a 1 bit full adder cell based on dynamic TSPC logic to achieve high speed operation. A high threshold voltage sleep transistor is used to reduce the static power dissipation in standby mode. The circuit is designed and simulated in TSPICE using TSMC 180nm CMOS process. Average power consumption, delay and power-delay product is measured which showed considerable improvement in performance over the existing full adder designs.
Keywords: CMOS, TSPC, MTCMOS, ALU, Clock gating, power gating, pipelining.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 30661287 Robust & Energy Efficient Universal Gates for High Performance Computer Networks at 22nm Process Technology
Authors: M. Geetha Priya, K. Baskaran, S. Srinivasan
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Digital systems are said to be constructed using basic logic gates. These gates are the NOR, NAND, AND, OR, EXOR & EXNOR gates. This paper presents a robust three transistors (3T) based NAND and NOR gates with precise output logic levels, yet maintaining equivalent performance than the existing logic structures. This new set of 3T logic gates are based on CMOS inverter and Pass Transistor Logic (PTL). The new universal logic gates are characterized by better speed and lower power dissipation which can be straightforwardly fabricated as memory ICs for high performance computer networks. The simulation tests were performed using standard BPTM 22nm process technology using SYNOPSYS HSPICE. The 3T NAND gate is evaluated using C17 benchmark circuit and 3T NOR is gate evaluated using a D-Latch. According to HSPICE simulation in 22 nm CMOS BPTM process technology under given conditions and at room temperature, the proposed 3T gates shows an improvement of 88% less power consumption on an average over conventional CMOS logic gates. The devices designed with 3T gates will make longer battery life by ensuring extremely low power consumption.
Keywords: Low power, CMOS, pass-transistor, flash memory, logic gates.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 24231286 Low Power Digital System for Reconfigurable Neural Recording System
Authors: Peng Li, Jun Zhou, Xin Liu, Chee Keong Ho, Xiaodan Zou, Minkyu Je
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A digital system is proposed for low power 100- channel neural recording system in this paper, which consists of 100 amplifiers, 100 analog-to-digital converters (ADC), digital controller and baseband, transceiver for data link and RF command link. The proposed system is designed in a 0.18 μm CMOS process and 65 nm CMOS process.Keywords: multiplex, neural recording, synchronization, transceiver
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 16461285 A Continuous Time Sigma Delta Modulators Using CMOS Current Conveyors
Authors: E. Farshidi, N. Ahmadpoor
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In this paper, a alternative structure method for continuous time sigma delta modulator is presented. In this modulator for implementation of integrators in loop filter second generation current conveyors are employed. The modulator is designed in CMOS technology and features low power consumption (<2.8mW), low supply voltage (±1.65), wide dynamic range (>65db), and with 180khZ bandwidth. Simulation results confirm that this design is suitable for data converters.Keywords: Current Conveyor, continuous, sigma delta, MOS, modulator
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 21141284 Study of a Fabry-Perot Resonator
Authors: F. Hadjaj, A. Belghachi, A. Halmaoui, M. Belhadj, H. Mazouz
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A laser is essentially an optical oscillator consisting of a resonant cavity, an amplifying medium and a pumping source. In semiconductor diode lasers, the cavity is created by the boundary between the cleaved face of the semiconductor crystal and air, and has reflective properties as a result of the differing refractive indices of the two media. For a GaAs-air interface a reflectance of 0.3 is typical and therefore the length of the semiconductor junction forms the resonant cavity. To prevent light being emitted in unwanted directions from the junction, sides perpendicular to the required direction are roughened. The objective of this work is to simulate the optical resonator Fabry-Perot and explore its main characteristics, such as FSR, finesse, linewidth, transmission and so on, that describe the performance of resonator.
Keywords: Fabry-Perot Resonator, laser diode.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 89431283 Technique for Online Condition Monitoring of Surge Arrestors
Authors: Anil S. Khopkar, Kartik S. Pandya
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Lightning overvoltage phenomenon in power systems cannot be avoided; however, it can be controlled to certain extent. To prevent system failure, power system equipment must be protected against overvoltage. Metal Oxide Surge Arrestors (MOSA) are connected in the system to provide protection against overvoltages. Under normal working conditions, MOSA function as, insulators, offering a conductive path during overvoltage events. MOSA consists of zinc oxide elements (ZnO Blocks) which has non-linear V-I characteristics. The ZnO blocks are connected in series and fitted in ceramic or polymer housing. Over time, these components degrade due to continuous operation. The degradation of zinc oxide elements increases the leakage current flowing through the surge arrestors. This increased leakage current results in elevated temperatures within the surge arrester, further decreasing the resistance of the zinc oxide elements. Consequently, the leakage current increases, leading to higher temperatures within the MOSA. This cycle creates thermal runaway conditions for the MOSA. Once a surge arrester reaches the thermal runaway condition, it cannot return to normal working conditions. This condition is a primary cause of premature failure of surge arrestors. Given that MOSA constitutes a core protective device for electrical power systems against transients, it contributes significantly to the reliable operation of power system networks. Therefore, periodic condition monitoring of surge arrestors is essential. Both online and offline condition monitoring techniques are available for surge arrestors. Offline condition monitoring techniques are not as popular because they require the removal of surge arrestors from the system, which requires system shutdown. Therefore, online condition monitoring techniques are more commonly used. This paper presents an evaluation technique for the surge arrester condition based on leakage current analysis. The maximum amplitudes of total leakage current (IT), fundamental resistive leakage current (IR), and third harmonic resistive leakage current (I3rd) are analyzed as indicators for surge arrester condition monitoring.
Keywords: Metal Oxide Surge Arrester, MOSA, Over voltage, total leakage current, resistive leakage current, third harmonic resistive leakage current, capacitive leakage current.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 641282 Design of High Gain, High Bandwidth Op-Amp for Reduction of Mismatch Currents in Charge Pump PLL in 180 nm CMOS Technology
Authors: R .H. Talwekar, S. S Limaye
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The designing of charge pump with high gain Op- Amp is a challenging task for getting faithful response .Design of high performance phase locked loop require ,a design of high performance charge pump .We have designed a operational amplifier for reducing the error caused by high speed glitch in a transistor and mismatch currents . A separate Op-Amp has designed in 180 nm CMOS technology by CADENCE VIRTUOSO tool. This paper describes the design of high performance charge pump for GHz CMOS PLL targeting orthogonal frequency division multiplexing (OFDM) application. A high speed low power consumption Op-Amp with more than 500 MHz bandwidth has designed for increasing the speed of charge pump in Phase locked loop.Keywords: Charge pump (CP) Orthogonal frequency divisionmultiplexing (OFDM), Phase locked loop (PLL), Phase frequencydetector (PFD), Voltage controlled oscillator (VCO),
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 34271281 Research on Modern Semiconductor Converters and the Usage of SiC Devices in the Technology Centre of Ostrava
Authors: P. Vaculík, P. Kaňovský
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The following article presents Technology Centre of Ostrava (TCO) in the Czech Republic describing the structure and main research areas realized by the project ENET - Energy Units for Utilization of non Traditional Energy Sources. More details are presented from the research program dealing with transformation, accumulation and distribution of electric energy. Technology Centre has its own energy mix consisting of alternative sources of fuel sources that use of process gases from the storage part and also the energy from distribution network. The article will be focus on the properties and application possibilities SiC semiconductor devices for power semiconductor converter for photovoltaic systems.Keywords: SiC, Si, Technology Centre of Ostrava, Photovoltaic Systems, DC/DC Converter, Simulation.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 18361280 The removal of Ni, Cu and Fe from a Mixed Metal System using Sodium Hypophosphite as a Reducing Agent
Authors: Promise Sethembiso Ngema, Freeman Ntuli, Mohamed Belaid
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The main objective of this study was to remove and recover Ni, Cu and Fe from a mixed metal system using sodium hypophosphite as a reducing agent and nickel powder as seeding material. The metal systems studied consisted of Ni-Cu, Ni-Fe and Ni-Cu-Fe solutions. A 5 L batch reactor was used to conduct experiments where 100 mg/l of each respective metal was used. It was found that the metals were reduced to their elemental form with removal efficiencies of over 80%. The removal efficiency decreased in the order Fe>Ni>Cu. The metal powder obtained contained between 97-99% Ni and was almost spherical and porous. Size enlargement by aggregation was the dominant particulate process.
Keywords: crystallization, electroless plating, heavy metal removal, wastewater treatment
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 20291279 Electronic Nose Based On Metal Oxide Semiconductor Sensors as an Alternative Technique for the Spoilage Classification of Oat Milk
Authors: A. Deswal, N. S. Deora, H. N. Mishra
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The aim of the present study was to develop a rapid method for electronic nose for online quality control of oat milk. Analysis by electronic nose and bacteriological measurements were performed to analyze spoilage kinetics of oat milk samples stored at room temperature and refrigerated conditions for up to 15 days. Principal component analysis (PCA), Discriminant Factorial Analysis (DFA) and Soft Independent Modelling by Class Analogy (SIMCA) classification techniques were used to differentiate the samples of oat milk at different days. The total plate count (bacteriological method) was selected as the reference method to consistently train the electronic nose system. The e-nose was able to differentiate between the oat milk samples of varying microbial load. The results obtained by the bacteria total viable countsshowed that the shelf-life of oat milk stored at room temperature and refrigerated conditions were 20hrs and 13 days, respectively. The models built classified oat milk samples based on the total microbial population into “unspoiled” and “spoiled”.
Keywords: Electronic-nose, bacteriological, shelf-life, classification.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 32641278 Esterification of Free Fatty Acids in Crude Palm Oil Using Alumina-Doped Sulfated Tin Oxide as a Catalyst
Authors: Worawoot Prasitturattanachai, Kamchai Nuithitikul
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The conventional production of biodiesel from crude palm oil which contains large amounts of free fatty acids in the presence of a homogeneous base catalyst confronts the problems of soap formation and very low yield of biodiesel. To overcome these problems, free fatty acids must be esterified to their esters in the presence of an acid catalyst prior to alkaline-catalyzed transesterification. Sulfated metal oxides are a promising group of catalysts due to their very high acidity. In this research, aluminadoped sulfated tin oxide (SO4 2-/Al2O3-SnO2) catalysts were prepared and used for esterification of free fatty acids in crude palm oil in a batch reactor. The SO4 2-/Al2O3-SnO2 catalysts were prepared from different Al precursors. The results showed that different Al precursors gave different activities of the SO4 2-/Al2O3-SnO2 catalysts. The esterification of free fatty acids in crude palm oil with methanol in the presence of SO4 2-/Al2O3-SnO2 catalysts followed first-order kinetics.
Keywords: Methyl ester, Biodiesel, Esterification, Sulfated tin oxide, Fatty acid.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 30501277 Analysis of CNT Bundle and its Comparison with Copper for FPGAs Interconnects
Authors: Kureshi Abdul Kadir, Mohd. Hasan
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Each new semiconductor technology node brings smaller transistors and wires. Although this makes transistors faster, wires get slower. In nano-scale regime, the standard copper (Cu) interconnect will become a major hurdle for FPGA interconnect due to their high resistivity and electromigration. This paper presents the comprehensive evaluation of mixed CNT bundle interconnects and investigates their prospects as energy efficient and high speed interconnect for future FPGA routing architecture. All HSPICE simulations are carried out at operating frequency of 1GHz and it is found that mixed CNT bundle implemented in FPGAs as interconnect can potentially provide a substantial delay and energy reduction over traditional interconnects at 32nm process technology.Keywords: CMOS, Copper Interconnect, Mixed CNT Bundle Interconnect, FPGAs.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 16291276 Pattern Recognition Using Feature Based Die-Map Clusteringin the Semiconductor Manufacturing Process
Authors: Seung Hwan Park, Cheng-Sool Park, Jun Seok Kim, Youngji Yoo, Daewoong An, Jun-Geol Baek
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Depending on the big data analysis becomes important, yield prediction using data from the semiconductor process is essential. In general, yield prediction and analysis of the causes of the failure are closely related. The purpose of this study is to analyze pattern affects the final test results using a die map based clustering. Many researches have been conducted using die data from the semiconductor test process. However, analysis has limitation as the test data is less directly related to the final test results. Therefore, this study proposes a framework for analysis through clustering using more detailed data than existing die data. This study consists of three phases. In the first phase, die map is created through fail bit data in each sub-area of die. In the second phase, clustering using map data is performed. And the third stage is to find patterns that affect final test result. Finally, the proposed three steps are applied to actual industrial data and experimental results showed the potential field application.
Keywords: Die-Map Clustering, Feature Extraction, Pattern Recognition, Semiconductor Manufacturing Process.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 31401275 Zinc Oxide Nanoparticles Modified with Galactose as Potential Drug Carrier with Reduced Releasing of Zinc Ions
Authors: Jolanta Pulit-Prociak, Olga Długosz, Marcin Banach
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The toxicity of bare zinc oxide nanoparticles used as drug carriers may be the result of releasing zinc ions. Thus, zinc oxide nanoparticles modified with galactose were obtained. The process of their formation was conducted in the microwave field. The physicochemical properties of the obtained products were studied. The size and electrokinetic potential were defined by using dynamic light scattering technique. The crystalline properties were assessed by X-ray diffractometry. In order to confirm the formation of the desired products, Fourier-transform infrared spectroscopy was used. Releasing of zinc ions from the prepared products when comparing to the bare oxide was analyzed. It was found out that modification of zinc oxide nanoparticles with galactose limits the releasing of zinc ions which are responsible for the toxic effect of the whole carrier-drug conjugate.
Keywords: Nanomaterials, zinc oxide, drug delivery system, toxicity.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 5361274 Effective Photodegradation of Tetracycline by a Heteropoly Acid/Graphene Oxide Nanocomposite Based on Uio-66
Authors: Anasheh Maridiroosi, Ali Reza Mahjoub, Hanieh Fakhri
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Heteropoly acid nanoparticles anchored on graphene oxide based on UiO-66 were synthesized via in-situ growth hydrothermal method and tested for photodegradation of a tetracycline as critical pollutant. Results showed that presence of graphene oxide and UiO-66 with high specific surface area, great electron mobility and various functional groups make an excellent support for heteropoly acid and improve photocatalytic efficiency up to 95% for tetracycline. Furthermore, total organic carbon (TOC) analysis verified 79% mineralization of this pollutant under optimum condition.
Keywords: Heteropoly acid, graphene oxide, MOF, tetracycline.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 7451273 Current Controlled Current Conveyor (CCCII)and Application using 65nm CMOS Technology
Authors: Zia Abbas, Giuseppe Scotti, Mauro Olivieri
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Current mode circuits like current conveyors are getting significant attention in current analog ICs design due to their higher band-width, greater linearity, larger dynamic range, simpler circuitry, lower power consumption and less chip area. The second generation current controlled conveyor (CCCII) has the advantage of electronic adjustability over the CCII i.e. in CCCII; adjustment of the X-terminal intrinsic resistance via a bias current is possible. The presented approach is based on the CMOS implementation of second generation positive (CCCII+), negative (CCCII-) and dual Output Current Controlled Conveyor (DOCCCII) and its application as Universal filter. All the circuits have been designed and simulated using 65nm CMOS technology model parameters on Cadence Virtuoso / Spectre using 1V supply voltage. Various simulations have been carried out to verify the linearity between output and input ports, range of operation frequency, etc. The outcomes show good agreement between expected and experimental results.Keywords: CCCII+, CCCII-, DOCCCII, Electronic tunability, Universal filter
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 46941272 AI Applications to Metal Stamping Die Design– A Review
Authors: Vishal Naranje, Shailendra Kumar
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Metal stamping die design is a complex, experiencebased and time-consuming task. Various artificial intelligence (AI) techniques are being used by worldwide researchers for stamping die design to reduce complexity, dependence on human expertise and time taken in design process as well as to improve design efficiency. In this paper a comprehensive review of applications of AI techniques in manufacturability evaluation of sheet metal parts, die design and process planning of metal stamping die is presented. Further the salient features of major research work published in the area of metal stamping are presented in tabular form and scope of future research work is identified.Keywords: Artificial Intelligence, Die design, ManufacturabilityEvaluation, Metal Stamping Die.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 38461271 Evaluation of the Magnesium Wastes with Boron Oxide in Magnesium Borate Synthesis
Authors: A. S. Kipcak, F. T. Senberber, E. Moroydor Derun, S. Piskin
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Magnesium wastes and scraps, one of the metal wastes, are produced by many industrial activities, all over the world. Their growing size is becoming a future problem for the world. In this study, the use of magnesium wastes as a raw material in the production of the magnesium borate hydrates are aimed. The method used in the experiments is hydrothermal synthesis. The conditions are set to, waste magnesium to B2O3, 1:3 as a molar ratio. Four different reaction times are studied which are 30, 60, 120 and 240 minutes. For the identification analyses X-Ray Diffraction (XRD), Fourier Transform Infrared Spectroscopy (FT-IR) and Raman spectroscopy techniques are used. As a result at all the reaction times magnesium borate hydrates are synthesized and the most crystalline forms are obtained at a reaction time of 120 minutes. The overall yields of the production are found between the values of 65-80 %.
Keywords: Hydrothermal synthesis, magnesium borates, magnesium wastes, boron oxide
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 23231270 Highly Optimized Novel High Speed Low Power Barrel Shifter at 22nm Hi K Metal Gate Strained Si Technology Node
Authors: Shobha Sharma, Amita Dev
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This research paper presents highly optimized barrel shifter at 22nm Hi K metal gate strained Si technology node. This barrel shifter is having a unique combination of static and dynamic body bias which gives lowest power delay product. This power delay product is compared with the same circuit at same technology node with static forward biasing at ‘supply/2’ and also with normal reverse substrate biasing and still found to be the lowest. The power delay product of this barrel sifter is .39362X10-17J and is lowered by approximately 78% to reference proposed barrel shifter at 32nm bulk CMOS technology. Power delay product of barrel shifter at 22nm Hi K Metal gate technology with normal reverse substrate bias is 2.97186933X10-17J and can be compared with this design’s PDP of .39362X10-17J. This design uses both static and dynamic substrate biasing and also has approximately 96% lower power delay product compared to only forward body biased at half of supply voltage. The NMOS model used are predictive technology models of Arizona state university and the simulations to be carried out using HSPICE simulator.Keywords: Dynamic body biasing, highly optimized barrel shifter, PDP, Static body biasing.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 18791269 Preparation of Protective Coating Film on Metal Alloy
Authors: Rana Th. A. Al-Rubaye
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A novel chromium-free protective coating films based on a zeolite coating was growing onto a FeCrAlloy metal using in – situ hydrothermal method. The zeolite film was obtained using in-situ crystallization process that is capable of coating large surfaces with complex shape and in confined spaces has been developed. The zeolite coating offers an advantage of a high mechanical stability and thermal stability. The physicochemical properties were investigated using X-ray diffraction (XRD), Electron Microscopy (SEM), Energy Dispersive X–ray Analysis (EDX) and Thermogravimetric Analysis (TGA). The transition from oxide-on-alloy wires to hydrothermally synthesised uniformly zeolite coated surfaces was followed using SEM and XRD. In addition, the robustness of the prepared coating was confirmed by subjecting these to thermal cycling (ambient to 550oC).Keywords: FeCrAlloy, Zeolite ZSM-5. Zeolite coating.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 18331268 The Microstructure of Aging ZnO, AZO, and GZO Films
Authors: Z. C. Chang, S. C. Liang
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RF magnetron sputtering is used on the ceramic targets, each of which contains zinc oxide (ZnO), zinc oxide doped with aluminum (AZO) and zinc oxide doped with gallium (GZO). The electric conduction mechanism of the AZO and GZO films came mainly from the Al and Ga, the oxygen vacancies, Zn interstitial atoms, and Al and/or Ga interstitial atoms. AZO and GZO films achieved higher conduction than did ZnO film, it being ion vacant and nonstoichiometric. The XRD analysis showed a preferred orientation along the (002) plane for ZnO, AZO, and GZO films.
Keywords: ZnO, AZO, GZO, Doped, Sputtering
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 27441267 The Effect of Aging of ZnO, AZO, and GZO Films on the Microstructure and Photoelectric Property
Authors: Zue Chin Chang
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RF magnetron sputtering is used on the ceramic targets, each of which contains zinc oxide (ZnO), zinc oxide doped with aluminum (AZO) and zinc oxide doped with gallium (GZO). The XRD analysis showed a preferred orientation along the (002) plane for ZnO, AZO, and GZO films. The AZO film had the best electrical properties; it had the lowest resistivity of 6.6 × 10-4 cm, the best sheet resistance of 2.2 × 10-1 Ω/square, and the highest carrier concentration of 4.3 × 1020 cm-3, as compared to the ZnO and GZO films.Keywords: Aging, films, Microstructure, Photoelectric Property.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 20091266 A Novel Four-Transistor SRAM Cell with Low Dynamic Power Consumption
Authors: Arash Azizi Mazreah, Mohammad T. Manzuri Shalmani, Hamid Barati, Ali Barati
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This paper presents a novel CMOS four-transistor SRAM cell for very high density and low power embedded SRAM applications as well as for stand-alone SRAM applications. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 20% smaller than a conventional six-transistor cell using same design rules. Also proposed cell uses two word-lines and one pair bit-line. Read operation perform from one side of cell, and write operation perform from another side of cell, and swing voltage reduced on word-lines thus dynamic power during read/write operation reduced. The fabrication process is fully compatible with high-performance CMOS logic technologies, because there is no need to integrate a poly-Si resistor or a TFT load. HSPICE simulation in standard 0.25μm CMOS technology confirms all results obtained from this paper.Keywords: Positive feedback, leakage current, read operation, write operation, dynamic energy consumption.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 28531265 Heavy Metal Concentration in Orchard Area, Amphawa District, Samut Songkram Province, Thailand
Authors: Sisuwan Kaseamsawat, Sivapan Choo-In
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A study was conducted in May to July 2013 with the aim of determination of heavy metal concentration in orchard area. 60 samples were collected and analyzed for Cadmium (Cd), Copper (Cu), Lead (Pb), and Zinc (Zn) by Atomic Absorption Spectrophotometer (AAS).
The heavy metal concentrations in sediment of orchards, that use chemical for Cd (1.13 ± 0.26 mg/l), Cu (8.00 ± 1.05 mg/l), Pb (13.16 ± 2.01) and Zn (37.41 ± 3.20 mg/l). The heavy metal concentrations in sediment of the orchards, that do not use chemical for Cd (1.28 ± 0.50 mg/l), Cu (7.60 ± 1.20 mg/l), Pb (29.87 ± 4.88) and Zn (21.79 ± 2.98 mg/l). Statistical analysis between heavy metal in sediment from the orchard, that use chemical and the orchard, that not use chemical were difference statistic significant of 0.5 level of significant for Cd and Pb while no statistically difference for Cu and Zn.
Keywords: Heavy metal, Orchard, Pollution and monitoring, Sediment.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 19961264 Solving Differential's Equation of Carrier Load on Semiconductor
Authors: Morteza Amirabadi, Vahid Fayaz , Fereshteh Felegary, Hossien Hossienkhani
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The most suitable Semiconductor detector, Cadmium Zinc Teloraid , has unique properties because of high Atomic number and wide Brand Gap . It has been tried in this project with different processes such as Lead , Diffusion , Produce and Recombination , effect of Trapping and injection carrier of CdZnTe , to get hole and then present a complete answer of it . Then we should investigate the movement of carrier ( Electron – Hole ) by using above answer.Keywords: Semiconcuctor detector, Trapping, Recommbination, Diffusion
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 14451263 On Use of Semiconductor Detector Arrays on COMPASS Tokamak
Authors: V. Weinzettl, M. Imrisek, J. Havlicek, J. Mlynar, D. Naydenkova, P. Hacek, M. Hron, F. Janky, D. Sarychev, M. Berta, A. Bencze, T. Szabolics
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Semiconductor detector arrays are widely used in high-temperature plasma diagnostics. They have a fast response, which allows observation of many processes and instabilities in tokamaks. In this paper, there are reviewed several diagnostics based on semiconductor arrays as cameras, AXUV photodiodes (referred often as fast “bolometers") and detectors of both soft X-rays and visible light installed on the COMPASS tokamak recently. Fresh results from both spring and summer campaigns in 2012 are introduced. Examples of the utilization of the detectors are shown on the plasma shape determination, fast calculation of the radiation center, two-dimensional plasma radiation tomography in different spectral ranges, observation of impurity inflow, and also on investigation of MHD activity in the COMPASS tokamak discharges.Keywords: Bolometry, plasma diagnostics, soft X-rays, tokamak.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 2578