Search results for: excess loop delay

Authors: J. P. P. Andrade, V. A. F. Campos

Abstract:

This work presents an application of Linear Matrix Inequalities (LMI) for the robust control of an F-16 aircraft through an algorithm ensuring the damping factor to the closed loop system. The results show that the zero and gain settings are sufficient to ensure robust performance and stability with respect to various operating points. The technique used is the pole placement, which aims to put the system in closed loop poles in a specific region of the complex plane. Test results using a dynamic model of the F-16 aircraft are presented and discussed.

Keywords: F-16 Aircraft, linear matrix inequalities, pole placement, robust control.

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Authors: Shilpi Lavania

Abstract:

As the frequency of operation has attained a range of GHz and signal rise time continues to increase interconnect technology is suffering due to various high frequency effects as well as ground bounce problem. In some recent studies a high frequency effect i.e. skin effect has been modeled and its drawbacks have been discussed. This paper strives to make an impression on the advantage side of modeling skin effect for interconnect line. The proposed method has considered a CMOS with RC interconnect. Delay and noise considering ground bounce problem and with skin effect are discussed. The simulation results reveal an advantage of considering skin effect for minimization of ground bounce problem during the working of the model. Noise and delay variations with temperature are also presented.

Keywords: Interconnect, Skin effect, Ground Bounce, Delay, Noise.

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Authors: B. S. Yew , B. L. Ong , R. B. Ahmad

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This paper describes the performance of TCP Vegas over the wireless IPv6 network. The performance of TCP Vegas is evaluated using network simulator (ns-2). The simulation experiment investigates how packet spacing affects the network delay, network throughput and network efficiency of TCP Vegas. Moreover, we investigate how the variable FTP packet sizes affect the network performance. The result of the simulation experiment shows that as the packet spacing is implements, the network delay is reduces, network throughput and network efficiency is optimizes. As the FTP packet sizes increase, the ratio of delay per throughput decreases. From the result of experiment, we propose the appropriate packet size in transmitting file transfer protocol application using TCP Vegas with packet spacing enhancement over wireless IPv6 environment in ns-2. Additionally, we suggest the appropriate ratio in determining the appropriate RTT and buffer size in a network.

Keywords: TCP Vegas, Packet Spacing, Packet Size, Wireless IPv6, ns-2

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Authors: Sana Testouri, Karim Saadaoui, Mohamed Benrejeb

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This paper presents a Particle Swarm Optimization (PSO) method for determining the optimal parameters of a first-order controller for TCP/AQM system. The model TCP/AQM is described by a second-order system with time delay. First, the analytical approach, based on the D-decomposition method and Lemma of Kharitonov, is used to determine the stabilizing regions of a firstorder controller. Second, the optimal parameters of the controller are obtained by the PSO algorithm. Finally, the proposed method is implemented in the Network Simulator NS-2 and compared with the PI controller.

Keywords: AQM, first-order controller, time delay, stability, PSO.

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Authors: Mohammad Taghi Darvishi, Samad Kheybari

Abstract:

In this paper, the dynamics of a system of two van der Pol oscillators with delayed position and velocity is studied. We provide an approximate solution for this system using parameterexpansion method. Also, we obtain approximate values for frequencies of the system. The parameter-expansion method is more efficient than the perturbation method for this system because the method is independent of perturbation parameter assumption.

Keywords: Parameter-expansion method, coupled van der pol oscillator, time-delay system.

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Authors: Paul Y. Oh, Rares I. Stanciu

Abstract:

Cameras are often mounted on platforms that canmove like rovers, booms, gantries and aircraft. People operate suchplatforms to capture desired views of scene or target. To avoidcollisions with the environment and occlusions, such platforms oftenpossess redundant degrees-of-freedom. As a result, manipulatingsuch platforms demands much skill. Visual-servoing some degrees-of-freedom may reduce operator burden and improve tracking per-formance. This concept, which we call human-in-the-loop visual-servoing, is demonstrated in this paper and applies a Α-β-γ filter and feedforward controller to a broadcast camera boom.

Keywords: Computer vision, visual-servoing, man-machine sys-tems, human-in-the-loop control

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Authors: Pooja, Megha Kulshrestha, V. K. Banga, Parvinder S. Sandhu

Abstract:

To support mobility in ATM networks, a number of technical challenges need to be resolved. The impact of handoff schemes in terms of service disruption, handoff latency, cost implications and excess resources required during handoffs needs to be addressed. In this paper, a one phase handoff and route optimization solution using reserved PVCs between adjacent ATM switches to reroute connections during inter-switch handoff is studied. In the second phase, a distributed optimization process is initiated to optimally reroute handoff connections. The main objective is to find the optimal operating point at which to perform optimization subject to cost constraint with the purpose of reducing blocking probability of inter-switch handoff calls for delay tolerant traffic. We examine the relation between the required bandwidth resources and optimization rate. Also we calculate and study the handoff blocking probability due to lack of bandwidth for resources reserved to facilitate the rapid rerouting.

Keywords: Wireless ATM, Mobility, Latency, Optimization rateand Blocking Probability.

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Authors: Bhaskar M., Venkataramani B.

Abstract:

In the literature, surfing technique has been proposed for single ended wave-pipelined serial interconnects to increase the data transfer rate. In this paper a novel surfing technique is proposed for differential wave-pipelined serial interconnects, which uses a 'Controllable inverter pair' for surfing. To evaluate the efficiency of this technique, a transceiver with transmitter, receiver, delay locked loop (DLL) along with 40mm metal 4 interconnects using the proposed surfing technique is implemented in UMC 180nm technology and their performances are studied through post layout simulations. From the study, it is observed that the proposed scheme permits 1.875 times higher data transmission rate compared to the single ended scheme whose maximum data transfer rate is 1.33 GB/s. The proposed scheme has the ability to receive the correct data even with stuck-at-faults in the complementary line.

Keywords: Controllable inverter pair, differential interconnect, serial link, surfing, wave pipelining.

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Authors: Caspar von Seckendorff, Eldar Sultanow

Abstract:

Many studies have shown that parallelization decreases efficiency [1], [2]. There are many reasons for these decrements. This paper investigates those which appear in the context of parallel data integration. Integration processes generally cannot be allocated to packages of identical size (i. e. tasks of identical complexity). The reason for this is unknown heterogeneous input data which result in variable task lengths. Process delay is defined by the slowest processing node. It leads to a detrimental effect on the total processing time. With a real world example, this study will show that while process delay does initially increase with the introduction of more nodes it ultimately decreases again after a certain point. The example will make use of the cloud computing platform Hadoop and be run inside Amazon-s EC2 compute cloud. A stochastic model will be set up which can explain this effect.

Keywords: Process delay, speedup, efficiency, parallel computing, data integration, E-Commerce, Amazon Elastic Compute Cloud (EC2), Hadoop, Nutch.

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Authors: Venkatesh C., K. Shanti Swarup

Abstract:

This paper investigates the impact on operating time delay and relay maloperation when 1st,2nd and 3rd order analog antialiasing filters are used in numerical distance protection. RC filter with cut-off frequency 90 Hz is used. Simulations are carried out for different SIR (Source to line Impedance Ratio), load, fault type and fault conditions using SIMULINK, where the voltage and current signals are fed online to the developed numerical distance relay model. Matlab is used for plotting the impedance trajectory. Investigation results shows that, about 75 % of the simulated cases, numerical distance relay operating time is not increased even-though there is a time delay when higher order filters are used. Relay maloperation (selectivity) also reduces (increases) when higher order filters are used in numerical distance protection.

Keywords: Antialiasing, capacitive voltage transformers, delay estimation, discrete Fourier transform (DFT), distance measurement, low-pass filters, source to line impedance ratio (SIR), protective relaying.

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Authors: Farzana Yasmeen, Md. Nurul Huda, Md. Enamul Haque, Michihiro Aoki, Shigeki Yamada

Abstract:

Delay-Tolerant Networks (DTNs) are sparse, wireless networks where disconnections are common due to host mobility and low node density. The Message Ferrying (MF) scheme is a mobilityassisted paradigm to improve connectivity in DTN-like networks. A ferry or message ferry is a special node in the network which has a per-determined route in the deployed area and relays messages between mobile hosts (MHs) which are intermittently connected. Increased contact opportunities among mobile hosts and the ferry improve the performance of the network, both in terms of message delivery ratio and average end-end delay. However, due to the inherent mobility of mobile hosts and pre-determined periodicity of the message ferry, mobile hosts may often -miss- contact opportunities with a ferry. In this paper, we propose the combination of stationary ferry access points (FAPs) with MF routing to increase contact opportunities between mobile hosts and the MF and consequently improve the performance of the DTN. We also propose several placement models for deploying FAPs on MF routes. We evaluate the performance of the FAP placement models through comprehensive simulation. Our findings show that FAPs do improve the performance of MF-assisted DTNs and symmetric placement of FAPs outperforms other placement strategies.

Keywords: Service infrastructure, delay-tolerant network, messageferry routing, placement models.

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Authors: T.Sheela, Dr.J.Raja

Abstract:

Continuously growing needs for Internet applications that transmit massive amount of data have led to the emergence of high speed network. Data transfer must take place without any congestion and hence feedback parameters must be transferred from the receiver end to the sender end so as to restrict the sending rate in order to avoid congestion. Even though TCP tries to avoid congestion by restricting the sending rate and window size, it never announces the sender about the capacity of the data to be sent and also it reduces the window size by half at the time of congestion therefore resulting in the decrease of throughput, low utilization of the bandwidth and maximum delay. In this paper, XCP protocol is used and feedback parameters are calculated based on arrival rate, service rate, traffic rate and queue size and hence the receiver informs the sender about the throughput, capacity of the data to be sent and window size adjustment, resulting in no drastic decrease in window size, better increase in sending rate because of which there is a continuous flow of data without congestion. Therefore as a result of this, there is a maximum increase in throughput, high utilization of the bandwidth and minimum delay. The result of the proposed work is presented as a graph based on throughput, delay and window size. Thus in this paper, XCP protocol is well illustrated and the various parameters are thoroughly analyzed and adequately presented.

Keywords: Bandwidth-Delay Product, Congestion Control, Congestion Window, TCP/IP

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Authors: P.Ramanathan, P.T.Vanathi

Abstract:

Parallel Prefix addition is a technique for improving the speed of binary addition. Due to continuing integrating intensity and the growing needs of portable devices, low-power and highperformance designs are of prime importance. The classical parallel prefix adder structures presented in the literature over the years optimize for logic depth, area, fan-out and interconnect count of logic circuits. In this paper, a new architecture for performing 8-bit, 16-bit and 32-bit Parallel Prefix addition is proposed. The proposed prefix adder structures is compared with several classical adders of same bit width in terms of power, delay and number of computational nodes. The results reveal that the proposed structures have the least power delay product when compared with its peer existing Prefix adder structures. Tanner EDA tool was used for simulating the adder designs in the TSMC 180 nm and TSMC 130 nm technologies.

Keywords: Parallel Prefix Adder (PPA), Dot operator, Semi-Dotoperator, Complementary Metal Oxide Semiconductor (CMOS), Odd-dot operator, Even-dot operator, Odd-semi-dot operator andEven-semi-dot operator.

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Authors: Guo-Ming Sung, Naga Raju Naik R.

Abstract:

Paper presents a low power, high speed, sense-amplifier based flip-flop (SAFF). The flip-flop’s power con-sumption and delay are greatly reduced by employing a new conditionally precharge sense-amplifier stage and a single-ended latch stage. Glitch-free and contention-free latch operation is achieved by using a conditional cut-off strategy. The design uses fewer transistors, has a lower clock load, and has a simple structure, all of which contribute to a near-zero setup time. When compared to previous flip-flop structures proposed for similar input/output conditions, this design’s performance and overall PDP have improved. The post layout simulation of the circuit uses 2.91µW of power and has a delay of 65.82 ps. Overall, the power-delay product has seen some enhancements. Cadence Virtuoso Designing tool with CMOS 90nm technology are used for all designs.

Keywords: high-speed, low-power, flip-flop, sense-amplifier

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Authors: P.S. Prakash, S. Selvan

Abstract:

IP networks are evolving from data communication infrastructure into many real-time applications such as video conferencing, IP telephony and require stringent Quality of Service (QoS) requirements. A rudimentary issue in QoS routing is to find a path between a source-destination pair that satisfies two or more endto- end constraints and termed to be NP hard or complete. In this context, we present an algorithm Multi Constraint Path Problem Version 3 (MCPv3), where all constraints are approximated and return a feasible path in much quicker time. We present another algorithm namely Delay Coerced Multi Constrained Routing (DCMCR) where coerce one constraint and approximate the remaining constraints. Our algorithm returns a feasible path, if exists, in polynomial time between a source-destination pair whose first weight satisfied by the first constraint and every other weight is bounded by remaining constraints by a predefined approximation factor (a). We present our experimental results with different topologies and network conditions.

Keywords: Routing, Quality-of-Service (QoS), additive constraints, shortest path, delay coercion.

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Authors: Gulshan Sharma

Abstract:

This article presents the design of optimal automatic generation control (AGC) based on full state feedback control for a multi-area interconnected power system. An extra high voltage AC transmission line in parallel with a high voltage DC link is considered as an area interconnection between the areas. The optimal AGC are designed and implemented in the wake of 1% load perturbation in one of the areas and the system dynamic response plots for various system states are obtained to investigate the system dynamic performance. The pattern of closed-loop eigenvalues are also determined to analyze the system stability. From the investigations carried out in the work, it is revealed that the dynamic performance of the system under consideration has an appreciable improvement when a high voltage DC line is paralleled with an extra high voltage AC line as an interconnection between the areas. The investigation of closed-loop eigenvalues reveals that the system stability is ensured in all case studies carried out with the designed optimal AGC.

Keywords: Automatic generation control, area control error, DC link, optimal AGC regulator, closed-loop eigenvalues.

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Authors: Ararat Khachatryan, Davit Mirzoyan

Abstract:

In sub micrometer technology, the aging phenomenon starts to have a significant impact on the reliability of integrated circuits by bringing performance degradation. For that reason, it is important to have a capability to evaluate the aging effects accurately. This paper presents an accurate aging measurement approach based on phase-locked loop (PLL) and voltage-controlled oscillator (VCO) circuit. The architecture is rejecting the circuit self-aging effect from the characteristics of PLL, which is generating the frequency without any aging phenomena affects. The aging monitor is implemented in low power 32 nm CMOS technology, and occupies a pretty small area. Aging simulation results show that the proposed aging measurement circuit improves accuracy by about 2.8% at high temperature and 19.6% at high voltage.

Keywords: Nanoscale, aging, effect, NBTI, HCI.

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Authors: Ashu Ahuja, Shiv Narayan, Jagdish Kumar

Abstract:

This paper realized the 2-DOF controller structure for first order with time delay systems. The co-prime factorization is used to design observer based controller K(s), representing one degree of freedom. The problem is based on H∞ norm of mixed sensitivity and aims to achieve stability, robustness and disturbance rejection. Then, the other degree of freedom, prefilter F(s), is formulated as fixed structure polynomial controller to meet open loop processing of reference model. This model matching problem is solved by minimizing integral square error between reference model and proposed model. The feedback controller and prefilter designs are posed as optimization problem and solved using Particle Swarm Optimization (PSO). To show the efficiency of the designed approach different variety of processes are taken and compared for analysis.

Keywords: 2-DOF, integral square error, mixed sensitivity function, observer based controller, particle swarm optimization, prefilter.

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Authors: Mathias Marquardt, Peter Dünow, Sandra Baßler

Abstract:

The paper describes the use of subspace based identification methods for auto tuning of a state space control system. The plant is an unstable but self balancing transport robot. Because of the unstable character of the process it has to be identified from closed loop input-output data. Based on the identified model a state space controller combined with an observer is calculated. The subspace identification algorithm and the controller design procedure is combined to a auto tuning method. The capability of the approach was verified in a simulation experiments under different process conditions.

Keywords: Auto tuning, balanced robot, closed loop identification, subspace identification.

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Authors: Kejun Zhuang, Zhaohui Wen

Abstract:

This paper is concerned with a nonautonomous three species food chain model with Crowley–Martin type functional response and time delay. Using the Mawhin-s continuation theorem in theory of degree, sufficient conditions for existence of periodic solutions are obtained.

Keywords: Periodic solutions, coincidence degree, food chain model, Crowley–Martin functional response.

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Authors: Vipul M. Patel, H. B. Mehta

Abstract:

Closed Loop Pulsating Heat Pipe (CLPHP) is a passive two-phase heat transfer device having potential to achieve high heat transfer rates over conventional cooling techniques. It is found in electronics cooling due to its outstanding characteristics such as excellent heat transfer performance, simple, reliable, cost effective, compact structure and no external mechanical power requirement etc. Comprehensive understanding of the thermo-hydrodynamic mechanism of CLPHP is still lacking due to its contradictory results available in the literature. The present paper discusses the experimental study on 9 turn CLPHP. Inner and outer diameters of the copper tube are 2 mm and 4 mm respectively. The lengths of the evaporator, adiabatic and condenser sections are 40 mm, 100 mm and 50 mm respectively. Water is used as working fluid. The Filling Ratio (FR) is kept as 50% throughout the investigations. The gravitational effect is studied by placing the evaporator heater at different orientations such as horizontal (90 degree), vertical top (180 degree) and bottom (0 degree) as well as inclined top (135 degree) and bottom (45 degree). Heat input is supplied in the range of 10-50 Watt. Heat transfer mechanism is natural convection in the condenser section. Vacuum pump is used to evacuate the system up to 10^-5 bar. The results demonstrate the influence of input heat flux and gravity on the thermal performance of the CLPHP.

Keywords: Closed loop pulsating heat pipe, gravity, heat input, orientation.

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Authors: Qingqing Wang, Shouming Zhong

Abstract:

This paper deals with the problem of delay-dependent stability for neural networks with distributed delays. Some new sufficient condition are derived by constructing a novel Lyapunov-Krasovskii functional approach. The criteria are formulated in terms of a set of linear matrix inequalities, this is convenient for numerically checking the system stability using the powerful MATLAB LMI Toolbox. Moreover, in order to show the stability condition in this paper gives much less conservative results than those in the literature, numerical examples are considered.

Keywords: Neural networks, Globally asymptotic stability , LMI approach, Distributed delays.

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Authors: Ki-Jin Kim, Sanghoon Park, K. H. Ahn

Abstract:

This paper presents the 20-GHz fractional PLL (Phase Locked Loop) circuit for the next generation Wi-Fi by using 90 nm TSMC process. The newly suggested millimeter wave 16/17 pre-scalar is designed and verified by measurement to make the fractional PLL having a low quantization noise. The operational bandwidth of the 60 GHz system is 15 % of the carrier frequency which requires large value of Kv (VCO control gain) resulting in degradation of phase noise. To solve this problem, this paper adopts AFC (Automatic Frequency Controller) controlled 4-bit millimeter wave VCO with small value of Kv. Also constant Kv is implemented using 4-bit varactor bank. The measured operational bandwidth is 18.2 ~ 23.2 GHz which is 25 % of the carrier frequency. The phase noise of -58 and -96.2 dBc/Hz at 100 KHz and 1 MHz offset is measured respectively. The total power consumption of the PLL is only 30 mW.

Keywords: Millimeter Wave Fractional PLL, Wide band VCO, WPAN Transceiver.

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Authors: Allouche Moez, Souissi Mansour, Chaabane Mohamed, Mehdi Driss

Abstract:

This paper deals with the synthesis of fuzzy state feedback controller of induction motor with optimal performance. First, the Takagi-Sugeno (T-S) fuzzy model is employed to approximate a non linear system in the synchronous d-q frame rotating with electromagnetic field-oriented. Next, a fuzzy controller is designed to stabilise the induction motor and guaranteed a minimum disturbance attenuation level for the closed-loop system. The gains of fuzzy control are obtained by solving a set of Linear Matrix Inequality (LMI). Finally, simulation results are given to demonstrate the controller-s effectiveness.

Keywords: Rejection disturbance, fuzzy modelling, open-loop control, Fuzzy feedback controller, fuzzy observer, Linear Matrix Inequality (LMI)

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Authors: Sunil Jadav, Rajeevan Chandel Munish Vashishath

Abstract:

Today’s VLSI networks demands for high speed. And in this work the compact form mathematical model for current mode signalling in VLSI interconnects is presented.RLC interconnect line is modelled using characteristic impedance of transmission line and inductive effect. The on-chip inductance effect is dominant at lower technology node is emulated into an equivalent resistance. First order transfer function is designed using finite difference equation, Laplace transform and by applying the boundary conditions at the source and load termination. It has been observed that the dominant pole determines system response and delay in the proposed model. The novel proposed current mode model shows superior performance as compared to voltage mode signalling. Analysis shows that current mode signalling in VLSI interconnects provides 2.8 times better delay performance than voltage mode. Secondly the damping factor of a lumped RLC circuit is shown to be a useful figure of merit.

Keywords: Current Mode, Voltage Mode, VLSI Interconnect.

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Authors: Bo-Wei Song, Yun-Jung Lee

Abstract:

This paper presents an intention interface and controller for a wire-driven heavy object lifting system that assists the operator with moving a heavy object. The handler is designed to allow a comfortable working posture for the operator. Plus, as a human assistive system, the operator is involved in the control loop, where a fuzzy control system is used to consider the human control characteristics. The effectiveness and performance of the proposed system are proved by experiments.

Keywords: Fuzzy controller, Handler design, Heavy object lifting system, Human-assistive device, Human-in-the-loop system.

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Authors: V. K. Rattan, Baljinder K. Gill, Seema Kapoor

Abstract:

Isobaric vapor-liquid equilibrium measurements are reported for binary mixture of 2-Methyltetrahydrofuran and Cumene at 97.3 kPa. The data were obtained using a vapor recirculating type (modified Othmer's) equilibrium still. The mixture shows slight negative deviation from ideality. The system does not form an azeotrope. The experimental data obtained in this study are thermodynamically consistent according to the Herington test. The activity coefficients have been satisfactorily correlated by means of the Margules, and NRTL equations. Excess Gibbs free energy has been calculated from the experimental data. The values of activity coefficients have also been obtained by the UNIFAC group contribution method.

Keywords: Binary mixture, 2-Methyltetrahydrofuran, Cumene, Vapor-liquid equilibrium, UNIFAC, Excess Gibbs free energy.

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Authors: Ankit Mitra

Abstract:

Speed, power consumption and area, are some of the most important factors of concern in modern day memory design. As we move towards Deep Sub-Micron Technologies, the problems of leakage current, noise and cell stability due to physical parameter variation becomes more pronounced. In this paper we have designed an 8T Read Decoupled Dual Port SRAM Cell with Dual Threshold Voltage and characterized it in terms of read and write delay, read and write noise margins, Data Retention Voltage and Leakage Current. Read Decoupling improves the Read Noise Margin and static power dissipation is reduced by using Dual-V_t transistors. The results obtained are compared with existing 6T, 8T, 9T SRAM Cells, which shows the superiority of the proposed design. The Cell is designed and simulated in TSPICE using 90nm CMOS process.

Keywords: CMOS, Dual-Port, Data Retention Voltage, 8T SRAM, Leakage Current, Noise Margin, Loop-cutting, Single-ended.

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Authors: V. T. S. Dao, T. G. Etoh, C. Vo Le, H. D. Nguyen, K. Takehara, T. Akino, K. Nishi

Abstract:

Since 2004, we have been developing an in-situ storage image sensor (ISIS) that captures more than 100 consecutive images at a frame rate of 10 Mfps with ultra-high sensitivity as well as the video camera for use with this ISIS. Currently, basic research is continuing in an attempt to increase the frame rate up to 100 Mfps and above. In order to suppress electro-magnetic noise at such high frequency, a digital-noiseless imaging transfer scheme has been developed utilizing solely sinusoidal driving voltages. This paper presents highly efficient-yet-accurate expressions to estimate attenuation as well as phase delay of driving voltages through RC networks of an ultra-high-speed image sensor. Elmore metric for a fundamental RC chain is employed as the first-order approximation. By application of dimensional analysis to SPICE data, we found a simple expression that significantly improves the accuracy of the approximation. Similarly, another simple closed-form model to estimate phase delay through fundamental RC networks is also obtained. Estimation error of both expressions is much less than previous works, only less 2% for most of the cases . The framework of this analysis can be extended to address similar issues of other VLSI structures.

Keywords: Dimensional Analysis, ISIS, Digital-noiseless, RC network, Attenuation, Phase Delay, Elmore model

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Authors: Pichayut Peerasathien, Hiroshi Nagahashi

Abstract:

Subdivision is a method to create a smooth surface from a coarse mesh by subdividing the entire mesh. The conventional ways to compute and render surfaces are inconvenient both in terms of memory and computational time as the number of meshes will increase exponentially. An adaptive subdivision is the way to reduce the computational time and memory by subdividing only certain selected areas. In this paper, a new adaptive subdivision method for triangle meshes is introduced. This method defines a new adaptive subdivision rules by considering the properties of each triangle's neighbors and is embedded in a traditional Loop's subdivision. It prevents some undesirable side effects that appear in the conventional adaptive ways. Models that were subdivided by our method are compared with other adaptive subdivision methods

Keywords: Subdivision, loop subdivision, handle cracks, smooth surface.

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