Search results for: Average Delay

Authors: Shobha Sharma, Amita Dev

Abstract:

This research paper presents highly optimized barrel shifter at 22nm Hi K metal gate strained Si technology node. This barrel shifter is having a unique combination of static and dynamic body bias which gives lowest power delay product. This power delay product is compared with the same circuit at same technology node with static forward biasing at ‘supply/2’ and also with normal reverse substrate biasing and still found to be the lowest. The power delay product of this barrel sifter is .39362X10-17J and is lowered by approximately 78% to reference proposed barrel shifter at 32nm bulk CMOS technology. Power delay product of barrel shifter at 22nm Hi K Metal gate technology with normal reverse substrate bias is 2.97186933X10-17J and can be compared with this design’s PDP of .39362X10-17J. This design uses both static and dynamic substrate biasing and also has approximately 96% lower power delay product compared to only forward body biased at half of supply voltage. The NMOS model used are predictive technology models of Arizona state university and the simulations to be carried out using HSPICE simulator.

Keywords: Dynamic body biasing, highly optimized barrel shifter, PDP, Static body biasing.

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Authors: Kejun Zhuang, Hailong Zhu

Abstract:

The dynamics of a delayed mathematical model for Hes1 oscillatory expression are investigated. The linear stability of positive equilibrium and existence of local Hopf bifurcation are studied. Moreover, the global existence of large periodic solutions has been established due to the global bifurcation theorem.

Keywords: Hes1, Hopf bifurcation, time delay, transcriptional repression loop

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Authors: S. Al-Sowayan, K. L. Lear

Abstract:

A new technique to quantify the differential mode delay (DMD) in multimode fiber (MMF) is been presented. The technique measures DMD based on angular launch and measurements of the difference in modal delay using variable apertures at the fiber face. The result of the angular spatial filtering revealed less excitation of higher order modes when the laser beam is filtered at higher angles. This result would indicate that DMD profiles would experience a data pattern dependency.

Keywords: Fiber measurements, Fiber optic communications

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Authors: Ali Al-Zughaibi, Huw Davies

Abstract:

The purpose of this paper is to present a modeling and control of a quarter-car active suspension system with unknown mass, unknown time-delay and road disturbance. The objective of designing the controller is to derive a control law to achieve stability of the system and convergence that can considerably improve ride comfort and road disturbance handling. This is accomplished by using Routh-Hurwitz criterion based on defined parameters. Mathematical proof is given to show the ability of the designed controller to ensure the target of design, implementation with the active suspension system and enhancement dispersion oscillation of the system despite these problems. Simulations were also performed to control quarter car suspension, where the results obtained from these simulations verify the validity of the proposed design.

Keywords: Active suspension system, disturbance rejection, dynamic uncertainty, time-delay.

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Authors: Xinli Zhang

Abstract:

In this paper, we consider the nonlinear delay dynamic system xΔ(t) = p(t)f1(y(t)), yΔ(t) = −q(t)f2(x(t − τ )). We obtain some necessary and sufficient conditions for the existence of nonoscillatory solutions with special asymptotic properties of the system. We generalize the known results in the literature. One example is given to illustrate the results.

Keywords: Dynamic system, oscillation, time scales, two-dimensional.

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Authors: Pengdi Diao, Zhuo Wang, Zundong Zhang, Hua Cheng

Abstract:

In the urban traffic network, the intersections are the “bottleneck point" of road network capacity. And the arterials are the main body in road network and the key factor which guarantees the normal operation of the city-s social and economic activities. The rapid increase in vehicles leads to seriously traffic jam and cause the increment of vehicles- delay. Most cities of our country are traditional single control system, which cannot meet the need for the city traffic any longer. In this paper, Synchro6.0 as a platform to minimize the intersection delay, optimizesingle signal cycle and split for Zhonghua Street in Handan City. Meanwhile, linear control system uses to optimize the phase for the t arterial road in this system. Comparing before and after use the control, capacities and service levels of this road and the adjacent road have improved significantly.

Keywords: linear control system; delay mode; signal optimization; synchro6.0 simulation

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Authors: P. Guayjarernpanishkand, T. Mayureesawan

Abstract:

This paper presents a comparison of average outgoing quality limit of the MCSP-2-C plan with MCSP-C when MCSP-2-C has been developed from MCSP-C. The parameters used in MCSP-2- C are: i (the clearance number), c (the acceptance number), m (the number of conforming units to be found before allowing c nonconforming units in the sampling inspection), f1 and f2 (the sampling frequency at level 1 and 2, respectively). The average outgoing quality limit (AOQL) values from two plans were compared and we found that for all sets of i, r, and c values, MCSP-2-C gives higher values than MCSP-C. For all sets of i, r, and c values, the average outgoing quality values of MCSP-C and MCSP-2-C are similar when p is low or high but is difference when p is moderate.

Keywords: average outgoing quality, average outgoing quality limit, continuous sampling plan.

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Authors: P. S. Prakash, S. Selvan

Abstract:

QoS Routing aims to find paths between senders and receivers satisfying the QoS requirements of the application which efficiently using the network resources and underlying routing algorithm to be able to find low-cost paths that satisfy given QoS constraints. The problem of finding least-cost routing is known to be NP-hard or complete and some algorithms have been proposed to find a near optimal solution. But these heuristics or algorithms either impose relationships among the link metrics to reduce the complexity of the problem which may limit the general applicability of the heuristic, or are too costly in terms of execution time to be applicable to large networks. In this paper, we concentrate an algorithm that finds a near-optimal solution fast and we named this algorithm as optimized Delay Constrained Routing (ODCR), which uses an adaptive path weight function together with an additional constraint imposed on the path cost, to restrict search space and hence ODCR finds near optimal solution in much quicker time.

Keywords: QoS, Delay, Routing, Optimization.

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Authors: Govindaraj Ramanathan

Abstract:

The time delay and the structural stability are major issues in big size projects due to several factors. Improper planning and poor coordination lead to delay in construction, which sometimes result in reworking or rebuilding. This definitely increases the cost and time of project. This situation stresses the structural engineers to plan out of the limits of contemporary technology utilizing non-chronological approach with creative ideas. One of the strategies to solve this issue is through structural integrity solutions in a cost-effective way. We have faced several problems in a project worth 470 million USD, and one such issue is crane girder installation with composite steel beams. We have applied structural integrity approach with the proper and revised planning schedule to solve the problem efficiently with minimal expenses.

Keywords: Construction management, delay, non-chronological approach, composite beam, structural integrity.

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Authors: Padmanabhan Balasubramanian, Karthik Anantha

Abstract:

Structural representation and technology mapping of a Boolean function is an important problem in the design of nonregenerative digital logic circuits (also called combinational logic circuits). Library aware function manipulation offers a solution to this problem. Compact multi-level representation of binary networks, based on simple circuit structures, such as AND-Inverter Graphs (AIG) [1] [5], NAND Graphs, OR-Inverter Graphs (OIG), AND-OR Graphs (AOG), AND-OR-Inverter Graphs (AOIG), AND-XORInverter Graphs, Reduced Boolean Circuits [8] does exist in literature. In this work, we discuss a novel and efficient graph realization for combinational logic circuits, represented using a NAND-NOR-Inverter Graph (NNIG), which is composed of only two-input NAND (NAND2), NOR (NOR2) and inverter (INV) cells. The networks are constructed on the basis of irredundant disjunctive and conjunctive normal forms, after factoring, comprising terms with minimum support. Construction of a NNIG for a non-regenerative function in normal form would be straightforward, whereas for the complementary phase, it would be developed by considering a virtual instance of the function. However, the choice of best NNIG for a given function would be based upon literal count, cell count and DAG node count of the implementation at the technology independent stage. In case of a tie, the final decision would be made after extracting the physical design parameters. We have considered AIG representation for reduced disjunctive normal form and the best of OIG/AOG/AOIG for the minimized conjunctive normal forms. This is necessitated due to the nature of certain functions, such as Achilles- heel functions. NNIGs are found to exhibit 3.97% lesser node count compared to AIGs and OIG/AOG/AOIGs; consume 23.74% and 10.79% lesser library cells than AIGs and OIG/AOG/AOIGs for the various samples considered. We compare the power efficiency and delay improvement achieved by optimal NNIGs over minimal AIGs and OIG/AOG/AOIGs for various case studies. In comparison with functionally equivalent, irredundant and compact AIGs, NNIGs report mean savings in power and delay of 43.71% and 25.85% respectively, after technology mapping with a 0.35 micron TSMC CMOS process. For a comparison with OIG/AOG/AOIGs, NNIGs demonstrate average savings in power and delay by 47.51% and 24.83%. With respect to device count needed for implementation with static CMOS logic style, NNIGs utilize 37.85% and 33.95% lesser transistors than their AIG and OIG/AOG/AOIG counterparts.

Keywords: AND-Inverter Graph, OR-Inverter Graph, DirectedAcyclic Graph, Low power design, Delay optimization.

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Authors: Yanling Zhu, Kai Wang

Abstract:

By means of Mawhin’s continuation theorem, we study a kind of third-order p-Laplacian functional differential equation with distributed delay in the form: ϕp(x (t)) = g  t,  0 −τ x(t + s) dα(s)  + e(t), some criteria to guarantee the existence of periodic solutions are obtained.

Keywords: p–Laplacian, distributed delay, periodic solution, Mawhin's continuation theorem.

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Authors: Jirawat Thaenthong, Steven Gordon

Abstract:

MANEMO is the integration of Network Mobility (NEMO) and Mobile Ad Hoc Network (MANET). A MANEMO node has an interface to both a MANET and NEMO network, and therefore should choose the optimal interface for packet delivery, however such a handover between interfaces will introduce packet loss. We define the steps necessary for a MANEMO handover, using Mobile IP and NEMO to signal the new binding to the relevant Home Agent(s). The handover steps aim to minimize the packet loss by avoiding waiting for Duplicate Address Detection and Neighbour Unreachability Detection. We present expressions for handover delay and packet loss, and then use numerical examples to evaluate a MANEMO handover. The analysis shows how the packet loss depends on level of nesting within NEMO, the delay between Home Agents and the load on the MANET, and hence can be used to developing optimal MANEMO handover algorithms.

Keywords: IP mobility, handover, MANET, network mobility

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Authors: K. Petcharat, Y. Areepong, S. Sukparungsri, G. Mititelu

Abstract:

These paper, we approximate the average run length (ARL) for CUSUM chart when observation are an exponential first order moving average sequence (EMA1). We used Gauss-Legendre numerical scheme for integral equations (IE) method for approximate ARL0 and ARL1, where ARL in control and out of control, respectively. We compared the results from IE method and exact solution such that the two methods perform good agreement.

Keywords: Cumulative Sum Chart, Moving Average Observation, Average Run Length, Numerical Approximations.

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Authors: Yong Li

Abstract:

The paper is concerned with the existence of solution of nonlinear second order neutral stochastic differential inclusions with infinite delay in a Hilbert Space. Sufficient conditions for the existence are obtained by using a fixed point theorem for condensing maps.

Keywords: Mild solution, Convex multivalued map, Neutral stochastic differential inclusions.

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Authors: Thomas Canhao Xu, Bo Yang, Alexander Wei Yin, Pasi Liljeberg, Hannu Tenhunen

Abstract:

With the increasing number of on-chip components and the critical requirement for processing power, Chip Multiprocessor (CMP) has gained wide acceptance in both academia and industry during the last decade. However, the conventional bus-based onchip communication schemes suffer from very high communication delay and low scalability in large scale systems. Network-on-Chip (NoC) has been proposed to solve the bottleneck of parallel onchip communications by applying different network topologies which separate the communication phase from the computation phase. Observing that the memory bandwidth of the communication between on-chip components and off-chip memory has become a critical problem even in NoC based systems, in this paper, we propose a novel 3D NoC with on-chip Dynamic Random Access Memory (DRAM) in which different layers are dedicated to different functionalities such as processors, cache or memory. Results show that, by using our proposed architecture, average link utilization has reduced by 10.25% for SPLASH-2 workloads. Our proposed design costs 1.12% less execution cycles than the traditional design on average.

Keywords: 3D integration, network-on-chip, memory-on-chip, DRAM, chip multiprocessor.

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Authors: G.Ramana Murthy, C.Senthilpari, P.Velrajkumar, Lim Tien Sze

Abstract:

The proposed multiplexer-based novel 1-bit full adder cell is schematized by using DSCH2 and its layout is generated by using microwind VLSI CAD tool. The adder cell layout interconnect analysis is performed by using BSIM4 layout analyzer. The adder circuit is compared with other six existing adder circuits for parametric analysis. The proposed adder cell gives better performance than the other existing six adder circuits in terms of power, propagation delay and PDP. The proposed adder circuit is further analyzed for interconnect analysis, which gives better performance than other adder circuits in terms of layout thickness, width and height.

Keywords: Full Adder, Interconnect Analysis, Low-Power, Multiplexer, Propagation Delay, Parametric Analysis.

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Authors: S. Balaji, M. Rajaram, Y. Harold Robinson, E. Golden Julie

Abstract:

Delay Tolerant Networks (DTN) which have sufficient state information include trajectory and contact information, to protect routing efficiency. However, state information is dynamic and hard to obtain without a global and/or long-term collection process. To deal with these problems, the internal social features of each node are introduced in the network to perform the routing process. This type of application is motivated from several human contact networks where people contact each other more frequently if they have more social features in common. Two unique processes were developed for this process; social feature extraction and multipath routing. The routing method then becomes a hypercube–based feature matching process. Furthermore, the effectiveness of multipath routing is evaluated and compared to that of single-path routing.

Keywords: Delay tolerant networks, entropy, human contact networks, hyper cubes, multipath Routing, social features.

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Authors: Daiming Wang

Abstract:

In this paper, a neutral impulsive competition system with distributed delays is studied by using Mawhin-s coincidence degree theory and the mean value theorem of differential calculus. Sufficient conditions on the existence of positive periodic solution of the system are obtained.

Keywords: Neutral impulsive delay system, competitive system, coincidence degree, periodic solution, existence.

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Authors: Amir Khalid, B. Manshoor

Abstract:

The mixture formation prior to the ignition process plays as a key element in the diesel combustion. Parametric studies of mixture formation and ignition process in various injection parameter has received considerable attention in potential for reducing emissions. Purpose of this study is to clarify the effects of injection pressure on mixture formation and ignition especially during ignition delay period, which have to be significantly influences throughout the combustion process and exhaust emissions. This study investigated the effects of injection pressure on diesel combustion fundamentally using rapid compression machine. The detail behavior of mixture formation during ignition delay period was investigated using the schlieren photography system with a high speed camera. This method can capture spray evaporation, spray interference, mixture formation and flame development clearly with real images. Ignition process and flame development were investigated by direct photography method using a light sensitive high-speed color digital video camera. The injection pressure and air motion are important variable that strongly affect to the fuel evaporation, endothermic and prolysis process during ignition delay. An increased injection pressure makes spray tip penetration longer and promotes a greater amount of fuel-air mixing occurs during ignition delay. A greater quantity of fuel prepared during ignition delay period thus predominantly promotes more rapid heat release.

Keywords: Mixture Formation, Diesel Combustion, Ignition Process, Spray, Rapid Compression Machine.

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Authors: Yngvar Berg, Omid Mirmotahari

Abstract:

In this paper we ultra low-voltage and high speed CMOS domino logic. For supply voltages below 500mV the delay for a ultra low-voltage NAND2 gate is aproximately 10% of a complementary CMOS inverter. Furthermore, the delay variations due to mismatch is much less than for conventional CMOS. Differential domino gates for AND/NAND and OR/NOR operation are presented.

Keywords: Low-voltage, high-speed, NAND, NOR, CMOS.

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Authors: Xiaoyan Dou, Yongkun Li

Abstract:

In this paper, we consider a food-limited population model with delay and feedback control. By applying the comparison theorem of the differential equation and constructing a suitable Lyapunov functional, sufficient conditions which guarantee the permanence and existence of a unique globally attractive positive almost periodic solution of the system are obtained.

Keywords: Almost periodic solution, food-limited population, feedback control, permanence.

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Authors: Seyed Saeed Changiz Rezaei, Babak Hossein Khalaj

Abstract:

As the demand for higher capacity in a cellular environment increases, the cell size decreases. This fact makes the role of suitable handoff algorithms to reduce both number of handoffs and handoff delay more important. In this paper we show that applying the grey prediction technique for handoff leads to considerable decrease in handoff delay with using a small number of handoffs, compared with traditional hystersis based handoff algorithms.

Keywords: Cellular network, Grey prediction, Handoff.

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Authors: Sui Xin, Li Chunsheng, Tian Di

Abstract:

Short message integrated distributed monitoring systems (SM-DMS) are growing rapidly in wireless communication applications in various areas, such as electromagnetic field (EMF) management, wastewater monitoring, and air pollution supervision, etc. However, delay in short messages often makes the data embedded in SM-DMS transmit unreliably. Moreover, there are few regulations dealing with this problem in SMS transmission protocols. In this study, based on the analysis of the command and data requirements in the SM-DMS, we developed a processing model for the control center to solve the delay problem in data transmission. Three components of the model: the data transmission protocol, the receiving buffer pool method, and the timer mechanism were described in detail. Discussions on adjusting the threshold parameter in the timer mechanism were presented for the adaptive performance during the runtime of the SM-DMS. This model optimized the data transmission reliability in SM-DMS, and provided a supplement to the data transmission reliability protocols at the application level.

Keywords: Delay, SMS, reliability, distributed monitoringsystem (DMS), wireless communication.

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Authors: Shilpi Lavania

Abstract:

As the frequency of operation has attained a range of GHz and signal rise time continues to increase interconnect technology is suffering due to various high frequency effects as well as ground bounce problem. In some recent studies a high frequency effect i.e. skin effect has been modeled and its drawbacks have been discussed. This paper strives to make an impression on the advantage side of modeling skin effect for interconnect line. The proposed method has considered a CMOS with RC interconnect. Delay and noise considering ground bounce problem and with skin effect are discussed. The simulation results reveal an advantage of considering skin effect for minimization of ground bounce problem during the working of the model. Noise and delay variations with temperature are also presented.

Keywords: Interconnect, Skin effect, Ground Bounce, Delay, Noise.

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Authors: B. S. Yew , B. L. Ong , R. B. Ahmad

Abstract:

This paper describes the performance of TCP Vegas over the wireless IPv6 network. The performance of TCP Vegas is evaluated using network simulator (ns-2). The simulation experiment investigates how packet spacing affects the network delay, network throughput and network efficiency of TCP Vegas. Moreover, we investigate how the variable FTP packet sizes affect the network performance. The result of the simulation experiment shows that as the packet spacing is implements, the network delay is reduces, network throughput and network efficiency is optimizes. As the FTP packet sizes increase, the ratio of delay per throughput decreases. From the result of experiment, we propose the appropriate packet size in transmitting file transfer protocol application using TCP Vegas with packet spacing enhancement over wireless IPv6 environment in ns-2. Additionally, we suggest the appropriate ratio in determining the appropriate RTT and buffer size in a network.

Keywords: TCP Vegas, Packet Spacing, Packet Size, Wireless IPv6, ns-2

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Authors: Sana Testouri, Karim Saadaoui, Mohamed Benrejeb

Abstract:

This paper presents a Particle Swarm Optimization (PSO) method for determining the optimal parameters of a first-order controller for TCP/AQM system. The model TCP/AQM is described by a second-order system with time delay. First, the analytical approach, based on the D-decomposition method and Lemma of Kharitonov, is used to determine the stabilizing regions of a firstorder controller. Second, the optimal parameters of the controller are obtained by the PSO algorithm. Finally, the proposed method is implemented in the Network Simulator NS-2 and compared with the PI controller.

Keywords: AQM, first-order controller, time delay, stability, PSO.

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Authors: Mohammad Taghi Darvishi, Samad Kheybari

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In this paper, the dynamics of a system of two van der Pol oscillators with delayed position and velocity is studied. We provide an approximate solution for this system using parameterexpansion method. Also, we obtain approximate values for frequencies of the system. The parameter-expansion method is more efficient than the perturbation method for this system because the method is independent of perturbation parameter assumption.

Keywords: Parameter-expansion method, coupled van der pol oscillator, time-delay system.

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Authors: Caspar von Seckendorff, Eldar Sultanow

Abstract:

Many studies have shown that parallelization decreases efficiency [1], [2]. There are many reasons for these decrements. This paper investigates those which appear in the context of parallel data integration. Integration processes generally cannot be allocated to packages of identical size (i. e. tasks of identical complexity). The reason for this is unknown heterogeneous input data which result in variable task lengths. Process delay is defined by the slowest processing node. It leads to a detrimental effect on the total processing time. With a real world example, this study will show that while process delay does initially increase with the introduction of more nodes it ultimately decreases again after a certain point. The example will make use of the cloud computing platform Hadoop and be run inside Amazon-s EC2 compute cloud. A stochastic model will be set up which can explain this effect.

Keywords: Process delay, speedup, efficiency, parallel computing, data integration, E-Commerce, Amazon Elastic Compute Cloud (EC2), Hadoop, Nutch.

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Authors: Venkatesh C., K. Shanti Swarup

Abstract:

This paper investigates the impact on operating time delay and relay maloperation when 1st,2nd and 3rd order analog antialiasing filters are used in numerical distance protection. RC filter with cut-off frequency 90 Hz is used. Simulations are carried out for different SIR (Source to line Impedance Ratio), load, fault type and fault conditions using SIMULINK, where the voltage and current signals are fed online to the developed numerical distance relay model. Matlab is used for plotting the impedance trajectory. Investigation results shows that, about 75 % of the simulated cases, numerical distance relay operating time is not increased even-though there is a time delay when higher order filters are used. Relay maloperation (selectivity) also reduces (increases) when higher order filters are used in numerical distance protection.

Keywords: Antialiasing, capacitive voltage transformers, delay estimation, discrete Fourier transform (DFT), distance measurement, low-pass filters, source to line impedance ratio (SIR), protective relaying.

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Authors: T.Sheela, Dr.J.Raja

Abstract:

Continuously growing needs for Internet applications that transmit massive amount of data have led to the emergence of high speed network. Data transfer must take place without any congestion and hence feedback parameters must be transferred from the receiver end to the sender end so as to restrict the sending rate in order to avoid congestion. Even though TCP tries to avoid congestion by restricting the sending rate and window size, it never announces the sender about the capacity of the data to be sent and also it reduces the window size by half at the time of congestion therefore resulting in the decrease of throughput, low utilization of the bandwidth and maximum delay. In this paper, XCP protocol is used and feedback parameters are calculated based on arrival rate, service rate, traffic rate and queue size and hence the receiver informs the sender about the throughput, capacity of the data to be sent and window size adjustment, resulting in no drastic decrease in window size, better increase in sending rate because of which there is a continuous flow of data without congestion. Therefore as a result of this, there is a maximum increase in throughput, high utilization of the bandwidth and minimum delay. The result of the proposed work is presented as a graph based on throughput, delay and window size. Thus in this paper, XCP protocol is well illustrated and the various parameters are thoroughly analyzed and adequately presented.

Keywords: Bandwidth-Delay Product, Congestion Control, Congestion Window, TCP/IP

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