Search results for: FieldProgrammable Gate Array (FPGA)

Authors: Noha M. Rashad, W. Swelam, M. H. Abd ElAzeem

Abstract:

A simple design of array antenna is presented in this paper, supporting millimeter wave applications which can be used in short range wireless communications such as 5G applications. This design enhances the use of V-band, according to IEEE standards, as the antenna works in the 70 GHz band with bandwidth more than 11 GHz and peak gain more than 13 dBi. The design is simulated using different numerical techniques achieving a very good agreement.

Keywords: 5G Technology, array antenna, microstrip, millimeter wave.

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Authors: Maja Sarevska, Abdel-Badeeh M. Salem

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This paper considers the problem of Null-Steering beamforming using Neural Network (NN) approach for antenna array system. Two cases are presented. First, unlike the other authors, the estimated Direction Of Arrivals (DOAs) are used for antenna array weights NN-based determination and the imprecise DOAs estimations are taken into account. Second, the blind null-steering beamforming is presented. In this case the antenna array outputs are presented at the input of the NN without DOAs estimation. The results of computer simulations will show much better relative mean error performances of the first NN approach compared to the NNbased blind beamforming.

Keywords: Beamforming, DOAs, neural network.

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Authors: Ju-Hong Lee, Ching-Wei Liao, Kun-Che Lee

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This paper deals with the problem of using antenna sensors for adaptive beamforming in the presence of random steering mismatch. We present an efficient adaptive array beamformer with robustness to deal with the considered problem. The robustness of the proposed beamformer comes from the efficient designation of the steering vector. Using the received array data vector, we construct an appropriate correlation matrix associated with the received array data vector and a correlation matrix associated with signal sources. Then, the eigenvector associated with the largest eigenvalue of the constructed signal correlation matrix is designated as an appropriate estimate of the steering vector. Finally, the adaptive weight vector required for adaptive beamforming is obtained by using the estimated steering vector and the constructed correlation matrix of the array data vector. Simulation results confirm the effectiveness of the proposed method.

Keywords: Adaptive beamforming, antenna array, linearly constrained minimum variance, robustness, steering vector.

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Authors: Mustafa Abdalla, Khaled A. Madi, Rajab Farhat

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An array antenna system with innovative signal processing can improve the resolution of a source direction of arrival (DoA) estimation. High resolution techniques take the advantage of array antenna structures to better process the incoming waves. They also have the capability to identify the direction of multiple targets. This paper investigates performance of the DOA estimation algorithm namely; Capon and MUSIC on the uniform linear array (ULA). The simulation results show that in Capon and MUSIC algorithm the resolution of the DOA techniques improves as number of snapshots, number of array elements, signal-to-noise ratio and separation angle between the two sources θ increases.

Keywords: Antenna array, Capon, MUSIC, Direction-of-arrival estimation, signal processing, uniform linear arrays.

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Authors: Somayeh Komeylian

Abstract:

Array signal processing techniques have been recently developing in a variety application of the performance enhancement of receivers by refraining the power of jamming and interference signals. In this scenario, biases induced to the antenna array receiver degrade significantly the accurate estimation of the carrier phase. Owing to the integration of frequency becomes the carrier phase, we have obtained the unbiased doppler frequency for the high precision estimation of carrier phase. The unbiased characteristic of Doppler frequency to the power jamming and the other interference signals allows achieving the highly accurate estimation of phase carrier. In this study, we have rigorously investigated the unbiased characteristic of Doppler frequency to the variation of the antenna array geometries. The simulation results have efficiently verified that the Doppler frequency remains also unbiased and accurate to the variation of antenna array geometries.

Keywords: Array signal processing, unbiased Doppler frequency, GNSS, carrier phase, slowly fluctuating point target.

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Authors: Olesya Bolkhovskaya, Alexey Davydov, Alexander Maltsev

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In this paper, approach to incoherent signal detection in multi-element antenna array are researched and modeled. Two types of useful signals with unknown wavefront were considered: first one, deterministic (Barker code), and second one, random (Gaussian distribution). The derivation of the sufficient statistics took into account the linearity of the antenna array. The performance characteristics and detecting curves are modeled and compared for different useful signals parameters and for different number of elements of the antenna array. Results of researches in case of some additional conditions can be applied to a digital communications systems.

Keywords: Antenna array, detection curves, performance characteristics, quadrature processing, signal detection.

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Authors: Rishikesh Pandey, Maneesha Gupta

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A new low-voltage floating gate MOSFET (FGMOS) based squarer using square law characteristic of the FGMOS is proposed in this paper. The major advantages of the squarer are simplicity, rail-to-rail input dynamic range, low total harmonic distortion, and low power consumption. The proposed circuit is biased without body effect. The circuit is designed and simulated using SPICE in 0.25μm CMOS technology. The squarer is operated at the supply voltages of ±0.75V . The total harmonic distortion (THD) for the input signal 0.75Vpp at 25 KHz, and maximum power consumption were found to be less than 1% and 319μW respectively.

Keywords: Analog signal processing, floating gate MOSFETs, low-voltage, Spice, squarer.

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Authors: Y. J. Huang, J. D. Yu, B. W. Hong, C. H. Tai, T. C. Kuo

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In this paper, a multi-agent robot system is presented. The system consists of four robots. The developed robots are able to automatically enter and patrol a harmful environment, such as the building infected with virus or the factory with leaking hazardous gas. Further, every robot is able to perform obstacle avoidance and search for the victims. Several operation modes are designed: remote control, obstacle avoidance, automatic searching, and so on.

Keywords: autonomous robot, field programmable gate array, obstacle avoidance, ultrasonic sensor, wireless communication.

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Authors: Sheng Ge, Jian-Peng Wang, Hai-Ying Tang, Xi Xiao, Wen Wu

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This research proposed a new design of helmet-shaped array transcranial magnetic stimulation coil system. It was constructed using several sagittal directional wires and several coronal directional wires. By varying the current direction and strength on each wire, this array coil system could be constructed into the circular coil and figure-eight coil of different size. Also, this proposed coil system can flexibly not only change the stimulation location, range, type and strength, but also change the shape and the channel number of coil dynamically.

Keywords: TMS, circular coils, figure-eight coil, array coil

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Authors: Priyanka Malik A, Rishu Chaujar B, Mridula Gupta C, R.S. Gupta D

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In this paper, for the first time, a two-dimensional (2D) analytical drain current model for sub-100 nm multi-layered gate material engineered trapezoidal recessed channel (MLGMETRC) MOSFET: a novel design is presented and investigated using ATLAS and DEVEDIT device simulators, to mitigate the large gate leakages and increased standby power consumption that arise due to continued scaling of SiO2-based gate dielectrics. The twodimensional (2D) analytical model based on solution of Poisson-s equation in cylindrical coordinates, utilizing the cylindrical approximation, has been developed which evaluate the surface potential, electric field, drain current, switching metric: ION/IOFF ratio and transconductance for the proposed design. A good agreement between the model predictions and device simulation results is obtained, verifying the accuracy of the proposed analytical model.

Keywords: ATLAS, DEVEDIT, NJD, MLGME- TRCMOSFET.

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Authors: Fatemeh Karimi, Morteza Fathipour, Hamdam Ghanatian, Vala Fathipour

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In this paper we investigate the electrical characteristics of a new structure of gate all around strained silicon nanowire field effect transistors (FETs) with dual dielectrics by changing the radius (RSiGe) of silicon-germanium (SiGe) wire and gate dielectric. Indeed the effect of high-κ dielectric on Field Induced Barrier Lowering (FIBL) has been studied. Due to the higher electron mobility in tensile strained silicon, the n-type FETs with strained silicon channel have better drain current compare with the pure Si one. In this structure gate dielectric divided in two parts, we have used high-κ dielectric near the source and low-κ dielectric near the drain to reduce the short channel effects. By this structure short channel effects such as FIBL will be reduced indeed by increasing the RSiGe, ID-VD characteristics will be improved. The leakage current and transfer characteristics, the threshold-voltage (Vt), the drain induced barrier height lowering (DIBL), are estimated with respect to, gate bias (VG), RSiGe and different gate dielectrics. For short channel effects, such as DIBL, gate all around strained silicon nanowire FET have similar characteristics with the pure Si one while dual dielectrics can improve short channel effects in this structure.

Keywords: SNWT (silicon nanowire transistor), Tensile Strain, high-κ dielectric, Field Induced Barrier Lowering (FIBL), cylindricalnano wire (CW), drain induced barrier lowering (DIBL).

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Authors: Dia I. Abu-Al-Nadi, M. J. Mismar, T. H. Ismail

Abstract:

A technique for estimating the direction-of-arrival (DOA) of unknown number of source signals is presented using the eigen-approach. The eigenvector corresponding to the minimum eigenvalue of the autocorrelation matrix yields the minimum output power of the array. Also, the array polynomial with this eigenvector possesses roots on the unit circle. Therefore, the pseudo-spectrum is found by perturbing the phases of the roots one by one and calculating the corresponding array output power. The results indicate that the DOAs and the number of source signals are estimated accurately in the presence of a wide range of input noise levels.

Keywords: Array signal processing, direction-of-arrival, antenna arrays, eigenvalues, eigenvectors.

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Authors: F. Smach, M. Atri, J. Mitéran, M. Abid

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Face detection and recognition has many applications in a variety of fields such as security system, videoconferencing and identification. Face classification is currently implemented in software. A hardware implementation allows real-time processing, but has higher cost and time to-market. The objective of this work is to implement a classifier based on neural networks MLP (Multi-layer Perceptron) for face detection. The MLP is used to classify face and non-face patterns. The systm is described using C language on a P4 (2.4 Ghz) to extract weight values. Then a Hardware implementation is achieved using VHDL based Methodology. We target Xilinx FPGA as the implementation support.

Keywords: Classification, Face Detection, FPGA Hardware description, MLP.

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Authors: Yashvir Singh, Mayank Joshi

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A lateral trench-gate power metal-oxide-semiconductor on 4H-SiC is proposed. The device consists of two separate trenches in which two gates are placed on both sides of P-body region resulting two parallel channels. Enhanced current conduction and reduced-surface-field effect in the structure provide substantial improvement in the device performance. Using two dimensional simulations, the performance of proposed device is evaluated and compare of with that of the conventional device for same cell pitch. It is demonstrated that the proposed structure provides two times higher output current, 11% decrease in threshold voltage, 70% improvement in transconductance, 70% reduction in specific ON-resistance, 52% increase in breakdown voltage, and nearly eight time improvement in figure-of-merit over the conventional device.

Keywords: 4H-SiC, lateral, trench-gate, power MOSFET.

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Authors: V. Masilamani, D.K. Sheena Christy, D.G. Thomas

Abstract:

Image synthesis is an important area in image processing. To synthesize images various systems are proposed in the literature. In this paper, we propose a bio-inspired system to synthesize image and to study the generating power of the system, we define the class of languages generated by our system. We call image as array in this paper. We use a primitive called iso-array to synthesize image/array. The operation is double splicing on iso-arrays. The double splicing operation is used in DNA computing and we use this to synthesize image. A comparison of the family of languages generated by the proposed self restricted double splicing systems on iso-arrays with the existing family of local iso-picture languages is made. Certain closure properties such as union, concatenation and rotation are studied for the family of languages generated by the proposed model.

Keywords: DNA computing, splicing system, iso-picture languages, iso-array double splicing system, iso-array self splicing.

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Authors: Mansi Jhamb, R. K. Sharma, A. K. Gupta

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The distribution of a single global clock across a chip has become the major design bottleneck for high performance VLSI systems owing to the power dissipation, process variability and multicycle cross-chip signaling. A Network-on-Chip (NoC) architecture partitioned into several synchronous blocks has become a promising approach for attaining fine-grain power management at the system level. In a NoC architecture the communication between the blocks is handled asynchronously. To interface these blocks on a chip operating at different frequencies, an asynchronous FIFO interface is inevitable. However, these asynchronous FIFOs are not required if adjacent blocks belong to the same clock domain. In this paper, we have designed and analyzed a 16-bit asynchronous micropipelined FIFO of depth four, with the awareness of place and route on an FPGA device. We have used a commercially available Spartan 3 device and designed a high speed implementation of the asynchronous 4-phase micropipeline. The asynchronous FIFO implemented on the FPGA device shows 76 Mb/s throughput and a handshake cycle of 109 ns for write and 101.3 ns for read at the simulation under the worst case operating conditions (voltage = 0.95V) on a working chip at the room temperature.

Keywords: Asynchronous, FIFO, FPGA, GALS, Network-on- Chip (NoC), VHDL.

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Authors: Paris Kitsos

Abstract:

In this paper the FPGA implementations for four stream ciphers are presented. The two stream ciphers, MUGI and SNOW 2.0 are recently adopted by the International Organization for Standardization ISO/IEC 18033-4:2005 standard. The other two stream ciphers, MICKEY 128 and TRIVIUM have been submitted and are under consideration for the eSTREAM, the ECRYPT (European Network of Excellence for Cryptology) Stream Cipher project. All ciphers were coded using VHDL language. For the hardware implementation, an FPGA device was used. The proposed implementations achieve throughputs range from 166 Mbps for MICKEY 128 to 6080 Mbps for MUGI.

Keywords: Cryptography, ISO/IEC 18033-4:2005 standard, Hardware implementation, Stream ciphers

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Authors: Meiling Yang, Shuguo Xie, Yilong Zhu

Abstract:

Nowadays, due to diverse electric products and complex electromagnetic environment, the localization and troubleshooting of the electromagnetic radiation source is urgent and necessary especially on the condition of far field. However, based on the existing DOA positioning method, the system or devices are complex, bulky and expensive. To address this issue, this paper proposes a single antenna radiation source localization method. A single antenna moves to form a virtual antenna array combined with DOA and MUSIC algorithm to position accurately, meanwhile reducing the cost and simplify the equipment. As shown in the results of simulations and experiments, the virtual antenna array DOA estimation modeling is correct and its positioning is credible.

Keywords: Virtual antenna array, DOA, localization, far field.

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Authors: Youguo Wang, Lenan Wu

Abstract:

We discuss the signal detection through nonlinear threshold systems. The detection performance is assessed by the probability of error Per . We establish that: (1) when the signal is complete suprathreshold, noise always degrades the signal detection both in the single threshold system and in the parallel array of threshold devices. (2) When the signal is a little subthreshold, noise degrades signal detection in the single threshold system. But in the parallel array, noise can improve signal detection, i.e., stochastic resonance (SR) exists in the array. (3) When the signal is predominant subthreshold, noise always can improve signal detection and SR always exists not only in the single threshold system but also in the parallel array. (4) Array can improve signal detection by raising the number of threshold devices. These results extend further the applicability of SR in signal detection.

Keywords: Probability of error, signal detection, stochasticresonance, threshold system.

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Authors: Ahmet Turer

Abstract:

Middle-gate is located in Hasankeyf, Batman dating back to 1800 BC and is one of the important historical structures in Turkey. The ancient structure has suffered major structural cracks due to aging as well as lateral pressure of a cracked rock which is predicted to be about 100 tons. The existing support system was found to be inadequate to support the load especially after a recent rock fall in the close vicinity. Concerns were increased since the existing support system that is integral with a damaged and cracked gate wall needed to be replaced by a new support system. The replacement process must be carefully monitored by crackmeters and control mechanisms should be integrated to prevent cracks to expand while the same crack width needs to be maintained after the operation. The control system and actions taken during the intervention are explained in this paper.

Keywords: structural control, crack width, replacement, support

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Authors: Fasil Endalamaw

Abstract:

Digital magnitude comparators based on Gate Diffusion Input (GDI) implementation technique are high speed and area-efficient, and they consume less power as compared to other implementation techniques. However, they are less efficient for some logic gates and have no full voltage swing. In this paper, we made a performance comparison between the GDI implementation technique and other implementation methods, such as Static CMOS, Pass Transistor Logic (PTL), and Transmission Gate (TG) in 90 nm, 120 nm, and 180 nm CMOS technologies using BSIM4 MOS model. We proposed a methodology (hybrid implementation) of implementing digital magnitude comparators which significantly improved the power, speed, area, and voltage swing requirements. Simulation results revealed that the hybrid implementation of digital magnitude comparators show a 10.84% (power dissipation), 41.6% (propagation delay), 47.95% (power-delay product (PDP)) improvement compared to the usual GDI implementation method. We used Microwind & Dsch Version 3.5 as well as the Tanner EDA 16.0 tools for simulation purposes.

Keywords: Efficient, gate diffusion input, high speed, low power, CMOS.

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Authors: Padmanabhan Balasubramanian, C. Ardil

Abstract:

An effective approach for realizing the binary tree structure, representing a combinational logic functionality with enhanced throughput, is discussed in this paper. The optimization in maximum operating frequency was achieved through delay minimization, which in turn was possible by means of reducing the depth of the binary network. The proposed synthesis methodology has been validated by experimentation with FPGA as the target technology. Though our proposal is technology independent, yet the heuristic enables better optimization in throughput even after technology mapping for such Boolean functionality; whose reduced CNF form is associated with a lesser literal cost than its reduced DNF form at the Boolean equation level. For cases otherwise, our method converges to similar results as that of [12]. The practical results obtained for a variety of case studies demonstrate an improvement in the maximum throughput rate for Spartan IIE (XC2S50E-7FT256) and Spartan 3 (XC3S50-4PQ144) FPGA logic families by 10.49% and 13.68% respectively. With respect to the LUTs and IOBUFs required for physical implementation of the requisite non-regenerative logic functionality, the proposed method enabled savings to the tune of 44.35% and 44.67% respectively, over the existing efficient method available in literature [12].

Keywords: Binary logic tree, FPGA based design, Boolean function, Throughput rate, CNF, DNF.

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Authors: R. Hanuma Naik, D. V. Ashok Kumar, K. S. R. Anjaneyulu

Abstract:

Several of the practical industrial control processes are multivariable processes. Due to the relation amid the variables (interaction), delay in the loops, it is very intricate to design a controller directly for these processes. So first, the interaction of the variables is analyzed using Relative Normalized Gain Array (RNGA), which considers the time constant, static gain and delay time of the processes. Based on the effect of RNGA, relative gain array (RGA) and NI, the pair (control configuration) of variables to be controlled by decentralized control is selected. The equivalent transfer function (ETF) of the process model is estimated as first order process with delay using the corresponding elements in the Relative gain array and Relative average residence time array (RARTA) of the processes. Secondly, a decentralized Proportional- Integral (PI) controller is designed for each ETF simply using frequency response specifications. Finally, the performance and robustness of the algorithm is comparing with existing related approaches to validate the effectiveness of the projected algorithm.

Keywords: Decentralized control, interaction, Multivariable processes, relative normalized gain array, relative average residence time array, steady state gain.

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Authors: Shubhajit Roy Chowdhury, Aritra Banerjee, Aniruddha Roy, Hiranmay Saha

Abstract:

The paper proposes the novel design of a 3T XOR gate combining complementary CMOS with pass transistor logic. The design has been compared with earlier proposed 4T and 6T XOR gates and a significant improvement in silicon area and power-delay product has been obtained. An eight transistor full adder has been designed using the proposed three-transistor XOR gate and its performance has been investigated using 0.15um and 0.35um technologies. Compared to the earlier designed 10 transistor full adder, the proposed adder shows a significant improvement in silicon area and power delay product. The whole simulation has been carried out using HSPICE.

Keywords: XOR gate, full adder, improvement in speed, area minimization, transistor count minimization.

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Authors: Blesson Varghese, Gerard T. McKee

Abstract:

The work reported in this paper is motivated by the fact that there is a need to apply autonomic computing concepts to parallel computing systems. Advancing on prior work based on intelligent cores [36], a swarm-array computing approach, this paper focuses on 'Intelligent agents' another swarm-array computing approach in which the task to be executed on a parallel computing core is considered as a swarm of autonomous agents. A task is carried to a computing core by carrier agents and is seamlessly transferred between cores in the event of a predicted failure, thereby achieving self-ware objectives of autonomic computing. The feasibility of the proposed swarm-array computing approach is validated on a multi-agent simulator.

Keywords: Autonomic computing, intelligent agents, swarm-array computing.

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Authors: S.M. Lee, J.H. Koo, J.H. Park, S.C. Won

Abstract:

In this paper, we propose synchronization of an array of nonlinear systems with time delays. The array of systems is decomposed into isolated systems to establish appropriate Lyapunov¬Krasovskii functional. Using the Lyapunov-Krasovskii functional, a sufficient condition for the synchronization is derived in terms of LMIs(Linear Matrix Inequalities). Delayed feedback control gains are obtained by solving the sufficient condition. Numerical examples are given to show the validity the proposed method.

Keywords: Synchronization, Delay, Lyapunov method, LMI.

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Authors: Li Li, Li-Ru Xia, He-Ye Wang, Xiao-Dong Bi

Abstract:

In this paper, we presented a highly sensitive immune-affinity monolithic array for detection of α-fetoprotein (AFP) and carcinoembryonic antigen (CEA). Firstly, the epoxy functionalized monolith arrays were fabricated using UV initiated copolymerization method. Scanning electron microscopy (SEM) image showed that the poly(BABEA-co-GMA) monolith exhibited a well-controlled skeletal and well-distributed porous structure. Then, AFP and CEA immune-affinity monolithic arrays were prepared by immobilization of AFP and CEA antibodies on epoxy functionalized monolith arrays. With a non-competitive immune response format, the presented AFP and CEA immune-affinity arrays were demonstrated as an inexpensive, flexible, homogeneous and stable array for detection of AFP and CEA.

Keywords: Chemiluminescent detection, immune-affinity, monolithic copolymer array, UV-initiated copolymerization.

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Authors: Yngvar Berg, Mehdi Azadmehr

Abstract:

In this paper we present a linear autozeroing ultra lowvoltage amplifier. The autozeroing performed by all ULV circuits is important to reduce the impact of noise and especially avoid power supply noise in mixed signal low-voltage CMOS circuits. The simulated data presented is relevant for a 90nm TSMC CMOS process.

Keywords: Low-voltage, trans conductance amplifier, linearity, floating-gate.

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Authors: Kureshi Abdul Kadir, Mohd. Hasan

Abstract:

Each new semiconductor technology node brings smaller transistors and wires. Although this makes transistors faster, wires get slower. In nano-scale regime, the standard copper (Cu) interconnect will become a major hurdle for FPGA interconnect due to their high resistivity and electromigration. This paper presents the comprehensive evaluation of mixed CNT bundle interconnects and investigates their prospects as energy efficient and high speed interconnect for future FPGA routing architecture. All HSPICE simulations are carried out at operating frequency of 1GHz and it is found that mixed CNT bundle implemented in FPGAs as interconnect can potentially provide a substantial delay and energy reduction over traditional interconnects at 32nm process technology.

Keywords: CMOS, Copper Interconnect, Mixed CNT Bundle Interconnect, FPGAs.

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Authors: Xia Liu, Marek E. Bialkowski

Abstract:

This paper reports on investigations into capacity of a Multiple Input Multiple Output (MIMO) wireless communication system employing a uniform linear array (ULA) at the transmitter and either a uniform linear array (ULA) or a uniform circular array (UCA) antenna at the receiver. The transmitter is assumed to be surrounded by scattering objects while the receiver is postulated to be free from scattering objects. The Laplacian distribution of angle of arrival (AOA) of a signal reaching the receiver is postulated. Calculations of the MIMO system capacity are performed for two cases without and with the channel estimation errors. For estimating the MIMO channel, the scaled least square (SLS) and minimum mean square error (MMSE) methods are considered.

Keywords: MIMO, channel capacity, channel estimation, ULA, UCA, spatial correlation

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