Search results for: 3D microfluidic chip

Authors: Maria E. Manioudaki, Panayiota Poirazi

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Yeast cells live in a constantly changing environment that requires the continuous adaptation of their genomic program in order to sustain their homeostasis, survive and proliferate. Due to the advancement of high throughput technologies, there is currently a large amount of data such as gene expression, gene deletion and protein-protein interactions for S. Cerevisiae under various environmental conditions. Mining these datasets requires efficient computational methods capable of integrating different types of data, identifying inter-relations between different components and inferring functional groups or 'modules' that shape intracellular processes. This study uses computational methods to delineate some of the mechanisms used by yeast cells to respond to environmental changes. The GRAM algorithm is first used to integrate gene expression data and ChIP-chip data in order to find modules of coexpressed and co-regulated genes as well as the transcription factors (TFs) that regulate these modules. Since transcription factors are themselves transcriptionally regulated, a three-layer regulatory cascade consisting of the TF-regulators, the TFs and the regulated modules is subsequently considered. This three-layer cascade is then modeled quantitatively using artificial neural networks (ANNs) where the input layer corresponds to the expression of the up-stream transcription factors (TF-regulators) and the output layer corresponds to the expression of genes within each module. This work shows that (a) the expression of at least 33 genes over time and for different stress conditions is well predicted by the expression of the top layer transcription factors, including cases in which the effect of up-stream regulators is shifted in time and (b) identifies at least 6 novel regulatory interactions that were not previously associated with stress-induced changes in gene expression. These findings suggest that the combination of gene expression and protein-DNA interaction data with artificial neural networks can successfully model biological pathways and capture quantitative dependencies between distant regulators and downstream genes.

Keywords: gene modules, artificial neural networks, yeast, stress

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Authors: Nasir Mehmood, Saad Rahman, Vinodh Ravinath, Mahesh Balaji

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This paper describes the design of a programmable FSK-modulator based on VCO and its implementation in 0.35m CMOS process. The circuit is used to transmit digital data at 100Kbps rate in the frequency range of 400-600MHz. The design and operation of the modulator is discussed briefly. Further the characteristics of PLL, frequency synthesizer, VCO and the whole design are elaborated. The variation among the proposed and tested specifications is presented. Finally, the layout of sub-modules, pin configurations, final chip and test results are presented.

Keywords: FSK Modulator, CMOS, VCO, Phase Locked Loop, Frequency Synthesizer.

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Authors: Haedong Lee, Dooho Choi, Sokjoon Lee, Howon Kim

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This paper is about hiding RFID tag identifier (ID) using handheld device like a cellular phone. By modifying the tag ID of objects periodically or manually using cellular phone built-in a RFID reader chip or with a external RFID reader device, we can prevent other people from gathering the information related with objects querying information server (like an EPC IS) with a tag ID or deriving the information from tag ID-s code structure or tracking the location of the objects and the owner of the objects. In this paper, we use a cryptographic algorithm for modification and restoring of RFID tag ID, and for one original tag ID, there are several different temporary tag ID, periodically.

Keywords: EPC, RFID, Mobile RFID.

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Authors: J. S. Kim, N. P. Hong

Abstract:

In this paper, a CMOS vector modulator designed for wireless backhaul system based on 802.11ac is presented. A poly phase filter and sign select switches yield two orthogonal signal paths. Two variable gain amplifiers with strongly reduced phase shift of only ±5 ° are used to weight these paths. It has a phase control range of 360 ° and a gain range of -10 dB to 10 dB. The current drawn from a 1.2 V supply amounts 20.4 mA. Using a 0.13 mm technology, the chip die area amounts 1.47x0.75 mm².

Keywords: CMOS, vector modulator, backhaul, 802.11ac.

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Authors: J. S. Kim

Abstract:

This paper presents a 0.13-µm Complementary Metal-Oxide Semiconductor (CMOS) vector modulator for beamforming system. The vector modulator features a 360° phase and gain range of -10 dB to 10 dB with a root mean square phase and amplitude error of only 2.2° and 0.45 dB, respectively. These features make it a suitable for wireless backhaul system in the 5 GHz industrial, scientific, and medical (ISM) bands. It draws a current of 20.4 mA from a 1.2 V supply. The total chip size is 1.87x1.34 mm².

Keywords: CMOS, vector modulator, beamforming, wireless backhaul, ISM.

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Authors: Ahmed Madian, Muaz Aljarhi

Abstract:

Coordinate Rotation Digital Computer (CORDIC) is a unique digital computing unit intended for the computation of mathematical operations and functions. This paper presents A multi CORDIC processor that integrates different CORDIC architectures on a single FPGA chip and allows the user to select the CORDIC architecture to proceed with based on what he wants to calculate and his needs. Synthesis show that radix 2 CORDIC has the lowest clock delay, radix 8 CORDIC has the highest LUT usage and lowest register usage while Hybrid Radix 4 CORDIC had the highest clock delay.

Keywords: Multi, CORDIC, FPGA, Processor.

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Authors: Bassem Fahs, Philippe Barré, Patrick Ozenne, Eric Chartier, Guillaume Hérault, Sébastien Jacquet, Sébastien Clamagirand

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We present a dual-band (Cellular & PCS) dual-path zero-IF receiver for CDMA2000 diversity, monitoring and simultaneous-GPS. The secondary path is a SAW-less diversity CDMA receiver which can be also used for advanced features like monitoring when supported with an additional external VCO. A GPS receiver is integrated with its dedicated VCO allowing simultaneous positioning during a cellular call. The circuit is implemented in a 0.25μm 40GHz-fT BiCMOS process and uses a HVQFN 56-pin package. It consumes a maximum 300mW from a 2.8V supply in dual-modes. The chip area is 12.8mm2.

Keywords: CDMA, diversity, GPS, zero-IF, SAW-less

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Authors: Cătălin Mărculescu, Andrei Avram, Cătălin Pârvulescu, Marioara Avram, Cătălin Mihai Bălan

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The present microfluidic study is emphasizing the flow behavior within a Y shape micro-bifurcation in two similar flow configurations. We report here a numerical and experimental investigation on the velocity profiles evolution and secondary flows, manifested at different Reynolds numbers (Re) and for two different boundary conditions. The experiments are performed using special designed setup based on optical microscopic devices. With this setup, direct visualizations and quantitative measurements of the path-lines are obtained. A Micro-PIV measurement system is used to obtain velocity profiles distributions in a spatial evolution in the main flows domains. The experimental data is compared with numerical simulations performed with commercial computational code FLUENT in a 3D geometry with the same dimensions as the experimental one. The numerical flow patterns are found to be in good agreement with the experimental manifestations.

Keywords: Micro-PIV, numerical investigations, secondary flows, velocity profiles.

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Authors: Hsiao-Wei Wang, Jung-Tang Huang, Chun-Chiang Lin

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Aptamers are useful tools in microorganism researches, diagnoses, and treatment. Aptamers are specific target molecules formed by oligonucleic acid molecules, and are not decomposed by alcohol. Aptamers used to detect Mycobacterium tuberculosis (MTB) have been proved to have specific affinity to the outer membrane proteins of MTB. This article presents a biosensor chip set with aptamers for early detection of MTB with high specificity and sensitivity, even in very low concentration. Meanwhile, we have already made a modified hydrophobic facial mask module with internal rendering hydrophobic for effectively collecting M. tuberculosis.

Keywords: Aptamers, CNTFET, Mycobacterium tuberculosis, early detection.

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Authors: Eva Ungure, Sandra Muizniece-Brasava, Lija Dukalska, Vita Levkane

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The objective of the research was to evaluate the quality of milk pomade sweet – sherbet packed in different packaging materials (Multibarrier 60, met.BOPET/PE, Aluthen), by several packaging technologies – active and modified atmosphere (MAP) (consisting of 100% CO2), and control – in air ambiance. Experiments were carried out at the Faculty of Food Technology of Latvia University of Agriculture. Samples were stored at the room temperature +21±1 °C. The physiochemical properties – weight losses, moisture, hardening, colour and changes in headspace atmosphere concentration (CO2 and O2) of packs were analysed before packaging and after 2, 4, 6, 8, 10 and 12 storage weeks.

Keywords: packaging, shelf life, sherbet with crunchy peanut chip's

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Authors: Seung-Mok Han, Woo-Jin Nam, Seongsoo Lee

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This paper proposes and implements an core transform architecture, which is one of the major processes in HEVC video compression standard. The proposed core transform architecture is implemented with only adders and shifters instead of area-consuming multipliers. Shifters in the proposed core transform architecture are implemented in wires and multiplexers, which significantly reduces chip area. Also, it can process from 4×4 to 16×16 blocks with common hardware by reusing processing elements. Designed core transform architecture in 0.13um technology can process a 16×16 block with 2-D transform in 130 cycles, and its gate count is 101,015 gates.

Keywords: HEVC, Core transform, Low area, Shift-and-add, PE reuse

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Authors: Qing Fang, Lianxi Jia, Junfeng Song, Chao Li, Xianshu Luo, Mingbin Yu, Guoqiang Lo

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In this paper, we demonstrated a 1 × 4 silicon photonic cascaded arrayed waveguide grating, which is fabricated on a SOI wafer with a 220 nm top Si layer and a 2µm buried oxide layer. The measured on-chip transmission loss of this cascaded arrayed waveguide grating is ~ 5.6 dB, including the fiber-to-waveguide coupling loss. The adjacent crosstalk is 33.2 dB. Compared to the normal single silicon photonic arrayed waveguide grating with a crosstalk of ~ 12.5 dB, the crosstalk of this device has been dramatically increased.

Keywords: Silicon photonic, arrayed waveguide grating, high-crosstalk, cascaded structure.

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Authors: Nasir Mehmood, Jens Ogniewski, Vinodh Ravinath

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This paper describes the design of a real-time audiorange digital oscilloscope and its implementation in 90nm CMOS FPGA platform. The design consists of sample and hold circuits, A/D conversion, audio and video processing, on-chip RAM, clock generation and control logic. The design of internal blocks and modules in 90nm devices in an FPGA is elaborated. Also the key features and their implementation algorithms are presented. Finally, the timing waveforms and simulation results are put forward.

Keywords: CMOS, VLSI, Oscilloscope, Field Programmable Gate Array (FPGA), VHDL, Video Graphics Array (VGA)

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Authors: Yong Ren, Yaping Zhang

Abstract:

A numerical model has been developed to investigate the thermally triggered release kinetics for drug delivery using phase change material as shell of microcapsules. Biocompatible material n-Eicosane is used as demonstration. PCM shell of microcapsule will remain in solid form after the drug is taken, so the drug will be encapsulated by the shell, and will not be released until the target body part of lesion is exposed to external heat source, which will thermally trigger the release kinetics, leading to solid-to-liquid phase change. The findings can lead to better understanding on the key effects influencing the phase change process for drug delivery applications. The facile approach to release drug from core/shell structure of microcapsule can be well integrated with organic solvent free fabrication of microcapsules, using double emulsion as template in microfluidic aqueous two phase system.

Keywords: Phase change material, drug release kinetics, double emulsion, microfluidics.

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Authors: Xin-Yu Shih, Yue-Qu Liu, Hong-Ru Chou

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This paper presents a low-area and fully-reconfigurable Fast Fourier Transform (FFT) hardware design for 3GPP-LTE communication standard. It can fully support 32 different FFT sizes, up to 2048 FFT points. Besides, a special processing element is developed for making reconfigurable computing characteristics possible, while first-in first-out (FIFO) scheduling scheme design technique is proposed for hardware-friendly FIFO resource arranging. In a synthesis chip realization via TSMC 40 nm CMOS technology, the hardware circuit only occupies core area of 0.2325 mm² and dissipates 233.5 mW at maximal operating frequency of 250 MHz.

Keywords: Reconfigurable, fast Fourier transform, single-path delay feedback, 3GPP-LTE.

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Authors: V. Zamora, Z. Zhang, A. Meldrum

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The compatibility of optical resonators with microfluidic systems may be relevant for chemical and biological applications. Here, a fluorescent-core microcavity (FCM) is investigated as a refractometric sensor for heavy oils. A high-index film of silicon quantum dots (QDs) was formed inside the capillary, supporting cylindrical fluorescence whispering gallery modes (WGMs). A set of standard refractive index oils was injected into a capillary, causing a shift of the WGM resonances toward longer wavelengths. A maximum sensitivity of 240 nm/RIU (refractive index unit) was found for a nominal oil index of 1.74. As well, a sensitivity of 22 nm/RIU was obtained for a lower index of 1.48, more typical of fuel hydrocarbons. Furthermore, the observed spectra and sensitivities were compared to theoretical predictions and reproduced via FDTD simulations, showing in general an excellent agreement. This work demonstrates the potential use of FCMs for oil sensing applications and the more generally for detecting liquid solutions with a high refractive index or high viscosity.

Keywords: Oils, optical resonators, sensing applications, whispering gallery modes.

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Authors: Qimin Yang

Abstract:

In this paper, 3X3 routing nodes are proposed to provide speedup and parallel processing capability in Data Vortex network architectures. The new design not only significantly improves network throughput and latency, but also eliminates the need for distributive traffic control mechanism originally embedded among nodes and the need for nodal buffering. The cost effectiveness is studied by a comparison study with the previously proposed 2- input buffered networks, and considerable performance enhancement can be achieved with similar or lower cost of hardware. Unlike previous implementation, the network leaves small probability of contention, therefore, the packet drop rate must be kept low for such implementation to be feasible and attractive, and it can be achieved with proper choice of operation conditions.

Keywords: Data Vortex, Packet Switch, Interconnection network, deflection, Network-on-chip

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Authors: Jan Doutreloigne

Abstract:

This paper describes two methods for the reduction of the peak input current during the boosting of Dickson charge pumps. Both methods are implemented in the fully integrated Dickson charge pumps of a high-voltage display driver chip for smart-card applications. Experimental results reveal good correspondence with Spice simulations and show a reduction of the peak input current by a factor of 6 during boosting.

Keywords: Bi-stable display driver, Dickson charge pump, highvoltage generator, peak current reduction, sub-pump boosting, variable frequency boosting.

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Authors: Konstantinos Chalkias, George Filiadis, George Stephanides

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In this paper the authors propose a protocol, which uses Elliptic Curve Cryptography (ECC) based on the ElGamal-s algorithm, for sending small amounts of data via an authentication server. The innovation of this approach is that there is no need for a symmetric algorithm or a safe communication channel such as SSL. The reason that ECC has been chosen instead of RSA is that it provides a methodology for obtaining high-speed implementations of authentication protocols and encrypted mail techniques while using fewer bits for the keys. This means that ECC systems require smaller chip size and less power consumption. The proposed protocol has been implemented in Java to analyse its features and vulnerabilities in the real world.

Keywords: Elliptic Curve Cryptography, ElGamal, authentication protocol.

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Authors: Krzysztof Wawryn, Robert Suszyński, Bogdan Strzeszewski

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This paper presents two prototypes of low power low voltage current mode 9 bit pipelined a/d converters. The first and the second converters are configured of 1.5 bit and 2.5 bit stages, respectively. The a/d converter structures are composed of current mode building blocks and final comparator block which converts the analog current signal into digital voltage signal. All building blocks have been designed in CMOS AMS 0.35μm technology, then simulated to verify proposed concept. The performances of both converters are compared to performances of known current mode and voltage mode switched capacitance converter structures. Low power consumption and small chip area are advantages of the proposed converters.

Keywords: Pipelined converter, a/d converter, low power, lowvoltage, current mode.

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Authors: Ararat Khachatryan, Davit Mirzoyan

Abstract:

In sub micrometer technology, the aging phenomenon starts to have a significant impact on the reliability of integrated circuits by bringing performance degradation. For that reason, it is important to have a capability to evaluate the aging effects accurately. This paper presents an accurate aging measurement approach based on phase-locked loop (PLL) and voltage-controlled oscillator (VCO) circuit. The architecture is rejecting the circuit self-aging effect from the characteristics of PLL, which is generating the frequency without any aging phenomena affects. The aging monitor is implemented in low power 32 nm CMOS technology, and occupies a pretty small area. Aging simulation results show that the proposed aging measurement circuit improves accuracy by about 2.8% at high temperature and 19.6% at high voltage.

Keywords: Nanoscale, aging, effect, NBTI, HCI.

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Authors: Hanane Ondella, Pierre Ladet, David Ferrand, Pat Sloan

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In the micro and nano-technology industry, the «clean-rooms» dedicated to manufacturing chip, are equipped with the most sophisticated equipment-tools. There use a large number of resources in according to strict specifications for an optimum working and result. The distribution of «utilities» to the production is assured by teams who use a supervision tool. The studies show the interest to control the various parameters of production or/and distribution, in real time, through a reliable and effective supervision tool. This document looks at a large part of the functions that the supervisor must assure, with complementary functionalities to help the diagnosis and simulation that prove very useful in our case where the supervised installations are complexed and in constant evolution.

Keywords: Control-Command, evolution, non regression, performances, real time, simulation, supervision.

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Authors: Seong-Ho Song, Ki-Seob Kim, Seon-Woo Lee, Seop-Hyeong Park

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Based on a theoretical erbium-doped fiber amplifier (EDFA) model, we have proposed an application of disturbance observer(DOB) with proportional/integral/differential(PID) controller to EDFA for minimizing gain-transient time of wavelength -division-multiplexing (WDM) multi channels in optical amplifier in channel add/drop networks. We have dramatically reduced the gain-transient time to less than 30μsec by applying DOB with PID controller to the control of amplifier gain. The proposed DOB-based gain control algorithm for EDFA was implemented as a digital control system using TI's DSP(TMS320C28346) chip and experimental results of the system verify the excellent performance of the proposed gain control methodology.

Keywords: EDFA, Disturbance observer, gain control, WDM.

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Authors: Y. Li, K. Buddharaju, N. Singh, G. Q. Lo, S. J. Lee

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Silicon nanowire (SiNW) based thermoelectric device (TED) has potential applications in areas such as chip level cooling/ energy harvesting. It is a great challenge however, to assemble an efficient device with these SiNW. The presence of parasitic in the form of interfacial electrical resistance will have a significant impact on the performance of the TED. In this work, we explore the effect of the electrical contact resistance on the performance of a TED. Numerical simulations are performed on SiNW to investigate such effects on its cooling performance. Intrinsically, SiNW individually without the unwanted parasitic effect has excellent cooling power density. However, the cooling effect is undermined with the contribution of the electrical contact resistance.

Keywords: Thermoelectric, silicon, nanowire, electrical contact resistance, parasitics.

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Authors: Jihyung Kim, Taejin Kim, Sungho Park, Jun-Dong Cho

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In this paper, the problem of reducing switching activity in on-chip buses at the stage of high-level synthesis is considered, and a high-level low power bus binding based on dynamic bit reordering is proposed. Whereas conventional methods use a fixed bit ordering between variables within a bus, the proposed method switches a bit ordering dynamically to obtain a switching activity reduction. As a result, the proposed method finds a binding solution with a smaller value of total switching activity (TSA). Experimental result shows that the proposed method obtains a binding solution having 12.0-34.9% smaller TSA compared with the conventional methods.

Keywords: bit reordering, bus binding, low power, switching activity matrix

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Authors: A.R. Aswatha, T. Basavaraju, S. Sandeep Kumar

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Timing driven physical design, synthesis, and optimization tools need efficient closed-form delay models for estimating the delay associated with each net in an integrated circuit (IC) design. The total number of nets in a modern IC design has increased dramatically and exceeded millions. Therefore efficient modeling of interconnection is needed for high speed IC-s. This paper presents closed–form expressions for RC and RLC interconnection trees in current mode signaling, which can be implemented in VLSI design tool. These analytical model expressions can be used for accurate calculation of delay after the design clock tree has been laid out and the design is fully routed. Evaluation of these analytical models is several orders of magnitude faster than simulation using SPICE.

Keywords: IC design, RC/RLC Interconnection, VLSI Systems.

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Authors: C. Kalamani, K. Paramasivam

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In VLSI, testing plays an important role. Major problem in testing are test data volume and test power. The important solution to reduce test data volume and test time is test data compression. The Proposed technique combines the bit maskdictionary and 2n pattern run length-coding method and provides a substantial improvement in the compression efficiency without introducing any additional decompression penalty. This method has been implemented using Mat lab and HDL Language to reduce test data volume and memory requirements. This method is applied on various benchmark test sets and compared the results with other existing methods. The proposed technique can achieve a compression ratio up to 86%.

Keywords: Bit Mask dictionary, 2n pattern run length code, system-on-chip, SOC, test data compression.

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Authors: Jun Yu, Yat-Hei Lam, Boris Grinberg, Kevin Chai Tshun Chuan

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This paper presents a 5-V to 30-V current-mode boost converter for powering the drive circuit of a micro-electro-mechanical sensor. The design of a transconductance amplifier and an integrated current sensing circuit are presented. In addition, essential building blocks for power-on protection such as a soft-start and clamp block and supply and clock ready block are discussed in details. The chip is fabricated in a 0.18-μm CMOS process. Measurement results show that the soft-start and clamp block can effectively limit the inrush current during startup and protect the boost converter from startup failure.

Keywords: Boost Converter, Current Sensing, Power-on protection, Step-up Converter, Soft-start.

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Authors: Jingjing Lan, Jun Zhou, Xin Liu

Abstract:

In this paper, a low-power digital controller for DC-DC power conversion was presented. The controller generates the pulse-width modulated (PWM) signal from digital inputs provided by analog-to-digital converter (ADC). An efficient and simple design scheme to develop the control unit was discussed. This method allows minimization of the consumed resources of the chip and it is based on direct digital design approach. In this application, with the proposed scheme, nearly half area and two-third of the power consumption was saved compared to the conventional schemes. This work illustrates the possibility of implementing low-power and area-efficient power management circuit using direct digital design based approach. 

Keywords: Buck converter, DC-DC power conversion, digital control, proportional-integral (PI) controller.

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Authors: Andrew Randles, Ilker Ocak, Cheam Daw Don, Navab Singh, Alex Gu

Abstract:

Nine Degrees of Freedom (9 DOF) systems are already in development in many areas. In this paper, an integrated pressure sensor is proposed that will make use of an already existing monolithic 9 DOF inertial MEMS platform. Capacitive pressure sensors can suffer from limited sensitivity for a given size of membrane. This novel pressure sensor design increases the sensitivity by over 5 times compared to a traditional array of square diaphragms while still fitting within a 2 mm x 2 mm chip and maintaining a fixed static capacitance. The improved design uses one large diaphragm supported by pillars with fixed electrodes placed above the areas of maximum deflection. The design optimization increases the sensitivity from 0.22 fF/kPa to 1.16 fF/kPa. Temperature sensitivity was also examined through simulation.

Keywords: Capacitive pressure sensor, 9 DOF, 10 DOF, sensor, capacitive, inertial measurement unit, IMU, inertial navigation system, INS.

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