Commenced in January 2007
Paper Count: 30850
Low Power Bus Binding Based on Dynamic Bit Reordering
Abstract:In this paper, the problem of reducing switching activity in on-chip buses at the stage of high-level synthesis is considered, and a high-level low power bus binding based on dynamic bit reordering is proposed. Whereas conventional methods use a fixed bit ordering between variables within a bus, the proposed method switches a bit ordering dynamically to obtain a switching activity reduction. As a result, the proposed method finds a binding solution with a smaller value of total switching activity (TSA). Experimental result shows that the proposed method obtains a binding solution having 12.0-34.9% smaller TSA compared with the conventional methods.
Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1329362Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1014
 V. Soteriou and L. Peh, "Design space exploration of power-aware on/off interconnection networks," in Proc. Int. Conf. Comput. Des., Oct. 2004, pp. 510-517.
 C. Lyuh and T. Kim, "High-level synthesis for low power based on network flow method," " IEEE Trans. VLSI, vol. 1, no. 3, pp. 309-320, 2003
 Y. Choi and T. Kim, "An efficient low-power binding algorithm in high-level synthesis," IEEE Int. Symp. On Circuits and Systems, vol. 4, pp. 321-324, 2002.
 W. C. Cheng and M. Pedram, "Power-optimal encoding for DRAM address bus," in Proc. Int. Symp. Low-Power Electron. Design, pp. 250-252, 2000.
 L. Benini, A. Macii, E. Macii, M. Poncino, and R. Scarsi, "Architectures and synthesis algorithms for power efficient bus interfaces, " IEEE Trans. Computer-Aided Design, vol. 19, pp. 969-980, Sept. 2000.
 T. Lv, J. Henkel, H. Lekatsas, and W. Wolf, "An adaptive dictionary encoding scheme for SOC data buses, " in Proc. Design Automation Test Eur. Conf. Exihib., pp.1059-1064, 2002.
 A. P. Chandrakasan and R. W. Brodersen, Low power digital CMOS design, Kluwer Academic Publishers, pp. 235-245, 1995.
 M. Keating, D. Flynn, R. Aitken, A. Gibbons, and K. Shi, Low power methodology manual : for system-on-chip design, Springer, pp. 4-7, 2007.
 J. Kim and J. Cho, "Low power bus binding exploiting optimal substructure," IEICE Trans. on fundamentals of electronics communications and computer sciences, will be published in Jan. 2011.
 M. X. Goemans, Lecture notes on bipartite matching, unpublished, 2007.
 R. Jonker and A. Volgenant, "A shortest augmenting path algorithm for dense and sparse linear assignment problems," Computing, vol. 38, issue 4, pp. 325-340, 1987.
 J. Munkres, "Algorithms for the assignment and transportation problems," Journal of the Society for Industrial and Applied Mathematics, vol. 5, no. 1, pp. 32-38, 1957.
 J. Chang and M. Pedram, "Module assignment for low power," " in Proc. Eur. Design Automation Conf., pp.376-381, 1996.
 X. Xing and C. C. Jong, "A look-ahead synthesis technique with backtracking for switching activity reduction in low power high-level synthesis," Microelectronics Journal, vol. 38, no. 4-5, pp. 595-605, 2007.