Low Power Bus Binding Based on Dynamic Bit Reordering

Authors: Jihyung Kim, Taejin Kim, Sungho Park, Jun-Dong Cho

Abstract:

In this paper, the problem of reducing switching activity in on-chip buses at the stage of high-level synthesis is considered, and a high-level low power bus binding based on dynamic bit reordering is proposed. Whereas conventional methods use a fixed bit ordering between variables within a bus, the proposed method switches a bit ordering dynamically to obtain a switching activity reduction. As a result, the proposed method finds a binding solution with a smaller value of total switching activity (TSA). Experimental result shows that the proposed method obtains a binding solution having 12.0-34.9% smaller TSA compared with the conventional methods.

Keywords: bit reordering, bus binding, low power, switching activity matrix

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1329362

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