Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 30124
Compensated CIC-Hybrid Signed Digit Decimation Filter

Authors: Vishal Awasthi, Krishna Raj

Abstract:

In this paper, firstly, we present the mathematical modeling of finite impulse response (FIR) filter and Cascaded Integrator Comb (CIC) filter for sampling rate reduction and then an extension of Canonical signed digit (CSD) based efficient structure is presented in framework using hybrid signed digit (HSD) arithmetic. CSD representation imposed a restriction that two non-zero CSD coefficient bits cannot acquire adjacent bit positions and therefore, represented structure is not economical in terms of speed, area and power consumption. The HSD based structure gives optimum performance in terms of area and speed with 37.02% passband droop compensation.

Keywords: Multirate filtering, compensation theory, CIC filter, compensation filter, signed digit arithmetic, canonical signed digit.

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1340234

Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 484

References:


[1] R. E. Crochiere and L. R. Rabiner, "Optimum FIR Digital Filter Implementations for Decimation, Interpolation, and Narrow-Band Filtering," IEEE Transactions on Acoustics, Speech, and Signal Processing, Vol. Assp-23, No. 5, pp. 444-456, Oct. 1975.
[2] M. G. Bellanger, J. L. Daguet, and G. P. Lepagnol,"Interpolation, extrapolation and reduction of computation speed in digital filters," IEEE Trans. Acoustic., Speech, and Signal Processing, vol. ASSP-22, pp. 231-235, Aug. 1974.
[3] E. B. Hogenauer, "An Economical Class of Digital Filters for Decimation and Interpolation", IEEE Transactions on Acoustics, Speech & Signal Processing, Vol. ASSP-29, pp. 155-162, April 1981.
[4] A. Kwentus, O. Lee and A. N. Willson, Jr., "A 250 M sample/sec Programmable Cascaded Integrator-Comb Decimation Filter", in Proceeding of VLSI Signal Processing, IX, pp. 231-240, Oct. 1996.
[5] Kei-Yong Khoo, Zhan Yu, and Alan N. Willson Jr., “Efficient High-Speed CIC Decimation Filter", Proceedings Eleventh Annual IEEE International ASIC Conference, pp. 251-254, June 1998.
[6] Y. Djadi, T. A. Kwasniewski, C. Chan, and V. Szwarc, "A High Throughput Programmable Decimation and Interpolation Filter", Proceeding of the 1994 international Conference on Signal Proc. Applications and Technology, pp. 1743- 1748.
[7] H. K. Yang and W. M. Snelgrove, “High Speed Polyphase CIC Decimation Filters", Proc. of IEEE International Conference On Communications, pp. II.229- II.233, Atlanta, US, May 1996.
[8] Yonghong Gao, Lihong Jia, and Hannu Tenhunen, "An improved Architecture and implementation of Cascaded Integrator-Comb Decimation Filter", IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, pp. 317-320, Victoria, B.C., Canada, August 1999.
[9] G. J. Dolecek and Fred Harris, “Design of wideband CIC compensator filter for a digital IF receiver”, Journal of Digital Signal Processing, Vol. 19, Issue 5, Academic Press, U.S.A., pp. 827–837, Sept. 2009.
[10] G. J. Dolecek and Fred Harris, “On Design of Two- Stage CIC Compensation Filter”, IEEE International Symp. on Industrial Electronics, Seoul, Korea, pp. 903-908, July 5-8, 2009
[11] Rozita Teymourzadeh and Masuri Bin Othman, “An Enhancement of Decimation Process using Fast Cascaded Integrator Comb (CIC) Filter”, IEEE Trans. on Circuits & Systems, 2006.
[12] G. J. Dolecek and Fernando Javier Trejo Torres, “ Compensated CIC-Cosine Decimation Filter “, ECTI Transactions on Computer and Information Technology, Vol.4, No.1 , pp. 8-14, May 2010
[13] S. Kim, W.C. Lee, S. Ahn, and S. Choi, “Design of CIC roll-off compensation filter in a W-CDMA digital receiver”, Journal of Digital Signal Processing, vol. 16, pp. 846–854, 2006
[14] R. Latha and P.T. Vanathi, “Optimized Digital Filter Architectures for Multi-Standard RF Transceivers”, Journal of Theoretical and Applied Information Technology, Vol. 65, No.2, p.p. 544-558, July 2014
[15] Pecotic, M.G., Molnar, G., and Vucic, M. “Design of CIC compensators with SPT coefficients based on interval analysis”, Proceedings of the 35th International Convention, MIPRO, Croatia, pp. 123-128, 21-25 May 2012.
[16] G. J. Dolecek and J. Diaz Carmona, “A new cascaded modified CIC-Cosine decimation filter”, International IEEE Conference ISCAS 2005, Kobe, Japan, pp. 3733-3736, May 2005.
[17] R. K. Dubey, K. P. Pandey and R. K. Singh, “CIC Decimation Filter for Frequency”, International Journal of Science and Research (IJSR), Vol. 4, No.9, p.p. 1401-1405, September 2015.
[18] S. Karthikeyan, Dinesh G. and Binsu J Kailath, “Improved alias rejection using interleaved CIC decimation filter”, proc. of IEEE International conference on New Circuits and Systems Conference (NEWCAS), Canada, 26-29 June 2016.
[19] Y. M. Seddiq and H. Altwaijry,” An Implementation of a 2D FIR Filter Using the Signed-Digit Number System”, proc. of IEEE Inter. conference on Electronics, Communications and Photonics (SIECPC), Saudi, 2011.
[20] Phatak D. S. and I. Koren, “Hybrid Signed-Digit Number Systems: A Unified Framework for Redundant Number Representations with Bounded Carry Propagation Chains” IEEE Trans. on Computers, Vol. 43, No. 8, pp 880-891, Aug. 1994.
[21] A. Avizienis, "Signed-digit number representation for fast parallel arithmetic", IRE Transactions on Electronic Computers, pp. 389, 1961.