Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 4

Search results for: Digital Signal Processor (DSP)

4 Field Programmable Gate Array Based Infinite Impulse Response Filter Using Multipliers

Authors: Rajesh Mehra, Bharti Thakur

Abstract:

In this paper, an Infinite Impulse Response (IIR) filter has been designed and simulated on an Field Programmable Gate Arrays (FPGA). The implementation is based on Multiply Add and Accumulate (MAC) algorithm which uses multiply operations for design implementation. Parallel Pipelined structure is used to implement the proposed IIR Filter taking optimal advantage of the look up table of target device. The designed filter has been synthesized on Digital Signal Processor (DSP) slice based FPGA to perform multiplier function of MAC unit. The DSP slices are useful to enhance the speed performance. The proposed design is simulated with Matlab, synthesized with Xilinx Synthesis Tool, and implemented on FPGA devices. The Virtex 5 FPGA based design can operate at an estimated frequency of 81.5 MHz as compared to 40.5 MHz in case of Spartan 3 ADSP based design. The Virtex 5 based implementation also consumes less slices and slice flip flops of target FPGA in comparison to Spartan 3 ADSP based implementation to provide cost effective solution for signal processing applications.

Keywords: FPGA, dsp, MAC, butterworth, IIR

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3 Fuzzy Logic Speed Controller for Direct Vector Control of Induction Motor

Authors: Ben Hamed M., Sbita L

Abstract:

This paper presents a new method for the implementation of a direct rotor flux control (DRFOC) of induction motor (IM) drives. It is based on the rotor flux components regulation. The d and q axis rotor flux components feed proportional integral (PI) controllers. The outputs of which are the target stator voltages (vdsref and vqsref). While, the synchronous speed is depicted at the output of rotor speed controller. In order to accomplish variable speed operation, conventional PI like controller is commonly used. These controllers provide limited good performances over a wide range of operations even under ideal field oriented conditions. An alternate approach is to use the so called fuzzy logic controller. The overall investigated system is implemented using dSpace system based on digital signal processor (DSP). Simulation and experimental results have been presented for a one kw IM drives to confirm the validity of the proposed algorithms.

Keywords: Control, Fuzzy Logic, Variable Speed Drives, DRFOC, IM and real time

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2 Accelerating Integer Neural Networks On Low Cost DSPs

Authors: Thomas Behan, Zaiyi Liao, Lian Zhao, Chunting Yang

Abstract:

In this paper, low end Digital Signal Processors (DSPs) are applied to accelerate integer neural networks. The use of DSPs to accelerate neural networks has been a topic of study for some time, and has demonstrated significant performance improvements. Recently, work has been done on integer only neural networks, which greatly reduces hardware requirements, and thus allows for cheaper hardware implementation. DSPs with Arithmetic Logic Units (ALUs) that support floating or fixed point arithmetic are generally more expensive than their integer only counterparts due to increased circuit complexity. However if the need for floating or fixed point math operation can be removed, then simpler, lower cost DSPs can be used. To achieve this, an integer only neural network is created in this paper, which is then accelerated by using DSP instructions to improve performance.

Keywords: Digital Signal Processor (DSP), Integer Neural Network(INN), Low Cost Neural Network, Integer Neural Network DSPImplementation

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1 Parallel-computing Approach for FFT Implementation on Digital Signal Processor (DSP)

Authors: Yi-Pin Hsu, Shin-Yu Lin

Abstract:

An efficient parallel form in digital signal processor can improve the algorithm performance. The butterfly structure is an important role in fast Fourier transform (FFT), because its symmetry form is suitable for hardware implementation. Although it can perform a symmetric structure, the performance will be reduced under the data-dependent flow characteristic. Even though recent research which call as novel memory reference reduction methods (NMRRM) for FFT focus on reduce memory reference in twiddle factor, the data-dependent property still exists. In this paper, we propose a parallel-computing approach for FFT implementation on digital signal processor (DSP) which is based on data-independent property and still hold the property of low-memory reference. The proposed method combines final two steps in NMRRM FFT to perform a novel data-independent structure, besides it is very suitable for multi-operation-unit digital signal processor and dual-core system. We have applied the proposed method of radix-2 FFT algorithm in low memory reference on TI TMSC320C64x DSP. Experimental results show the method can reduce 33.8% clock cycles comparing with the NMRRM FFT implementation and keep the low-memory reference property.

Keywords: FFT, Parallel-computing, low-memory reference, TIDSP

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