Search results for: transistor count minimization.
293 Two Stage Fuzzy Methodology to Evaluate the Credit Risks of Investment Projects
Authors: O. Badagadze, G. Sirbiladze, I. Khutsishvili
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The work proposes a decision support methodology for the credit risk minimization in selection of investment projects. The methodology provides two stages of projects’ evaluation. Preliminary selection of projects with minor credit risks is made using the Expertons Method. The second stage makes ranking of chosen projects using the Possibilistic Discrimination Analysis Method. The latter is a new modification of a well-known Method of Fuzzy Discrimination Analysis.
Keywords: Expert valuations, expertons, investment project risks, positive and negative discriminations, possibility distribution.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1738292 Distribution Centers Reliability Cost in Capacitated Facility Location Problem
Authors: Mehdi Seifbarghy, Sajjad Jalali, Seyed Habib A. Rahmati
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Recently studies in area of supply chain network (SCN) have focused on the disruption issues in distribution systems. Also this paper extends the previous literature by providing a new biobjective model for cost minimization of designing a three echelon SCN across normal and failure scenarios with considering multi capacity option for manufacturers and distribution centers. Moreover, in order to solve the problem by means of LINGO software, novel model will be reformulated through a branch of LP-Metric method called Min-Max approach.Keywords: Scenario programming, Distribution, Multi-echelon supply chain design, Reliable facility
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1745291 Reduction of Leakage Power in Digital Logic Circuits Using Stacking Technique in 45 Nanometer Regime
Authors: P.K. Sharma, B. Bhargava, S. Akashe
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Power dissipation due to leakage current in the digital circuits is a biggest factor which is considered specially while designing nanoscale circuits. This paper is exploring the ideas of reducing leakage current in static CMOS circuits by stacking the transistors in increasing numbers. Clearly it means that the stacking of OFF transistors in large numbers result a significant reduction in power dissipation. Increase in source voltage of NMOS transistor minimizes the leakage current. Thus stacking technique makes circuit with minimum power dissipation losses due to leakage current. Also some of digital circuits such as full adder, D flip flop and 6T SRAM have been simulated in this paper, with the application of reduction technique on ‘cadence virtuoso tool’ using specter at 45nm technology with supply voltage 0.7V.
Keywords: Stack, 6T SRAM cell, low power, threshold voltage
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 3421290 Interaction between Respiration and Low-Frequency Cardiovascular Rhythms
Authors: Vladimir I. Ponomarenko, Mikhail D. Prokhorov, Anatoly S. Karavaev
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The interaction between respiration and low-frequency rhythms of the cardiovascular system is studied. The obtained results count in favor of the hypothesis that low-frequency rhythms in blood pressure and R-R intervals are generated in different central neural structures involved in the autonomic control of the cardiovascular systems.Keywords: Cardiovascular system, R-R intervals, blood pressure, synchronization.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1646289 Building Gabor Filters from Retinal Responses
Authors: Johannes Partzsch, Christian Mayr, Rene Schuffny
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Starting from a biologically inspired framework, Gabor filters were built up from retinal filters via LMSE algorithms. Asubset of retinal filter kernels was chosen to form a particular Gabor filter by using a weighted sum. One-dimensional optimization approaches were shown to be inappropriate for the problem. All model parameters were fixed with biological or image processing constraints. Detailed analysis of the optimization procedure led to the introduction of a minimization constraint. Finally, quantization of weighting factors was investigated. This resulted in an optimized cascaded structure of a Gabor filter bank implementation with lower computational cost.
Keywords: Gabor filter, image processing, optimization
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 2398288 Modeling the Transport of Charge Carriers in the Active Devices MESFET, Based of GaInP by the Monte Carlo Method
Authors: N. Massoum, A. Guen. Bouazza, B. Bouazza, A. El Ouchdi
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The progress of industry integrated circuits in recent years has been pushed by continuous miniaturization of transistors. With the reduction of dimensions of components at 0.1 micron and below, new physical effects come into play as the standard simulators of two dimensions (2D) do not consider. In fact the third dimension comes into play because the transverse and longitudinal dimensions of the components are of the same order of magnitude. To describe the operation of such components with greater fidelity, we must refine simulation tools and adapted to take into account these phenomena. After an analytical study of the static characteristics of the component, according to the different operating modes, a numerical simulation is performed of field-effect transistor with submicron gate MESFET GaInP. The influence of the dimensions of the gate length is studied. The results are used to determine the optimal geometric and physical parameters of the component for their specific applications and uses.
Keywords: Monte Carlo simulation, transient electron transport, MESFET device.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1665287 Design and Analysis of a Low Power High Speed 1 Bit Full Adder Cell Based On TSPC Logic with Multi-Threshold CMOS
Authors: Ankit Mitra
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An adder is one of the most integral component of a digital system like a digital signal processor or a microprocessor. Being an extremely computationally intensive part of a system, the optimization for speed and power consumption of the adder is of prime importance. In this paper we have designed a 1 bit full adder cell based on dynamic TSPC logic to achieve high speed operation. A high threshold voltage sleep transistor is used to reduce the static power dissipation in standby mode. The circuit is designed and simulated in TSPICE using TSMC 180nm CMOS process. Average power consumption, delay and power-delay product is measured which showed considerable improvement in performance over the existing full adder designs.
Keywords: CMOS, TSPC, MTCMOS, ALU, Clock gating, power gating, pipelining.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 3073286 Subthreshold Circuit Performance Investigation under Temperature Variations
Authors: Mohd. Hasan, Ajmal Kafeel, S. D. Pable
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Ultra-low-power (ULP) circuits have received widespread attention due to the rapid growth of biomedical applications and Battery-less Electronics. Subthreshold region of transistor operation is used in ULP circuits. Major research challenge in the subthreshold operating region is to extract the ULP benefits with minimal degradation in speed and robustness. Process, Voltage and Temperature (PVT) variations significantly affect the performance of subthreshold circuits. Designed performance parameters of ULP circuits may vary largely due to temperature variations. Hence, this paper investigates the effect of temperature variation on device and circuit performance parameters at different biasing voltages in the subthreshold region. Simulation results clearly demonstrate that in deep subthreshold and near threshold voltage regions, performance parameters are significantly affected whereas in moderate subthreshold region, subthreshold circuits are more immune to temperature variations. This establishes that moderate subthreshold region is ideal for temperature immune circuits.Keywords: Subthreshold, temperature variations, ultralow power.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 2306285 Effect of a Gravel Bed Flocculator on the Efficiency of a Low Cost Water Treatment Plants
Authors: Alaa Hussein Wadi
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The principal objective of a water treatment plant is to produce water that satisfies a set of drinking water quality standards at a reasonable price to the consumers. The gravel-bed flocculator provide a simple and inexpensive design for flocculation in small water treatment plants (less than 5000 m3/day capacity). The packed bed of gravel provides ideal conditions for the formation of compact settleable flocs because of continuous recontact provided by the sinuous flow of water through the interstices formed by the gravel. The field data which were obtained from the operation of the water supply treatment unit cover the physical, chemical and biological water qualities of the raw and settled water as obtained by the operation of the treatment unit. The experiments were carried out with the aim of assessing the efficiency of the gravel filter in removing the turbidity, pathogenic bacteria, from the raw water. The water treatment plant, which was constructed for the treatment of river water, was in principle a rapid sand filter. The results show that the average value of the turbidity level of the settled water was 4.83 NTU with a standard deviation of turbidity 2.893 NTU. This indicated that the removal efficiency of the sedimentation tank (gravel filter) was about 67.8 %. for pH values fluctuated between 7.75 and 8.15, indicating the alkaline nature of the raw water of the river Shatt Al-Hilla, as expected. Raw water pH is depressed slightly following alum coagulation. The pH of the settled water ranged from 7.75 to a maximum of 8.05. The bacteriological tests which were carried out on the water samples were: total coliform test, E-coli test, and the plate count test. In each test the procedure used was as outlined in the Standard Methods for the Examination of Water and Wastewater (APHA, AWWA, and WPCF, 1985). The gravel filter exhibit a low performance in removing bacterial load. The percentage bacterial removal, which is maximum for total plate count (19%) and minimum for total coliform (16.82%).Keywords: Gravel bed flocculator, turbidity, total coliform.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 2674284 Self-Organizing Maps in Evolutionary Approachmeant for Dimensioning Routes to the Demand
Authors: J.-C. Créput, A. Koukam, A. Hajjam
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We present a non standard Euclidean vehicle routing problem adding a level of clustering, and we revisit the use of self-organizing maps as a tool which naturally handles such problems. We present how they can be used as a main operator into an evolutionary algorithm to address two conflicting objectives of route length and distance from customers to bus stops minimization and to deal with capacity constraints. We apply the approach to a real-life case of combined clustering and vehicle routing for the transportation of the 780 employees of an enterprise. Basing upon a geographic information system we discuss the influence of road infrastructures on the solutions generated.Keywords: Evolutionary algorithm, self-organizing map, clustering and vehicle routing.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1382283 Quantum Dot Cellular Automata Based Effective Design of Combinational and Sequential Logical Structures
Authors: Hema Sandhya Jagarlamudi, Mousumi Saha, Pavan Kumar Jagarlamudi
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The use of Quantum dots is a promising emerging Technology for implementing digital system at the nano level. It is effecient for attractive features such as faster speed , smaller size and low power consumption than transistor technology. In this paper, various Combinational and sequential logical structures - HALF ADDER, SR Latch and Flip-Flop, D Flip-Flop preceding NAND, NOR, XOR,XNOR are discussed based on QCA design, with comparatively less number of cells and area. By applying these layouts, the hardware requirements for a QCA design can be reduced. These structures are designed and simulated using QCA Designer Tool. By taking full advantage of the unique features of this technology, we are able to create complete circuits on a single layer of QCA. Such Devices are expected to function with ultra low power Consumption and very high speeds.Keywords: QCA, QCA Designer, Clock, Majority Gate
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 2620282 A Kernel Classifier using Linearised Bregman Iteration
Authors: K. A. D. N. K Wimalawarne
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In this paper we introduce a novel kernel classifier based on a iterative shrinkage algorithm developed for compressive sensing. We have adopted Bregman iteration with soft and hard shrinkage functions and generalized hinge loss for solving l1 norm minimization problem for classification. Our experimental results with face recognition and digit classification using SVM as the benchmark have shown that our method has a close error rate compared to SVM but do not perform better than SVM. We have found that the soft shrinkage method give more accuracy and in some situations more sparseness than hard shrinkage methods.Keywords: Compressive sensing, Bregman iteration, Generalisedhinge loss, sparse, kernels, shrinkage functions
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1378281 Stability of Electrical Drives Supplied by a Three Level Inverter
Authors: M. S. Kelaiaia, H. Labar, S. Kelaiaia, T. Mesbah
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The development of the power electronics has allowed increasing the precision and reliability of the electrical devices, thanks to the adjustable inverters, as the Pulse Wide Modulation (PWM) applied to the three level inverters, which is the object of this study. The authors treat the relation between the law order adopted for a given system and the oscillations of the electrical and mechanical parameters of which the tolerance depends on the process with which they are integrated (paper factory, lifting of the heavy loads, etc.).Thus, the best choice of the regulation indexes allows us to achieve stability and safety training without investment (management of existing equipment). The optimal behavior of any electric device can be achieved by the minimization of the stored electrical and mechanical energy.Keywords: Multi level inverter, PWM, Harmonics, oscillation, control.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1373280 Characterization of the LMOS with Different Channel Structure
Authors: Hung-Pei Hsu, Jyi-Tsong Lin, Po-Hsieh Lin, Cheng-Hsien Chang, Ming-Tsung Shih, Chan-Hsiang Chang, Shih-Chuan Tseng, Min-Yan Lin, Shih-Wen Hsu
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In this paper, we propose a novel metal oxide semiconductor field effect transistor with L-shaped channel structure (LMOS), and several type of L-shaped structures are also designed, studied and compared with the conventional MOSFET device for the same average gate length (Lavg). The proposed device electrical characteristics are analyzed and evaluated by three dimension (3-D) ISE-TCAD simulator. It can be confirmed that the LMOS devices have higher on-state drain current and both lower drain-induced barrier lowering (DIBL) and subthreshold swing (S.S.) than its conventional counterpart has. In addition, the transconductance and voltage gain properties of the LMOS are also improved.Keywords: Average gate length (Lavg), drain-induced barrier lowering (DIBL), L-shaped channel MOSFET (LMOS), subthreshold swing (S.S.).
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1413279 Ec-A: A Task Allocation Algorithm for Energy Minimization in Multiprocessor Systems
Authors: Anju S. Pillai, T.B. Isha
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With the necessity of increased processing capacity with less energy consumption; power aware multiprocessor system has gained more attention in the recent future. One of the additional challenges that is to be solved in a multi-processor system when compared to uni-processor system is job allocation. This paper presents a novel task dependent job allocation algorithm: Energy centric- Allocation (Ec-A) and Rate Monotonic (RM) scheduling to minimize energy consumption in a multiprocessor system. A simulation analysis is carried out to verify the performance increase with reduction in energy consumption and required number of processors in the system.
Keywords: Energy consumption, Job allocation, Multiprocessor systems, Task dependent.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 2187278 Improving the LDMOS Temperature Compensation Bias Circuit to Optimize Back-Off
Authors: Antonis Constantinides, Christos Yiallouras, Christakis Damianou
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The application of today's semiconductor transistors in high power UHF DVB-T linear amplifiers has evolved significantly by utilizing LDMOS technology. This fact provides engineers with the option to design a single transistor signal amplifier which enables output power and linearity that was unobtainable previously using bipolar junction transistors or later type first generation MOSFETS. The quiescent current stability in terms of thermal variations of the LDMOS guarantees a robust operation in any topology of DVB-T signal amplifiers. Otherwise, progressively uncontrolled heat dissipation enhancement on the LDMOS case can degrade the amplifier’s crucial parameters in regards to the gain, linearity and RF stability, resulting in dysfunctional operation or a total destruction of the unit. This paper presents one more sophisticated approach from the traditional biasing circuits used so far in LDMOS DVB-T amplifiers. It utilizes a microprocessor control technology, providing stability in topologies where IDQ must be perfectly accurate.
Keywords: Amplifier, DVB-T, LDMOS, MOSFETS.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 3271277 Verification of the Simultaneous Local Extraction Method of Base and Thermal Resistance of Bipolar Transistors
Authors: Robert Setekera, Luuk Tiemeijer, Ramses van der Toorn
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In this paper an extensive verification of the extraction method (published earlier) that consistently accounts for self-heating and Early effect to accurately extract both base and thermal resistance of bipolar junction transistors is presented. The method verification is demonstrated on advanced RF SiGe HBTs were the extracted results for the thermal resistance are compared with those from another published method that ignores the effect of Early effect on internal base-emitter voltage and the extracted results of the base resistance are compared with those determined from noise measurements. A self-consistency of our method in the extracted base resistance and thermal resistance using compact model simulation results is also carried out in order to study the level of accuracy of the method.
Keywords: Avalanche, Base resistance, Bipolar transistor, Compact modeling, Early voltage, Thermal resistance, Self-heating, parameter extraction.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 2050276 Extraction of Forest Plantation Resources in Selected Forest of San Manuel, Pangasinan, Philippines Using LiDAR Data for Forest Status Assessment
Authors: Mark Joseph Quinto, Roan Beronilla, Guiller Damian, Eliza Camaso, Ronaldo Alberto
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Forest inventories are essential to assess the composition, structure and distribution of forest vegetation that can be used as baseline information for management decisions. Classical forest inventory is labor intensive and time-consuming and sometimes even dangerous. The use of Light Detection and Ranging (LiDAR) in forest inventory would improve and overcome these restrictions. This study was conducted to determine the possibility of using LiDAR derived data in extracting high accuracy forest biophysical parameters and as a non-destructive method for forest status analysis of San Manual, Pangasinan. Forest resources extraction was carried out using LAS tools, GIS, Envi and .bat scripts with the available LiDAR data. The process includes the generation of derivatives such as Digital Terrain Model (DTM), Canopy Height Model (CHM) and Canopy Cover Model (CCM) in .bat scripts followed by the generation of 17 composite bands to be used in the extraction of forest classification covers using ENVI 4.8 and GIS software. The Diameter in Breast Height (DBH), Above Ground Biomass (AGB) and Carbon Stock (CS) were estimated for each classified forest cover and Tree Count Extraction was carried out using GIS. Subsequently, field validation was conducted for accuracy assessment. Results showed that the forest of San Manuel has 73% Forest Cover, which is relatively much higher as compared to the 10% canopy cover requirement. On the extracted canopy height, 80% of the tree’s height ranges from 12 m to 17 m. CS of the three forest covers based on the AGB were: 20819.59 kg/20x20 m for closed broadleaf, 8609.82 kg/20x20 m for broadleaf plantation and 15545.57 kg/20x20m for open broadleaf. Average tree counts for the tree forest plantation was 413 trees/ha. As such, the forest of San Manuel has high percent forest cover and high CS.
Keywords: Carbon stock, forest inventory, LiDAR, tree count.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1281275 Input-Output Analysis in Laptop Computer Manufacturing
Authors: H. Z. Ulukan, E. Demircioğlu, M. Erol Genevois
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The scope of this paper and the aim of proposed model were to apply monetary Input –Output (I-O) analysis to point out the importance of reusing know-how and other requirements in order to reduce the production costs in a manufacturing process for a laptop computer. I-O approach using the monetary input-output model is employed to demonstrate the impacts of different factors in a manufacturing process. A sensitivity analysis showing the correlation between these different factors is also presented. It is expected that the recommended model would have an advantageous effect in the cost minimization process.
Keywords: Input-Output Analysis, Monetary Input-Output Model, Manufacturing Process, Laptop Computer.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 4627274 A Clock Skew Minimization Technique Considering Temperature Gradient
Authors: Se-Jin Ko, Deok-Min Kim, Seok-Yoon Kim
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The trend of growing density on chips has increases not only the temperature in chips but also the gradient of the temperature depending on locations. In this paper, we propose the balanced skew tree generation technique for minimizing the clock skew that is affected by the temperature gradients on chips. We calculate the interconnect delay using Elmore delay equation, and find out the optimal balanced clock tree by modifying the clock trees generated through the Deferred Merge Embedding(DME) algorithm. The experimental results show that the distance variance of clock insertion points with and without considering the temperature gradient can be lowered below 54% and we confirm that the skew is remarkably decreased after applying the proposed technique.Keywords: clock, clock-skew, temperature, thermal.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1713273 Meshed Antenna for Ku-band Wireless Communication
Authors: Chokri Baccouch, Chayma Bahhar, Hedi Sakli, Nizar Sakli
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In this article, we present the combination of an antenna patch structure with a photovoltaic cell in one device for telecommunication applications in isolated environments. The radiating patch element of a patch antenna was replaced by a solar cell. DC current generation is the original feature of the solar cell, but now it was additionally able to receive and transmit electromagnetic waves. A mathematical model which serves in the minimization of power losses of the cell and therefore the improvement in conversion performance was studied. Simulation results of this antenna show a resonance at a frequency of 16.55 GHz in Ku-band with a gain of 4.24 dBi.
Keywords: Electric power collected, optical and electrical losses, optimization of the grid of collection, patch antenna, photovoltaic cell.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 761272 Design of High Gain, High Bandwidth Op-Amp for Reduction of Mismatch Currents in Charge Pump PLL in 180 nm CMOS Technology
Authors: R .H. Talwekar, S. S Limaye
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The designing of charge pump with high gain Op- Amp is a challenging task for getting faithful response .Design of high performance phase locked loop require ,a design of high performance charge pump .We have designed a operational amplifier for reducing the error caused by high speed glitch in a transistor and mismatch currents . A separate Op-Amp has designed in 180 nm CMOS technology by CADENCE VIRTUOSO tool. This paper describes the design of high performance charge pump for GHz CMOS PLL targeting orthogonal frequency division multiplexing (OFDM) application. A high speed low power consumption Op-Amp with more than 500 MHz bandwidth has designed for increasing the speed of charge pump in Phase locked loop.Keywords: Charge pump (CP) Orthogonal frequency divisionmultiplexing (OFDM), Phase locked loop (PLL), Phase frequencydetector (PFD), Voltage controlled oscillator (VCO),
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 3448271 An Approximation Method for Exact Boundary Controllability of Euler-Bernoulli System
Authors: Abdelaziz Khernane, Naceur Khelil, Leila Djerou
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The aim of this work is to study the numerical implementation of the Hilbert Uniqueness Method for the exact boundary controllability of Euler-Bernoulli beam equation. This study may be difficult. This will depend on the problem under consideration (geometry, control and dimension) and the numerical method used. Knowledge of the asymptotic behaviour of the control governing the system at time T may be useful for its calculation. This idea will be developed in this study. We have characterized as a first step, the solution by a minimization principle and proposed secondly a method for its resolution to approximate the control steering the considered system to rest at time T.Keywords: Boundary control, exact controllability, finite difference methods, functional optimization.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1487270 Optical Heterodyning of Injection-Locked Laser Sources — A Novel Technique for Millimeter-Wave Signal Generation
Authors: Subal Kar, Madhuja Ghosh, Soumik Das, Antara Saha
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A novel technique has been developed to generate ultra-stable millimeter-wave signal by optical heterodyning of the output from two slave laser (SL) sources injection-locked to the sidebands of a frequency modulated (FM) master laser (ML). Precise thermal tuning of the SL sources is required to lock the particular slave laser frequency to the desired FM sidebands of the ML. The output signals from the injection-locked SL when coherently heterodyned in a fast response photo detector like high electron mobility transistor (HEMT), extremely stable millimeter-wave signal having very narrow line width can be generated. The scheme may also be used to generate ultra-stable sub-millimeter-wave/terahertz signal.
Keywords: FM sideband injection locking, Master-Slave injection locking, Millimetre-wave signal generation and Optical heterodyning.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1980269 A Comparative Study of Novel Opportunistic Routing Protocols in Mobile Ad Hoc Networks
Authors: R. Poonkuzhali, M. Y. Sanavullah, M. R. Gurupriya
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Opportunistic routing is used, where the network has the features like dynamic topology changes and intermittent network connectivity. In Delay tolerant network or Disruption tolerant network opportunistic forwarding technique is widely used. The key idea of opportunistic routing is selecting forwarding nodes to forward data packets and coordination among these nodes to avoid duplicate transmissions. This paper gives the analysis of pros and cons of various opportunistic routing techniques used in MANET.
Keywords: Expected Transmission Count (ETX), Opportunistic routing, Proactive Source Routing (PSR), throughput.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 2412268 Fabrication and Electrical Characterization of Al/BaxSr1-xTiO3/Pt/SiO2/Si Configuration for FeFET Applications
Authors: Ala'eddin A. Saif , Z. A. Z. Jamal, Z. Sauli, P. Poopalan
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The ferroelectric behavior of barium strontium titanate (BST) in thin film form has been investigated in order to study the possibility of using BST for ferroelectric gate-field effect transistor (FeFET) for memory devices application. BST thin films have been fabricated as Al/BST/Pt/SiO2/Si-gate configuration. The variation of the dielectric constant (ε) and tan δ with frequency have been studied to ensure the dielectric quality of the material. The results show that at low frequencies, ε increases as the Ba content increases, whereas at high frequencies, it shows the opposite variation, which is attributed to the dipole dynamics. tan δ shows low values with a peak at the mid-frequency range. The ferroelectric behavior of the Al/BST/Pt/SiO2/Si has been investigated using C-V characteristics. The results show that the strength of the ferroelectric hysteresis loop increases as the Ba content increases; this is attributed to the grain size and dipole dynamics effect.Keywords: BST thin film, Electrical properties, Ferroelectrichysteresis, Ferroelectric FET.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1533267 Minimizing Examinee Collusion with a Latin- Square Treatment Structure
Authors: M. H. Omar
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Cheating on standardized tests has been a major concern as it potentially minimizes measurement precision. One major way to reduce cheating by collusion is to administer multiple forms of a test. Even with this approach, potential collusion is still quite large. A Latin-square treatment structure for distributing multiple forms is proposed to further reduce the colluding potential. An index to measure the extent of colluding potential is also proposed. Finally, with a simple algorithm, the various Latin-squares were explored to find the best structure to keep the colluding potential to a minimum.Keywords: Colluding pairs, Scale for Colluding Potential, Latin-Square Structure, Minimization of Cheating.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1166266 Genetic Algorithm and Padé-Moment Matching for Model Order Reduction
Authors: Shilpi Lavania, Deepak Nagaria
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A mixed method for model order reduction is presented in this paper. The denominator polynomial is derived by matching both Markov parameters and time moments, whereas numerator polynomial derivation and error minimization is done using Genetic Algorithm. The efficiency of the proposed method can be investigated in terms of closeness of the response of reduced order model with respect to that of higher order original model and a comparison of the integral square error as well.
Keywords: Model Order Reduction (MOR), control theory, Markov parameters, time moments, genetic algorithm, Single Input Single Output (SISO).
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 3534265 Design Optimization of the Primary Containment Building of a Pressurized Water Reactor
Authors: M. Hossain, A. H. Khan, M. A. R. Sarkar
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Primary containment structure is one of the five safety layers of a nuclear facility which is needed to be designed in such a manner that it can withstand the pressure and excessive radioactivity during accidental situations. It is also necessary to ensure minimization of cost with maximum possible safety in order to make the design economically feasible and attractive. This paper attempts to identify the optimum design conditions for primary containment structure considering both mechanical and radiation safety keeping the economic aspects in mind. This work takes advantage of commercial simulation software to identify the suitable conditions without the requirement of costly experiments. Generated data may be helpful for further studies.
Keywords: PWR, concrete containment, finite element approach, neutron attenuation, Von Mises Stress.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 875264 Reliability Improvement with Optimal Placement of Distributed Generation in Distribution System
Authors: N. Rugthaicharoencheep, T. Langtharthong
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This paper presents the optimal placement and sizing of distributed generation (DG) in a distribution system. The problem is to reliability improvement of distribution system with distributed generations. The technique employed to solve the minimization problem is based on a developed Tabu search algorithm and reliability worth analysis. The developed methodology is tested with a distribution system of Roy Billinton Test System (RBTS) bus 2. It can be seen from the case study that distributed generation can reduce the customer interruption cost and therefore improve the reliability of the system. It is expected that our proposed method will be utilized effectively for distribution system operator.
Keywords: Distributed generation Optimization technique Reliability improvement, Distribution system.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 3019