Search results for: Bridge Circuit
661 A Soft Error Rates Evaluation Method of Combinational Logic Circuit Based on Linear Energy Transfers
Authors: Man Li, Wanting Zhou, Lei Li
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Communication stability is the primary concern of communication satellites. Communication satellites are easily affected by particle radiation to generate single event effects (SEE), which leads to soft errors (SE) of combinational logic circuit. The existing research on soft error rates (SER) of combined logic circuit is mostly based on the assumption that the logic gates being bombarded have the same pulse width. However, in the actual radiation environment, the pulse widths of the logic gates being bombarded are different due to different linear energy transfers (LET). In order to improve the accuracy of SER evaluation model, this paper proposes a soft error rates evaluation method based on LET. In this paper, we analyze the influence of LET on the pulse width of combinational logic and establish the pulse width model based on LET. Based on this model, the error rate of test circuit ISCAS’85 is calculated. Experimental results show that this model can be used for SER evaluation.
Keywords: Communication satellite, pulse width, soft error rates, linear energy transfer, LET.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 383660 Reversible Signed Division for Computing Systems
Authors: D. Krishnaveni, M. Geetha Priya
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Applications of reversible logic gates in the design of complex integrated circuits provide power optimization. This technique finds a great use in low power CMOS design, optical computing, quantum computing and nanotechnology. This paper proposes a reversible signed division circuit that can divide an n-bit signed dividend with an n-bit signed divisor using non-restoration division logic. The proposed design adequately addresses the ‘delay’ there by improving the efficiency of the circuit. An attempt is made to design a reversible signed division circuit. This paper provides a threshold to build more complex arithmetic systems using reversible logic, thus increasing the performance of computing systems.
Keywords: Low power CMOS, quantum computing, reversible logic gates, shift register, signed division.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1261659 A Neural Network Approach for an Automatic Detection and Localization of an Open Phase Circuit of a Five-Phase Induction Machine Used in a Drivetrain of an Electric Vehicle
Authors: S. Chahba, R. Sehab, A. Akrad, C. Morel
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Nowadays, the electric machines used in urban electric vehicles are, in most cases, three-phase electric machines with or without a magnet in the rotor. Permanent Magnet Synchronous Machine (PMSM) and Induction Machine (IM) are the main components of drive trains of electric and hybrid vehicles. These machines have very good performance in healthy operation mode, but they are not redundant to ensure safety in faulty operation mode. Faced with the continued growth in the demand for electric vehicles in the automotive market, improving the reliability of electric vehicles is necessary over the lifecycle of the electric vehicle. Multiphase electric machines respond well to this constraint because, on the one hand, they have better robustness in the event of a breakdown (opening of a phase, opening of an arm of the power stage, intern-turn short circuit) and, on the other hand, better power density. In this work, a diagnosis approach using a neural network for an open circuit fault or more of a five-phase induction machine is developed. Validation on the simulator of the vehicle drivetrain, at reduced power, is carried out, creating one and more open circuit stator phases showing the efficiency and the reliability of the new approach to detect and to locate on-line one or more open phases of a five-induction machine.
Keywords: Electric vehicle drivetrain, multiphase drives, induction machine, control, open circuit fault diagnosis, artificial neural network.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 451658 Analysis of Partially Shaded PV Modules Using Piecewise Linear Parallel Branches Model
Authors: Yaw-Juen Wang, Po-Chun Hsu
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This paper presents an equivalent circuit model based on piecewise linear parallel branches (PLPB) to study solar cell modules which are partially shaded. The PLPB model can easily be used in circuit simulation software such as the ElectroMagnetic Transients Program (EMTP). This PLPB model allows the user to simulate several different configurations of solar cells, the influence of partial shadowing on a single or multiple cells, the influence of the number of solar cells protected by a bypass diode and the effect of the cell connection configuration on partial shadowing.
Keywords: Cell Connection Configurations, EMTP, Equivalent Circuit, Partial Shading, Photovoltaic Module
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 2934657 Prediction of the Performance of a Bar-Type Piezoelectric Vibration Actuator Depending on the Frequency Using an Equivalent Circuit Analysis
Authors: J. H. Kim, J. H. Kwon, J. S. Park, K. J. Lim
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This paper has been investigated a technique that predicts the performance of a bar-type unimorph piezoelectric vibration actuator depending on the frequency. This paper has been proposed an equivalent circuit that can be easily analyzed for the bar-type unimorph piezoelectric vibration actuator. In the dynamic analysis, rigidity and resonance frequency, which are important mechanical elements, were derived using the basic beam theory. In the equivalent circuit analysis, the displacement and bandwidth of the piezoelectric vibration actuator depending on the frequency were predicted. Also, for the reliability of the derived equations, the predicted performance depending on the shape change was compared with the result of a finite element analysis program.
Keywords: Actuator, performance, piezoelectric, unimorph.Actuator, performance, piezoelectric, unimorph.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1718656 Modeling and Visualizing Seismic Wave Propagation in Elastic Medium Using Multi-Dimension Wave Digital Filtering Approach
Authors: Jason Chien-Hsun Tseng, Nguyen Dong-Thai Dao, Chong-Ching Chang
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A novel PDE solver using the multidimensional wave digital filtering (MDWDF) technique to achieve the solution of a 2D seismic wave system is presented. In essence, the continuous physical system served by a linear Kirchhoff circuit is transformed to an equivalent discrete dynamic system implemented by a MD wave digital filtering (MDWDF) circuit. This amounts to numerically approximating the differential equations used to describe elements of a MD passive electronic circuit by a grid-based difference equations implemented by the so-called state quantities within the passive MDWDF circuit. So the digital model can track the wave field on a dense 3D grid of points. Details about how to transform the continuous system into a desired discrete passive system are addressed. In addition, initial and boundary conditions are properly embedded into the MDWDF circuit in terms of state quantities. Graphic results have clearly demonstrated some physical effects of seismic wave (P-wave and S–wave) propagation including radiation, reflection, and refraction from and across the hard boundaries. Comparison between the MDWDF technique and the finite difference time domain (FDTD) approach is also made in terms of the computational efficiency.Keywords: Seismic Wave Propagation, Multi-dimension WaveDigital Filters, Partial Differential Equations.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1434655 Seismic Fragility Assessment of Continuous Integral Bridge Frames with Variable Expansion Joint Clearances
Authors: P. Mounnarath, U. Schmitz, Ch. Zhang
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Fragility analysis is an effective tool for the seismic vulnerability assessment of civil structures in the last several years. The design of the expansion joints according to various bridge design codes is almost inconsistent, and only a few studies have focused on this problem so far. In this study, the influence of the expansion joint clearances between the girder ends and the abutment backwalls on the seismic fragility assessment of continuous integral bridge frames is investigated. The gaps (ranging from 60 mm, 150 mm, 250 mm and 350 mm) are designed by following two different bridge design code specifications, namely, Caltrans and Eurocode 8-2. Five bridge models are analyzed and compared. The first bridge model serves as a reference. This model uses three-dimensional reinforced concrete fiber beam-column elements with simplified supports at both ends of the girder. The other four models also employ reinforced concrete fiber beam-column elements but include the abutment backfill stiffness and four different gap values. The nonlinear time history analysis is performed. The artificial ground motion sets, which have the peak ground accelerations (PGAs) ranging from 0.1 g to 1.0 g with an increment of 0.05 g, are taken as input. The soil-structure interaction and the P-Δ effects are also included in the analysis. The component fragility curves in terms of the curvature ductility demand to the capacity ratio of the piers and the displacement demand to the capacity ratio of the abutment sliding bearings are established and compared. The system fragility curves are then obtained by combining the component fragility curves. Our results show that in the component fragility analysis, the reference bridge model exhibits a severe vulnerability compared to that of other sophisticated bridge models for all damage states. In the system fragility analysis, the reference curves illustrate a smaller damage probability in the earlier PGA ranges for the first three damage states, they then show a higher fragility compared to other curves in the larger PGA levels. In the fourth damage state, the reference curve has the smallest vulnerability. In both the component and the system fragility analysis, the same trend is found that the bridge models with smaller clearances exhibit a smaller fragility compared to that with larger openings. However, the bridge model with a maximum clearance still induces a minimum pounding force effect.Keywords: Expansion joint clearance, fiber beam-column element, fragility assessment, time history analysis.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1714654 Simulation of Dynamics of a Permanent Magnet Linear Actuator
Authors: Ivan Yatchev, Ewen Ritchie
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Comparison of two approaches for the simulation of the dynamic behaviour of a permanent magnet linear actuator is presented. These are full coupled model, where the electromagnetic field, electric circuit and mechanical motion problems are solved simultaneously, and decoupled model, where first a set of static magnetic filed analysis is carried out and then the electric circuit and mechanical motion equations are solved employing bi-cubic spline approximations of the field analysis results. The results show that the proposed decoupled model is of satisfactory accuracy and gives more flexibility when the actuator response is required to be estimated for different external conditions, e.g. external circuit parameters or mechanical loads.Keywords: Coupled problems, dynamic models, finite elementanalysis, linear actuators, permanent magnets.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 2762653 Time Development of Local Scour around Semi Integral Bridge Piers and Piles in Malaysia
Authors: Shatirah Akib, Sadia Rahman
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Scouring around a bridge pier is a complex phenomenon. More laboratory experiments are required to understand the scour mechanism. This paper focused on time development of local scour around piers and piles in semi integral bridges. Laboratory data collected at Hydraulics Laboratory, University of Malaya was analyzed for this purpose. Tests were performed with two different uniform sediment sizes and five ranges of flow velocities. Fine and coarse sediments were tested in the flume. Results showed that scour depths for both pier and piles increased with time up to certain levels and after that they became almost constant. It had been found that scour depths increased when discharges increased. Coarser sediment also produced lesser scouring at the piers and combined piles.
Keywords: Pier, pile, scour, semi integral bridge, time.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 2920652 Modified Buck Boost Circuit for Linear and Non-Linear Piezoelectric Energy Harvesting
Authors: I Made Darmayuda, Chai Tshun Chuan Kevin, Je Minkyu
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Plenty researches have reported techniques to harvest energy from piezoelectric transducer. In the earlier years, the researches mainly report linear energy harvesting techniques whereby interface circuitry is designed to have input impedance that match with the impedance of the piezoelectric transducer. In recent years non-linear techniques become more popular. The non-linear technique employs voltage waveform manipulation to boost the available-for-extraction energy at the time of energy transfer. The fact that non-linear energy extraction provides larger available-for-extraction energy doesn’t mean the linear energy extraction is completely obsolete. In some scenarios, such as where initial power is not available, linear energy extraction is still preferred. A modified Buck Boost circuit which is capable of harvesting piezoelectric energy using both linear and non-linear techniques is reported in this paper. Efficiency of at least 64% can be achieved using this circuit. For linear extraction, the modified Buck Boost circuit is controlled using a fix frequency and duty cycle clock. A voltage sensor and a pulse generator are added as the controller for the non-linear extraction technique.
Keywords: Buck boost, energy harvester, linear energy harvester, non-linear energy harvester, piezoelectric, synchronized charge extraction.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 2435651 Design and Characterization of CMOS Readout Circuit for ISFET and ISE Based Sensors
Authors: Yuzman Yusoff, Siti Noor Harun, Noor Shelida Sallehand Tan Kong Yew
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This paper presents the design and characterization of analog readout interface circuits for ion sensitive field effect transistor (ISFET) and ion selective electrode (ISE) based sensor. These interface circuits are implemented using MIMOS’s 0.35um CMOS technology and experimentally characterized under 24-leads QFN package. The characterization evaluates the circuit’s functionality, output sensitivity and output linearity. Commercial sensors for both ISFET and ISE are employed together with glass reference electrode during testing. The test result shows that the designed interface circuits manage to readout signals produced by both sensors with measured sensitivity of ISFET and ISE sensor are 54mV/pH and 62mV/decade, respectively. The characterized output linearity for both circuits achieves above 0.999 rsquare. The readout also has demonstrated reliable operation by passing all qualifications in reliability test plan.
Keywords: Readout interface circuit (ROIC), analog interface circuit, ion sensitive field effect transistor (ISFET), ion selective electrode (ISE), and ion sensor electronics.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 2653650 Design and Characterization of CMOS Readout Circuit for ISFET and ISE Based Sensors
Authors: Yuzman Yusoff, Siti Noor Harun, Noor Shelida Sallehand, Tan Kong Yew
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This paper presents the design and characterization of analog readout interface circuits for ion sensitive field effect transistor (ISFET) and ion selective electrode (ISE) based sensor. These interface circuits are implemented using MIMOS’s 0.35um CMOS technology and experimentally characterized under 24-leads QFN package. The characterization evaluates the circuit’s functionality, output sensitivity and output linearity. Commercial sensors for both ISFET and ISE are employed together with glass reference electrode during testing. The test result shows that the designed interface circuits manage to readout signals produced by both sensors with measured sensitivity of ISFET and ISE sensor are 54mV/pH and 62mV/decade, respectively. The characterized output linearity for both circuits achieves above 0.999 Rsquare. The readout also has demonstrated reliable operation by passing all qualifications in reliability test plan.
Keywords: Readout interface circuit (ROIC), analog interface circuit, ion sensitive field effect transistor (ISFET), ion selective electrode (ISE), ion sensor electronics.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 2064649 Thermal Modeling of Dry-Transformers and Estimating Temperature Rise
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Temperature rise in a transformer depends on variety of parameters such as ambient temperature, output current and type of the core. Considering these parameters, temperature rise estimation is still complicated procedure. In this paper, we present a new model based on simple electrical equivalent circuit. This method avoids the complication associated to accurate estimation and is in very good agreement with practice.Keywords: Thermal modeling, temperature rise, equivalent thermal circuit.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 3811648 Design and Characterization of a CMOS Process Sensor Utilizing Vth Extractor Circuit
Authors: Rohana Musa, Yuzman Yusoff, Chia Chieu Yin, Hanif Che Lah
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This paper presents the design and characterization of a low power Complementary Metal Oxide Semiconductor (CMOS) process sensor. The design is targeted for implementation using Silterra’s 180 nm CMOS process technology. The proposed process sensor employs a voltage threshold (Vth) extractor architecture for detection of variations in the fabrication process. The process sensor generates output voltages in the range of 401 mV (fast-fast corner) to 443 mV (slow-slow corner) at nominal condition. The power dissipation for this process sensor is 6.3 µW with a supply voltage of 1.8V with a silicon area of 190 µm X 60 µm. The preliminary result of this process sensor that was fabricated indicates a close resemblance between test and simulated results.Keywords: CMOS Process sensor, Process, Voltage and Temperature (PVT) sensor, threshold extractor circuit, Vth extractor circuit.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 754647 Circuit Models for Conducted Susceptibility Analyses of Multiconductor Shielded Cables
Authors: Saih Mohamed, Rouijaa Hicham, Ghammaz Abdelilah
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This paper presents circuit models to analyze the conducted susceptibility of multiconductor shielded cables in frequency domains using Branin’s method, which is referred to as the method of characteristics. These models, which can be used directly in the time and frequency domains, take into account the presence of both the transfer impedance and admittance. The conducted susceptibility is studied by using an injection current on the cable shield as the source. Two examples are studied; a coaxial shielded cable and shielded cables with two parallel wires (i.e., twinax cables). This shield has an asymmetry (one slot on the side). Results obtained by these models are in good agreement with those obtained by other methods.
Keywords: Circuit models, multiconductor shielded cables, Branin’s method, coaxial shielded cable, twinax cables.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 2515646 A Novel Approach to Asynchronous State Machine Modeling on Multisim for Avoiding Function Hazards
Authors: L. Parisi, D. Hamili, N. Azlan
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The aim of this study was to design and simulate a particular type of Asynchronous State Machine (ASM), namely a ‘traffic light controller’ (TLC), operated at a frequency of 0.5 Hz. The design task involved two main stages: firstly, designing a 4-bit binary counter using J-K flip flops as the timing signal and, subsequently, attaining the digital logic by deploying ASM design process. The TLC was designed such that it showed a sequence of three different colours, i.e. red, yellow and green, corresponding to set thresholds by deploying the least number of AND, OR and NOT gates possible. The software Multisim was deployed to design such circuit and simulate it for circuit troubleshooting in order for it to display the output sequence of the three different colours on the traffic light in the correct order. A clock signal, an asynchronous 4- bit binary counter that was designed through the use of J-K flip flops along with an ASM were used to complete this sequence, which was programmed to be repeated indefinitely. Eventually, the circuit was debugged and optimized, thus displaying the correct waveforms of the three outputs through the logic analyser. However, hazards occurred when the frequency was increased to 10 MHz. This was attributed to delays in the feedback being too high.
Keywords: Asynchronous State Machine, Traffic Light Controller, Circuit Design, Digital Electronics.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 3242645 Modelling and Simulation of Cascaded H-Bridge Multilevel Single Source Inverter Using PSIM
Authors: Gaddafi S. Shehu, T. Yalcinoz, Abdullahi B. Kunya
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Multilevel inverters such as flying capacitor, diodeclamped, and cascaded H-bridge inverters are very popular particularly in medium and high power applications. This paper focuses on a cascaded H-bridge module using a single direct current (DC) source in order to generate an 11-level output voltage. The noble approach reduces the number of switches and gate drivers, in comparison with a conventional method. The anticipated topology produces more accurate result with an isolation transformer at high switching frequency. Different modulation techniques can be used for the multilevel inverter, but this work features modulation techniques known as selective harmonic elimination (SHE).This modulation approach reduces the number of carriers with reduction in Switching Losses, Total Harmonic Distortion (THD), and thereby increasing Power Quality (PQ). Based on the simulation result obtained, it appears SHE has the ability to eliminate selected harmonics by chopping off the fundamental output component. The performance evaluation of the proposed cascaded multilevel inverter is performed using PSIM simulation package and THD of 0.94% is obtained.
Keywords: Cascaded H-bridge Multilevel Inverter, Power Quality, Selective Harmonic Elimination.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 5096644 Ultimate Load Capacity of the Cable Tower of Liede Bridge
Authors: Weifeng Wang, Xilong Chen, Xianwei Zeng
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The cable tower of Liede Bridge is a double-column curved-lever arched-beam portal framed structure. Being novel and unique in structure, its cable tower differs in complexity from traditional ones. This paper analyzes the ultimate load capacity of cable tower by adopting the finite element calculations and model tests which indicate that constitutive relations applied here give a better simulation of actual failure process of prestressed reinforced concrete. In vertical load, horizontal load and overloading tests, the stepped loading of the tower model is of linear relationship, and the test data has good repeatability. All suggests that the cable tower has good bearing capacity, rational design and high emergency capacity.
Keywords: Cable tower of Liede Bridge, ultimate load capacity, model test, nonlinear finite element method
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 2116643 A Voltage Based Maximum Power Point Tracker for Low Power and Low Cost Photovoltaic Applications
Authors: Jawad Ahmad, Hee-Jun Kim
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This paper describes the design of a voltage based maximum power point tracker (MPPT) for photovoltaic (PV) applications. Of the various MPPT methods, the voltage based method is considered to be the simplest and cost effective. The major disadvantage of this method is that the PV array is disconnected from the load for the sampling of its open circuit voltage, which inevitably results in power loss. Another disadvantage, in case of rapid irradiance variation, is that if the duration between two successive samplings, called the sampling period, is too long there is a considerable loss. This is because the output voltage of the PV array follows the unchanged reference during one sampling period. Once a maximum power point (MPP) is tracked and a change in irradiation occurs between two successive samplings, then the new MPP is not tracked until the next sampling of the PV array voltage. This paper proposes an MPPT circuit in which the sampling interval of the PV array voltage, and the sampling period have been shortened. The sample and hold circuit has also been simplified. The proposed circuit does not utilize a microcontroller or a digital signal processor and is thus suitable for low cost and low power applications.
Keywords: Maximum power point tracker, Sample and hold amplifier, Sampling interval, Sampling period.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 2765642 Budget Optimization for Maintenance of Bridges in Egypt
Authors: Hesham Abd Elkhalek, Sherif M. Hafez, Yasser M. El Fahham
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Allocating limited budget to maintain bridge networks and selecting effective maintenance strategies for each bridge represent challenging tasks for maintenance managers and decision makers. In Egypt, bridges are continuously deteriorating. In many cases, maintenance works are performed due to user complaints. The objective of this paper is to develop a practical and reliable framework to manage the maintenance, repair, and rehabilitation (MR&R) activities of Bridges network considering performance and budget limits. The model solves an optimization problem that maximizes the average condition of the entire network given the limited available budget using Genetic Algorithm (GA). The framework contains bridge inventory, condition assessment, repair cost calculation, deterioration prediction, and maintenance optimization. The developed model takes into account multiple parameters including serviceability requirements, budget allocation, element importance on structural safety and serviceability, bridge impact on network, and traffic. A questionnaire is conducted to complete the research scope. The proposed model is implemented in software, which provides a friendly user interface. The framework provides a multi-year maintenance plan for the entire network for up to five years. A case study of ten bridges is presented to validate and test the proposed model with data collected from Transportation Authorities in Egypt. Different scenarios are presented. The results are reasonable, feasible and within acceptable domain.Keywords: Bridge Management Systems (BMS), cost optimization condition assessment, fund allocation, Markov chain.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1958641 Synchronization Between Two Chaotic Systems: Numerical and Circuit Simulation
Authors: J. H. Park, T. H. Lee, S. M. Lee, H. Y. Jung
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In this paper, a generalized synchronization scheme, which is called function synchronization, for chaotic systems is studied. Based on Lyapunov method and active control method, we design the synchronization controller for the system such that the error dynamics between master and slave chaotic systems is asymptotically stable. For verification of our theory, computer and circuit simulations for a specific chaotic system is conducted.
Keywords: Chaotic systems, synchronization, Lyapunov method, simulation.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1686640 Comparative Study of Evolutionary Model and Clustering Methods in Circuit Partitioning Pertaining to VLSI Design
Authors: K. A. Sumitra Devi, N. P. Banashree, Annamma Abraham
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Partitioning is a critical area of VLSI CAD. In order to build complex digital logic circuits its often essential to sub-divide multi -million transistor design into manageable Pieces. This paper looks at the various partitioning techniques aspects of VLSI CAD, targeted at various applications. We proposed an evolutionary time-series model and a statistical glitch prediction system using a neural network with selection of global feature by making use of clustering method model, for partitioning a circuit. For evolutionary time-series model, we made use of genetic, memetic & neuro-memetic techniques. Our work focused in use of clustering methods - K-means & EM methodology. A comparative study is provided for all techniques to solve the problem of circuit partitioning pertaining to VLSI design. The performance of all approaches is compared using benchmark data provided by MCNC standard cell placement benchmark net lists. Analysis of the investigational results proved that the Neuro-memetic model achieves greater performance then other model in recognizing sub-circuits with minimum amount of interconnections between them.
Keywords: VLSI, circuit partitioning, memetic algorithm, genetic algorithm.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1635639 Generalized Noise Analysis of Log Domain Static Translinear Circuits
Authors: E. Farshidi
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This paper presents a new general technique for analysis of noise in static log-domain translinear circuits. It is demonstrated that employing this technique, leads to a general, simple and routine method of the noise analysis. The circuit has been simulated by HSPICE. The simulation results are seen to conform to the theoretical analysis and shows benefits of the proposed circuit.
Keywords: Noise analysis, log-domain, static, dynamic, translinear loop, companding.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1233638 Improvement of Load Carrying Capacity of an RCC T-Beam Bridge Longitudinal Girder by Replacing Steel Bars with SMA Bars
Authors: N. K. Paul, S. Saha
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An innovative three dimensional finite element model has beed developed and tested under two point loading system to examine the structural behavior of the longitudinal reinforced concrete Tee-beam bridge girder, reinforcing with steel and shape memory alloy bars respectively. 25% of steel bars are replaced with superelastic Shape Memory Alloy bars in this study. Finite element analysis is performed using ANSYS 11.0 program. Experimentally a model of steel reinforced girder has been casted and its load deflection responses are checked with ANSYS analysis. A comparison of load carrying capacity for the model between steel RC girder and the girder combined reinforcement with SMA and steel are also performed.
Keywords: Shape memory alloy, bridge girder, ANSYS, load-deflection.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 887637 Modeling and Simulation of Practical Metamaterial Structures
Authors: Ridha Salhi, Mondher Labidi, Fethi Choubani
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Metamaterials have attracted much attention in recent years because of their electromagnetic exquisite proprieties. We will present, in this paper, the modeling of three metamaterial structures by equivalent circuit model. We begin by modeling the SRR (Split Ring Resonator), then we model the HIS (High Impedance Surfaces), and finally, we present the model of the CPW (Coplanar Wave Guide). In order to validate models, we compare the results obtained by an equivalent circuit models with numerical simulation.Keywords: Metamaterials, SRR, HIS, CPW, IDC.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1757636 Off-State Leakage Power Reduction by Automatic Monitoring and Control System
Authors: S. Abdollahi Pour, M. Saneei
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This paper propose a new circuit design which monitor total leakage current during standby mode and generates the optimal reverse body bias voltage, by using the adaptive body bias (ABB) technique to compensate die-to-die parameter variations. Design details of power monitor are examined using simulation framework in 65nm and 32nm BTPM model CMOS process. Experimental results show the overhead of proposed circuit in terms of its power consumption is about 10 μW for 32nm technology and about 12 μW for 65nm technology at the same power supply voltage as the core power supply. Moreover the results show that our proposed circuit design is not far sensitive to the temperature variations and also process variations. Besides, uses the simple blocks which offer good sensitivity, high speed, the continuously feedback loop.Keywords: leakage current, leakage power monitor, body biasing, low power
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1739635 Phasor Analysis of a Synchronous Generator: A Bond Graph Approach
Authors: Israel Núñez-Hernández, Peter C. Breedveld, Paul B. T. Weustink, Gilberto Gonzalez-A
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This paper presents the use of phasor bond graphs to obtain the steady-state behavior of a synchronous generator. The phasor bond graph elements are built using 2D multibonds, which represent the real and imaginary part of the phasor. The dynamic bond graph model of a salient-pole synchronous generator is showed, and verified viz. a sudden short-circuit test. The reduction of the dynamic model into a phasor representation is described. The previous test is executed on the phasor bond graph model, and its steady-state values are compared with the dynamic response. Besides, the widely used power (torque)-angle curves are obtained by means of the phasor bond graph model, to test the usefulness of this model.
Keywords: Bond graphs, complex power, phasors, synchronous generator, short-circuit, open-circuit, power-angle curve.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 2553634 Fault Classification of Double Circuit Transmission Line Using Artificial Neural Network
Authors: Anamika Jain, A. S. Thoke, R. N. Patel
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This paper addresses the problems encountered by conventional distance relays when protecting double-circuit transmission lines. The problems arise principally as a result of the mutual coupling between the two circuits under different fault conditions; this mutual coupling is highly nonlinear in nature. An adaptive protection scheme is proposed for such lines based on application of artificial neural network (ANN). ANN has the ability to classify the nonlinear relationship between measured signals by identifying different patterns of the associated signals. One of the key points of the present work is that only current signals measured at local end have been used to detect and classify the faults in the double circuit transmission line with double end infeed. The adaptive protection scheme is tested under a specific fault type, but varying fault location, fault resistance, fault inception angle and with remote end infeed. An improved performance is experienced once the neural network is trained adequately, which performs precisely when faced with different system parameters and conditions. The entire test results clearly show that the fault is detected and classified within a quarter cycle; thus the proposed adaptive protection technique is well suited for double circuit transmission line fault detection & classification. Results of performance studies show that the proposed neural network-based module can improve the performance of conventional fault selection algorithms.
Keywords: Double circuit transmission line, Fault detection and classification, High impedance fault and Artificial Neural Network.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 3185633 Traditionally Sustainability Analyses of Hydraulic-Architectural Bridge Construction in Iran
Authors: Karim Shiraazi, Zargham OstadiAsl, Vahid Sheikhloie, Ahadollah Azami, Shahin Hassanimehr
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Bridge is an architectural symbol in Iran as Badgir (wind catcher); fire temples and arch are vaults are such. Therefore, from the very old ages, construction of bridges in Iran has mixed with architecture, social customs, alms and charity and holiness. Since long ago, from Mad, Achaemenid, Parthian and Sassanid times which construction of bridges got an inseparable relation with social dependency and architecture, based on those dependency bridges and dams got holy names; as Dokhtar castle and Dokhtar bridges were constructed. This method continued even after Islam and whenever Iranians got free from political fights and the immunity of roads were established the bridge construction did also prospered. In ancient times bridge construction passes through it growing and completion process and in Sassanid time in some way it reached to the peak of art and glory; as after Islam especially during 4th. century (Arab calendar) it put behind a period of glory and in Safavid time it reached to an exceptional glory and magnificence by constructing glorious bridges on Zayandeh Roud River in Isfahan. Having a combined style and changeability into bridge barrier, some of these bridges develop into magnificent constructions. The sustainable structures, mentioned above, are constructed for various reasons as follows: connecting two sides of a river, storing water, controlling floods, using water energy to operate water windmills, making lanes of streams for farms- use, and building recreational places for people, etc. These studies carried in bridges reveals the fact that in construction and designing mentioned above, lots of technological factors have been taken into consideration such as exceeding floods in the rives, hydraulic and hydrology of the rivers and bridges, geology, foundation, structure, construction material, and adopting appropriate executing methods, all of which are being analyzed in this article.Keywords: Hydraulic-Architectural Bridge, Sustainability, Construction
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 2047632 Hardware Implementation of Stack-Based Replacement Algorithms
Authors: Hassan Ghasemzadeh, Sepideh Mazrouee, Hassan Goldani Moghaddam, Hamid Shojaei, Mohammad Reza Kakoee
Abstract:
Block replacement algorithms to increase hit ratio have been extensively used in cache memory management. Among basic replacement schemes, LRU and FIFO have been shown to be effective replacement algorithms in terms of hit rates. In this paper, we introduce a flexible stack-based circuit which can be employed in hardware implementation of both LRU and FIFO policies. We propose a simple and efficient architecture such that stack-based replacement algorithms can be implemented without the drawbacks of the traditional architectures. The stack is modular and hence, a set of stack rows can be cascaded depending on the number of blocks in each cache set. Our circuit can be implemented in conjunction with the cache controller and static/dynamic memories to form a cache system. Experimental results exhibit that our proposed circuit provides an average value of 26% improvement in storage bits and its maximum operating frequency is increased by a factor of twoKeywords: Cache Memory, Replacement Algorithms, LeastRecently Used Algorithm, First In First Out Algorithm.
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