A Novel Approach to Asynchronous State Machine Modeling on Multisim for Avoiding Function Hazards

Authors: L. Parisi, D. Hamili, N. Azlan

Abstract:

The aim of this study was to design and simulate a particular type of Asynchronous State Machine (ASM), namely a ‘traffic light controller’ (TLC), operated at a frequency of 0.5 Hz. The design task involved two main stages: firstly, designing a 4-bit binary counter using J-K flip flops as the timing signal and, subsequently, attaining the digital logic by deploying ASM design process. The TLC was designed such that it showed a sequence of three different colours, i.e. red, yellow and green, corresponding to set thresholds by deploying the least number of AND, OR and NOT gates possible. The software Multisim was deployed to design such circuit and simulate it for circuit troubleshooting in order for it to display the output sequence of the three different colours on the traffic light in the correct order. A clock signal, an asynchronous 4- bit binary counter that was designed through the use of J-K flip flops along with an ASM were used to complete this sequence, which was programmed to be repeated indefinitely. Eventually, the circuit was debugged and optimized, thus displaying the correct waveforms of the three outputs through the logic analyser. However, hazards occurred when the frequency was increased to 10 MHz. This was attributed to delays in the feedback being too high.

Keywords: Asynchronous State Machine, Traffic Light Controller, Circuit Design, Digital Electronics.

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1099128

References:

[1] Mary Bellis, History of Traffic Lights. Available at: http://inventors.about.com/History-Of-Roads_3.htm..
[2] Ricardo O Rabinovich, (1994). Transition maps guide successful asynchronous state-machine design. Electronics Design Strategy News. Available at: http://www.edn.com/archives/1994/051294/10df2.htm. Last accessed on: December, 1st, 2014.
[3] Hayes, J. (1994). Digital Logic Design. Addison –Wesley. p. 443-446.
[4] Asynchronous Counters. Available at: http://www.allaboutcircuits.com/ vol_4/chpt_11/2.html.
[5] Sequential Information. http://inst.eecs.berkeley.edu/~cs150/fa05/ Lectures/07-SeqLogicIIIx2.pdf.
[6] Interface BUS, (2012). Glue Logic Timing Hazards. Available at: http://www.interfacebus.com/Design_Logic_Timing_Hazards.html. Last accessed on: December, 2nd, 2014.
[7] Strom, E. G., Parkvall, S., Miller, S. & Otterson, B. (1996). Propagation Delay Estimation in Asynchronous Direct-sequence code-division multiple access systems.. IEEE Transactions on Communicaitions., 44 (1), p. 84-93.
[8] ECE 152A - Digital Design Principles. (2012). Propagation Delay, Circuit Timing and Adder Design. Available at: http://www.ece.ucsb.edu/Faculty/Johnson/ECE152A/L4/%20Propagatio n%20Delay%20Circuit%20Timing%20Adder%20Design.pdf. Last accessed on: December, 2nd, 2014.
[9] Global Spec, (2007). Complex Programmable Logic Devices (CPLD) Information. Available at: http://www.globalspec.com/learnmore/ analog_digital_ics/programmable_logic/complex_programmable_logic_ devices_cpld. Last accessed on: November, 28th, 2014.
[10] Hewes, J. (2011). Multiple Input Gates. Available at: http://www.allaboutcircuits.com/vol_4/chpt_3/4.html. Last accessed on: December, 2nd, 2014.
[11] 555 timer IC. Available at: http://www.doctronics.co.uk/555.htm. Last accessed: December, 1st, 2014.
[12] Tinder, R. (2000). Chapter 9 - Propagation Delay and Timing Defects in Combinational Logic, Engineering Digital Design, Academic Press San Diego, p. 391-418.