Search results for: large bandwidth delay product.

Authors: B. Fahimnia, L.H.S. Luong, B. Motevallian, R. M. Marian, M. M. Esmaeil

Abstract:

Product Lead Time (PLT) is the period of time from receiving a customer's order to delivering the final product. PLT is an indicator of the manufacturing controllability, efficiency and performance. Due to the explosion in the rate of technological innovations and the rapid changes in the nature of manufacturing processes, manufacturing firms can bring the new products to market quicker only if they can reduce their PLT and speed up the rate at which they can design, plan, control, and manufacture. Although there is a substantial body of research on manufacturing relating to cost and quality issues, there is no much specific research conducted in relation to the formulation of PLT, despite its significance and importance. This paper analyzes and formulates PLT which can be used as a guideline for achieving the shorter PLT. Further more this paper identifies the causes of delay and factors that contributes to the increased product lead-time.

Keywords: Manufacturing Control, Manufacturing Lead Time, Manufacturing Planning, Product Design, and Product Lead Time.

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Authors: Eman I. Raslan, Haitham S. Hamza, Reda A. El-Khoribi

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Fiber-Wireless (FiWi) networks are a promising candidate for future broadband access networks. These networks combine the optical network as the back end where different passive optical network (PON) technologies are realized and the wireless network as the front end where different wireless technologies are adopted, e.g. LTE, WiMAX, Wi-Fi, and Wireless Mesh Networks (WMNs). The convergence of both optical and wireless technologies requires designing architectures with robust efficient and effective bandwidth allocation schemes. Different bandwidth allocation algorithms have been proposed in FiWi networks aiming to enhance the different segments of FiWi networks including wireless and optical subnetworks. In this survey, we focus on the differentiating between the different bandwidth allocation algorithms according to their enhancement segment of FiWi networks. We classify these techniques into wireless, optical and Hybrid bandwidth allocation techniques.

Keywords: Fiber-Wireless (FiWi), dynamic bandwidth allocation (DBA), passive optical networks (PON), media access control (MAC).

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Authors: Sergei Aleinik, Mikhail Stolbov

Abstract:

In this work, a method of time delay estimation for  dual-channel acoustic signals (speech, music, etc.) recorded under  reverberant conditions is investigated. Standard methods based on  cross-correlation of the signals show poor results in cases involving  strong reverberation, large distances between microphones and  asynchronous recordings. Under similar conditions, a method based  on cross-correlation of temporal envelopes of the signals delivers a  delay estimation of acceptable quality. This method and its properties  are described and investigated in detail, including its limits of  applicability. The method’s optimal parameter estimation and a  comparison with other known methods of time delay estimation are  also provided.

 

Keywords: Cross-correlation, delay estimation, signal envelope, signal processing.

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Authors: Omar F. Hamad, T. Marwala

Abstract:

With optimized bandwidth and latency discrepancy ratios, Node Gain Scores (NGSs) are determined and used as a basis for shaping the max-heap overlay. The NGSs - determined as the respective bandwidth-latency-products - govern the construction of max-heap-form overlays. Each NGS is earned as a synergy of discrepancy ratio of the bandwidth requested with respect to the estimated available bandwidth, and latency discrepancy ratio between the nodes and the source node. The tree leads to enhanceddelivery overlay multicasting – increasing packet delivery which could, otherwise, be hindered by induced packet loss occurring in other schemes not considering the synergy of these parameters on placing the nodes on the overlays. The NGS is a function of four main parameters – estimated available bandwidth, Ba; individual node's requested bandwidth, Br; proposed node latency to its prospective parent (Lp); and suggested best latency as advised by source node (Lb). Bandwidth discrepancy ratio (BDR) and latency discrepancy ratio (LDR) carry weights of α and (1,000 - α ) , respectively, with arbitrary chosen α ranging between 0 and 1,000 to ensure that the NGS values, used as node IDs, maintain a good possibility of uniqueness and balance between the most critical factor between the BDR and the LDR. A max-heap-form tree is constructed with assumption that all nodes possess NGS less than the source node. To maintain a sense of load balance, children of each level's siblings are evenly distributed such that a node can not accept a second child, and so on, until all its siblings able to do so, have already acquired the same number of children. That is so logically done from left to right in a conceptual overlay tree. The records of the pair-wise approximate available bandwidths as measured by a pathChirp scheme at individual nodes are maintained. Evaluation measures as compared to other schemes – Bandwidth Aware multicaSt architecturE (BASE), Tree Building Control Protocol (TBCP), and Host Multicast Tree Protocol (HMTP) - have been conducted. This new scheme generally performs better in terms of trade-off between packet delivery ratio; link stress; control overhead; and end-to-end delays.

Keywords: Overlay multicast, Available bandwidth, Max-heapform overlay, Induced packet loss, Bandwidth-latency product, Node Gain Score (NGS).

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Authors: Xingyuan Qu, Shouming Zhong

Abstract:

In this paper, the problem of stability criteria of neural networks (NNs) with two-additive time-varying delay compenents is investigated. The relationship between the time-varying delay and its lower and upper bounds is taken into account when estimating the upper bound of the derivative of Lyapunov functional. As a result, some improved delay stability criteria for NNs with two-additive time-varying delay components are proposed. Finally, a numerical example is given to illustrate the effectiveness of the proposed method.

Keywords: Delay-dependent stability, time-varying delays, Lyapunov functional, linear matrix inequality (LMI).

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Authors: P.Ramanathan, P.T.Vanathi

Abstract:

Parallel Prefix addition is a technique for improving the speed of binary addition. Due to continuing integrating intensity and the growing needs of portable devices, low-power and highperformance designs are of prime importance. The classical parallel prefix adder structures presented in the literature over the years optimize for logic depth, area, fan-out and interconnect count of logic circuits. In this paper, a new architecture for performing 8-bit, 16-bit and 32-bit Parallel Prefix addition is proposed. The proposed prefix adder structures is compared with several classical adders of same bit width in terms of power, delay and number of computational nodes. The results reveal that the proposed structures have the least power delay product when compared with its peer existing Prefix adder structures. Tanner EDA tool was used for simulating the adder designs in the TSMC 180 nm and TSMC 130 nm technologies.

Keywords: Parallel Prefix Adder (PPA), Dot operator, Semi-Dotoperator, Complementary Metal Oxide Semiconductor (CMOS), Odd-dot operator, Even-dot operator, Odd-semi-dot operator andEven-semi-dot operator.

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Authors: P.S.Prakash, S.Selvan

Abstract:

QoS Routing aims to find paths between senders and receivers satisfying the QoS requirements of the application which efficiently using the network resources and underlying routing algorithm to be able to find low-cost paths that satisfy given QoS constraints. The problem of finding least-cost routing is known to be NP hard or complete and some algorithms have been proposed to find a near optimal solution. But these heuristics or algorithms either impose relationships among the link metrics to reduce the complexity of the problem which may limit the general applicability of the heuristic, or are too costly in terms of execution time to be applicable to large networks. In this paper, we analyzed two algorithms namely Characterized Delay Constrained Routing (CDCR) and Optimized Delay Constrained Routing (ODCR). The CDCR algorithm dealt an approach for delay constrained routing that captures the trade-off between cost minimization and risk level regarding the delay constraint. The ODCR which uses an adaptive path weight function together with an additional constraint imposed on the path cost, to restrict search space and hence ODCR finds near optimal solution in much quicker time.

Keywords: QoS, Delay, Routing, Optimization

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Authors: Yavar Safaei Mehrabani, Mehdi Hosseinzadeh

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As embedded and portable systems were emerged power consumption of circuits had been major challenge. On the other hand latency as determines frequency of circuits is also vital task. Therefore, trade off between both of them will be desirable. Modulo 2n+1 adders are important part of the residue number system (RNS) based arithmetic units with the interesting moduli set (2n-1,2n, 2n+1). In this manuscript we have introduced novel binary representation to the design of modulo 2n+1 adder. VLSI realization of proposed architecture under 180 nm full static CMOS technology reveals its superiority in terms of area, power consumption and power-delay product (PDP) against several peer existing structures.

Keywords: Computer arithmetic, modulo 2n+1 adders, Residue Number System (RNS), VLSI.

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Authors: Manas Ranjan Kabat, Manoj Kumar Patel, Chita Ranjan Tripathy

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Many multimedia communication applications require a source to transmit messages to multiple destinations subject to quality of service (QoS) delay constraint. To support delay constrained multicast communications, computer networks need to guarantee an upper bound end-to-end delay from the source node to each of the destination nodes. This is known as multicast delay problem. On the other hand, if the same message fails to arrive at each destination node at the same time, there may arise inconsistency and unfairness problem among users. This is related to multicast delayvariation problem. The problem to find a minimum cost multicast tree with delay and delay-variation constraints has been proven to be NP-Complete. In this paper, we propose an efficient heuristic algorithm, namely, Economic Delay and Delay-Variation Bounded Multicast (EDVBM) algorithm, based on a novel heuristic function, to construct an economic delay and delay-variation bounded multicast tree. A noteworthy feature of this algorithm is that it has very high probability of finding the optimal solution in polynomial time with low computational complexity.

Keywords: EDVBM, Heuristic algorithm, Multicast tree, QoS routing, Shortest path.

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Authors: T. Arsan

Abstract:

Video streaming over lossy IP networks is very important issues, due to the heterogeneous structure of networks. Infrastructure of the Internet exhibits variable bandwidths, delays, congestions and time-varying packet losses. Because of variable attributes of the Internet, video streaming applications should not only have a good end-to-end transport performance but also have a robust rate control, furthermore multipath rate allocation mechanism. So for providing the video streaming service quality, some other components such as Bandwidth Estimation and Adaptive Rate Controller should be taken into consideration. This paper gives an overview of video streaming concept and bandwidth estimation tools and then introduces special architectures for bandwidth adaptive video streaming. A bandwidth estimation algorithm – pathChirp, Optimized Rate Controllers and Multipath Rate Allocation Algorithm are considered as all-in-one solution for video streaming problem. This solution is directed and optimized by a decision center which is designed for obtaining the maximum quality at the receiving side.

Keywords: Adaptive Video Streaming, Bandwidth Estimation, QoS, Software Architecture.

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Authors: Ankit Jain, Archana Agrawal

Abstract:

With the ever-increasing need for wireless communication and the emergence of many systems, it is important to design broadband antennas to cover a wide frequency range. The aim of this paper is to design a broadband patch antenna, employing the three techniques of slotting, adding directly coupled parasitic elements, and fractal EBG structures. The bandwidth is improved from 9.32% to 23.77%. A wideband ranging from 4.15 GHz to 5.27 GHz is obtained. Also a comparative analysis of embedding EBG structures at different heights is also done. The composite effect of integrating these techniques in the design provides a simple and efficient method for obtaining low profile, broadband, high gain antenna. By the addition of parasitic elements the bandwidth was increased to only 18.04%. Later on by embedding EBG structures the bandwidth was increased up to 23.77%. The design is suitable for variety of wireless applications like WLAN and Radar Applications.

Keywords: Bandwidth, broadband, EBG structures, parasitic elements, Slotting.

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Authors: N. Seladji-Hassaine, L. Merad, S.M. Meriah, F.T. Bendimerad

Abstract:

UWB is a very attractive technology for many applications. It provides many advantages such as fine resolution and high power efficiency. Our interest in the current study is the use of UWB radar technique in microwave medical imaging systems, especially for early breast cancer detection. The Federal Communications Commission FCC allowed frequency bandwidth of 3.1 to 10.6 GHz for this purpose. In this paper we suggest an UWB Bowtie slot antenna with enhanced bandwidth. Effects of varying the geometry of the antenna on its performance and bandwidth are studied. The proposed antenna is simulated in CST Microwave Studio. Details of antenna design and simulation results such as return loss and radiation patterns are discussed in this paper. The final antenna structure exhibits good UWB characteristics and has surpassed the bandwidth requirements.

Keywords: Ultra Wide Band (UWB), microwave imaging system, Bowtie antenna, return loss, impedance bandwidth enhancement.

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Authors: Zarabizan Zakaria, Syuhaida Ismail, Aminah Md. Yusof

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Delay can be defined as time overrun or extension of time to complete the project. There are high possibilities that delay issues in final account closing cannot be avoided especially in construction project in Malaysia which is unique and dynamic in the terms of nature of design and technical skill. Delay in final account closing is a situation when the actual planning (time and budget allocation) of a construction project exceeds the planned schedule or on the other hand, final account closing exceeds the time and other provisions specified in the contract. The causes of delay discussed in this paper are appraised from the literature review. There are two main types of delay: excusable delay and non-excusable delay. The literature reviews on the delay in final account closing which is then translated into a theoretical framework are summarized in the context of construction players and academician perspective. It is anticipated that the finding reported in this paper could assist the planning of future strategies and guidelines of final account closing for the betterment of construction projects in Malaysia.

Keywords: Construction industry, construction contract, final account closing, delay.

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Authors: Sanghoon Park, Kijin Kim, Kwangho Ahn

Abstract:

An active RC filters with a 880 / 1760 MHz dual bandwidth tuning ability is present for 60 GHz unlicensed band applications. A third order Butterworth low-pass filter utilizes two Cherry-Hooper amplifiers to satisfy the very high bandwidth requirements of an amplifier. The low-pass filter is fabricated in 90nm standard CMOS process. Drawing 6.7 mW from 1.2 V power supply, the low frequency gains of the filter are -2.5 and -4.1 dB, and the output third order intercept points (OIP3) are +2.2 and +1.9 dBm for the single channel and channel bonding conditions, respectively.

Keywords: Butterworth filter, active RC, 60 GHz, CMOS, dual bandwidth, Cherry-Hooper amplifier.

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Authors: Qingqing Wang, Shouming Zhong

Abstract:

In this paper, delay-dependent stability analysis for neutral type neural networks with uncertain paramters and time-varying delay is studied. By constructing new Lyapunov-Krasovskii functional and dividing the delay interval into multiple segments, a novel sufficient condition is established to guarantee the globally asymptotically stability of the considered system. Finally, a numerical example is provided to illustrate the usefulness of the proposed main results.

Keywords: Neutral type neural networks, Time-varying delay, Stability, Linear matrix inequality(LMI).

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Authors: R. Reka, R. S. D. Wahidabanu

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The aim of this paper is to propose a novel technique to guarantee Quality of Service (QoS) in a highly dynamic environment. The MANET changes its topology dynamically as the nodes are moved frequently. This will cause link failure between mobile nodes. MANET cannot ensure reliability without delay. The relay node is selected based on achieving QoS in previous transmission. It considers one more factor Connection Existence Period (CEP) to ensure reliability. CEP is to find out the period during that connection exists between the nodes. The node with highest CEP becomes a next relay node. The relay node is selected dynamically to avoid frequent failure. The bandwidth of each link changed dynamically based on service rate and request rate. This paper proposes Active bandwidth setting up algorithm to guarantee the QoS. The series of results obtained by using the Network Simulator (NS-2) demonstrate the viability of our proposed techniques.

Keywords: Bandwidth, Connection Existence Period (CEP), Mobile Adhoc Network (MANET), Quality of Service (QoS), Relay node.

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Authors: Laurent Enel, Franck Guillem

Abstract:

This paper considers the benefits gained by using an efficient quality of service management such as DiffServ technique to improve the performance of military communications. Low delay and no blockage must be achieved especially for real time tactical data. All traffic flows generated by different applications do not need same bandwidth, same latency, same error ratio and this scalable technique of packet management based on priority levels is analysed. End to end architectures supporting various traffic flows and including lowbandwidth and high-delay HF or SHF military links as well as unprotected Internet sub domains are studied. A tuning of Diffserv parameters is proposed in accordance with different loads of various traffic and different operational situations.

Keywords: Military data networks, Quality of service, Tacticalsystems.

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Authors: N. Hamzah, M.A. Khoiry, I. Arshad, W.H.W. Badaruzzaman, N. M. Tawil

Abstract:

Construction delay is unavoidable in developing countries including Malaysia. It is defined as time overrun or extension of time for completion of a project. The purpose of the study is to determine the causes of delay in Malaysian construction industries based on previous worldwide research. The field survey conducted includes the experienced developers, consultants and contractors in Malaysia. 34 causes of the construction delay have been determined and 24 have been selected using the Rasch model analysis. The analysis result will be used as the baseline for the next research to find the causes of delay in the Malaysian construction industry taking place in Malaysian higher learning institutions.

Keywords: Causes of construction delay, construction projects, Malaysian construction industry, Rasch model analysis.

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Authors: S. Mohideen Badhusha, K. Duraiswamy

Abstract:

Most of the existing video streaming protocols provide video services without considering security aspects in decentralized mobile ad-hoc networks. The security policies adapted to the currently existing non-streaming protocols, do not comply with the live video streaming protocols resulting in considerable vulnerability, high bandwidth consumption and unreliability which cause severe security threats, low bandwidth and error prone transmission respectively in video streaming applications. Therefore a synergized methodology is required to reduce vulnerability and bandwidth consumption, and enhance reliability in the video streaming applications in MANET. To ensure the security measures with reduced bandwidth consumption and improve reliability of the video streaming applications, a Secure Low-bandwidth Video Streaming through Reliable Multipath Propagation (SLVRMP) protocol architecture has been proposed by incorporating the two algorithms namely Secure Low-bandwidth Video Streaming Algorithm and Reliable Secure Multipath Propagation Algorithm using Layered Video Coding in non-overlapping zone routing network topology. The performances of the proposed system are compared to those of the other existing secure multipath protocols Sec-MR, SPREAD using NS 2.34 and the simulation results show that the performances of the proposed system get considerably improved.

Keywords: Bandwidth consumption, layered video coding, multipath propagation, reliability, security threats, video streaming applications, vulnerability.

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Authors: Chutima Prommak, Airisa Jantaweetip

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In wireless networks, bandwidth is scare resource and it is essential to utilize it effectively. This paper analyses effects of using different bandwidth management techniques on the network performances of the Wireless Local Area Networks (WLANs) that use hybrid load balancing scheme. In particular, we study three bandwidth management schemes, namely Complete Sharing (CS), Complete Partitioning (CP), and Partial Sharing (PS). Performances of these schemes are evaluated by simulation experiments in term of percentage of network association blocking. Our results show that the CS scheme can provide relatively low blocking percentage in various network traffic scenarios whereas the PS scheme can enhance quality of services of the multimedia traffic with rather small expenses on the blocking percentage of the best effort traffic.

Keywords: Bandwidth management, Load Balancing, WLANs.

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Authors: Myeongjin Park, Ohmin Kwon, Juhyun Park, Sangmoon Lee

Abstract:

This paper proposes improved delay-dependent stability conditions of the linear time-delay systems of neutral type. The proposed methods employ a suitable Lyapunov-Krasovskii’s functional and a new form of the augmented system. New delay-dependent stability criteria for the systems are established in terms of Linear matrix inequalities (LMIs) which can be easily solved by various effective optimization algorithms. Numerical examples showed that the proposed method is effective and can provide less conservative results.

Keywords: Neutral systems, Time-delay, Stability, Lyapunovmethod, LMI.

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Authors: Vijay Kumar Sharma, Manisha Pattanaik, Balwinder Raj

Abstract:

Minimizations of power dissipation, chip area with higher circuit performance are the necessary and key parameters in deep submicron regime. The leakage current increases sharply in deep submicron regime and directly affected the power dissipation of the logic circuits. In deep submicron region the power dissipation as well as high performance is the crucial concern since increasing importance of portable systems. Number of leakage reduction techniques employed to reduce the leakage current in deep submicron region but they have some trade-off to control the leakage current. ONOFIC approach gives an excellent agreement between power dissipation and propagation delay for designing the efficient CMOS logic circuits. In this article ONOFIC approach is compared with LECTOR technique and output results show that ONOFIC approach significantly reduces the power dissipation and enhance the speed of the logic circuits. The lower power delay product is the big outcome of this approach and makes it an influential leakage reduction technique.

Keywords: Deep submicron, Leakage Current, LECTOR, ONOFIC, Power Delay Product

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Authors: D. P. Clayton, E. A. Ball

Abstract:

This paper describes an investigation into the isolation characteristics and bandwidth performance of radio frequency (RF) combiners that are used as part of Chireix power amplifier (PA) architectures, designed for use in the X-Band range of frequencies. Combiner designs investigated are the typical Chireix and Wilkinson configurations which also include simulation of the Wilkinson using manufacturer’s data for the isolation resistor. Another simulation was the less common approach of using a Branchline coupler to form the combiner, as well as simulation results from adding an additional stage. This paper presents the findings of this investigation and compares the bandwidth performance and isolation characteristics to determine suitability.

Keywords: Bandwidth, Chireix, couplers, outphasing, power amplifiers, Wilkinson, X-Band.

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Authors: Jonah Gamba

Abstract:

In this paper the problem of estimating the time delay between two spatially separated noisy sinusoidal signals by system identification modeling is addressed. The system is assumed to be perturbed by both input and output additive white Gaussian noise. The presence of input noise introduces bias in the time delay estimates. Normally the solution requires a priori knowledge of the input-output noise variance ratio. We utilize the cascade of a self-tuned filter with the time delay estimator, thus making the delay estimates robust to input noise. Simulation results are presented to confirm the superiority of the proposed approach at low input signal-to-noise ratios.

Keywords: LMS algorithm, Self-tuned filter, Systemidentification, Time delay estimation, .

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Authors: Hafiz Muhammad Obaid, Umais Tayyab, Shabbir Majeed Ch.

Abstract:

In this paper, a CMOS differential operational transresistance amplifier (OTRA) is presented. The amplifier is designed and implemented in a standard umc90-nm CMOS technology. The differential OTRA provides wider bandwidth at high gain. It also shows much better rise and fall time and exhibits a very good input current dynamic range of 50 to 50 μA. The OTRA can be used in many analog VLSI applications. The presented amplifier has high gain bandwidth product of 617.6 THz Ω. The total power dissipation of the presented amplifier is also very low and it is 0.21 mW.

Keywords: CMOS, differential, operational transresistance amplifier, OTRA, 90 nm, VLSI.

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Authors: Somenath Mukherjee, Rajdeep Ray, Raj Kumar Samanta, Mofazzal H. Khondekar, Gautam Sanyal

Abstract:

In next generation wireless networks (i.e., 4G and beyond), one of the main objectives is to ensure highest level of customer satisfaction in terms of data transfer speed, decrease in cost and delay, non-rejection and no drop of calls, availability of ‘always-on’ connectivity and services, continuity of connected services, hastle-free roaming in addition to the convenience of use of network services from anywhere and anytime. To take care of these requirements effectively, internet service providers (ISPs) and network planners have to go for major capacity enhancement of network resources and at the same time these resources are to be used effectively and efficiently to reduce cost and to increase revenue. In this work, the effective bandwidth available in a Mobile Switching Center (MSC) of a wireless network providing multi-class multimedia services is analyzed. Bandwidth requirement of the users for a customized Quality of Service (QoS) is estimated. The findings of the QoS estimation are applied for the capacity planning and admission control of the multi-class traffic flows coming into the MSC.

Keywords: Next generation wireless network, mobile switching center, multi-class traffic, quality of service, admission control, effective bandwidth.

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Authors: Shubhajit Roy Chowdhury, Aritra Banerjee, Aniruddha Roy, Hiranmay Saha

Abstract:

The paper proposes the novel design of a 3T XOR gate combining complementary CMOS with pass transistor logic. The design has been compared with earlier proposed 4T and 6T XOR gates and a significant improvement in silicon area and power-delay product has been obtained. An eight transistor full adder has been designed using the proposed three-transistor XOR gate and its performance has been investigated using 0.15um and 0.35um technologies. Compared to the earlier designed 10 transistor full adder, the proposed adder shows a significant improvement in silicon area and power delay product. The whole simulation has been carried out using HSPICE.

Keywords: XOR gate, full adder, improvement in speed, area minimization, transistor count minimization.

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Authors: Yingguo Li

Abstract:

In this paper, we consider a discrete Gompertz model with time delay. Firstly, the stability of the equilibrium of the system is investigated by analyzing the characteristic equation. By choosing the time delay as a bifurcation parameter, we prove that Neimark- Sacker bifurcations occur when the delay passes a sequence of critical values. The direction and stability of the Neimark-Sacker are determined by using normal forms and centre manifold theory. Finally, some numerical simulations are given to verify the theoretical analysis.

Keywords: Gompertz system, Neimark-Sacker bifurcation, stability, time delay.

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Authors: P. Asadee

Abstract:

Multiplication algorithms have considerable effect on processors performance. A new high-speed, low-power multiplication algorithm has been presented using modified Dadda tree structure. Three important modifications have been implemented in inner product generation step, inner product reduction step and final addition step. Optimized algorithms have to be used into basic computation components, such as multiplication algorithms. In this paper, we proposed a new algorithm to reduce power, delay, and transistor count of a multiplication algorithm implemented using low power modified counter. This work presents a novel design for Dadda multiplication algorithms. The proposed multiplication algorithm includes structured parts, which have important effect on inner product reduction tree. In this paper, a 1.3V, 64-bit carry hybrid adder is presented for fast, low voltage applications. The new 64-bit adder uses a new circuit to implement the proposed carry hybrid adder. The new adder using 80 nm CMOS technology has been implemented on 700 MHz clock frequency. The proposed multiplication algorithm has achieved 14 percent improvement in transistor count, 13 percent reduction in delay and 12 percent modification in power consumption in compared with conventional designs.

Keywords: adder, CMOS, counter, Dadda tree, encoder.

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Authors: Mohsen Maadani, Seyed Ahmad Motamedi

Abstract:

The use of wireless technology in industrial networks has gained vast attraction in recent years. In this paper, we have thoroughly analyzed the effect of contention window (CW) size on the performance of IEEE 802.11-based industrial wireless networks (IWN), from delay and reliability perspective. Results show that the default values of CWmin, CWmax, and retry limit (RL) are far from the optimum performance due to the industrial application characteristics, including short packet and noisy environment. In this paper, an adaptive CW algorithm (payload-dependent) has been proposed to minimize the average delay. Finally a simple, but effective CW and RL setting has been proposed for industrial applications which outperforms the minimum-average-delay solution from maximum delay and jitter perspective, at the cost of a little higher average delay. Simulation results show an improvement of up to 20%, 25%, and 30% in average delay, maximum delay and jitter respectively.

Keywords: Average Delay, Contention Window, Distributed Coordination Function (DCF), Jitter, Industrial Wireless Network (IWN), Maximum Delay, Reliability, Retry Limit.

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