Search results for: hardware compiler

Authors: Fengchi Shen, Rongtao Ding

Abstract:

The Informational Infrastructures of small and medium-sized manufacturing enterprises are relatively poor, there are serious shortages of capitals which can be invested in informatization construction, computer hardware and software resources, and human resources. To address the informatization issue in small and medium-sized manufacturing enterprises, and enable them to the application of advanced management thinking and enhance their competitiveness, the paper establish a manufacturing-oriented small and medium-sized enterprises informatization platform based on the ASP business intelligence technology, which effectively improves the scientificity of enterprises decision and management informatization.

Keywords: ASP, business intelligence, data warehouse.

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Authors: Da-Hye Kim, Won-Hyung Park, In-Ho Yun, Jeong Cheol Kim, Sang-Youn Kim

Abstract:

This paper presents an authoring tool which makes a user easily and intuitively design vibrotactile sensation. A mobile hardware platform powered by ANDROID, a multi-purpose haptic driver and a linear resonance actuator are used to implement the system of the presented authoring tool. The tool allows users to easily and simply create a vibrotactile sensation by drawing vibrotactile images and to feel the sensation by rubbing drawn images on the touch screen of a mobile device. The tool supports a graphical interface for designing, editing and playing vibrotactile images as well as a pre-defined file format for save and open.

Keywords: authoring tool, mobile device, vibrotactile pattern, vibrotactile sensation

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Authors: Khaled Shehata, Hanady Hussien, Sara Yehia

Abstract:

Securing the data stored on E-passport is a very important issue. RSA encryption algorithm is suitable for such application with low data size. In this paper the design and implementation of 1024 bit-key RSA encryption and decryption module on an FPGA is presented. The module is verified through comparing the result with that obtained from MATLAB tools. The design runs at a frequency of 36.3 MHz on Virtex-5 Xilinx FPGA. The key size is designed to be 1024-bit to achieve high security for the passport information. The whole design is achieved through VHDL design entry which makes it a portable design and can be directed to any hardware platform.

Keywords: RSA, VHDL, FPGA, modular multiplication, modular exponential.

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Authors: Ahmed El Oualkadi, Abdellah Ait Ouahman

Abstract:

This paper discusses a systematic design of a Σ-Δ fractional-N Phase-Locked Loop based on HDL behavioral modeling. The proposed design consists in describing the mixed behavior of this PLL architecture starting from the specifications of each building block. The HDL models of critical PLL blocks have been described in VHDL-AMS to predict the different specifications of the PLL. The effect of different noise sources has been efficiently introduced to study the PLL system performances. The obtained results are compared with transistor-level simulations to validate the effectiveness of the proposed models for wireless applications in the frequency range around 2.45 GHz.

Keywords: Phase-locked loop, frequency synthesizer, fractional-N PLL, Σ-Δ modulator, HDL models

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Authors: Won-Jun Choi, Seung-Jun Yu, Jung-In Baik, Hyoung-Kyu Song

Abstract:

Cooperative communication scheme can be substituted for multiple-input multiple-output (MIMO) technique when it may not be able to support multiple antennas due to size, cost or hardware limitations. In other words, cooperative communication scheme is an efficient method to achieve spatial diversity without multiple antennas. For satisfaction of rising QoS, we propose a reliable cooperative communication scheme with M-QAM based Dual Carrier Modulation (M-DCM), which can increase diversity gain. Although our proposed scheme is very simple method, it gives us frequency and spatial diversity. Simulation result shows our proposed scheme obtains diversity gain more than the conventional cooperative communication scheme.

Keywords: cooperation, diversity, M-DCM, OFDM.

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Authors: S. Seyedtabaii, E. Seyedtabaii

Abstract:

Rounding of coefficients is a common practice in hardware implementation of digital filters. Where some coefficients are very close to zero or one, as assumed in this paper, this rounding action also leads to some computation reduction. Furthermore, if the discarded coefficient is of high order, a reduced order filter is obtained, otherwise the order does not change but computation is reduced. In this paper, the Least Squares approximation to rounded (or discarded) coefficient FIR filter is investigated. The result also succinctly extended to general type of FIR filters.

Keywords: Digital filter, filter approximation, least squares, model order reduction.

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Authors: Roscoe McLean, Jared Padayachee, Glen Bright

Abstract:

There is currently a gap in the technology covering the rapid establishment of control after a reconfiguration in a Reconfigurable Manufacturing System. This gap involves the detection of the factory floor state and the communication link between the factory floor and the high-level software. In this paper, a thin, hardware-supported Middleware Management System (MMS) is proposed and its design and implementation are discussed. The research found that a cost-effective localization technique can be combined with intelligent software to speed up the ramp-up of a reconfigured system. The MMS makes the process more intelligent, more efficient and less time-consuming, thus supporting the industrial implementation of the RMS paradigm.

Keywords: Intelligent systems, middleware, reconfigurable manufacturing.

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Authors: A. Nassiry, A. Kardan

Abstract:

According to development of communications and web-based technologies in recent years, e-Learning has became very important for everyone and is seen as one of most dynamic teaching methods. Grid computing is a pattern for increasing of computing power and storage capacity of a system and is based on hardware and software resources in a network with common purpose. In this article we study grid architecture and describe its different layers. In this way, we will analyze grid layered architecture. Then we will introduce a new suitable architecture for e-Learning which is based on grid network, and for this reason we call it Grid Learning Architecture. Various sections and layers of suggested architecture will be analyzed; especially grid middleware layer that has key role. This layer is heart of grid learning architecture and, in fact, regardless of this layer, e-Learning based on grid architecture will not be feasible.

Keywords: Distributed learning, Grid Learning, Grid network, SCORM standard.

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Authors: M. Mashayekhi, H. H. Ardakani, A. Omidian

Abstract:

Among various testing methodologies, Built-in Self- Test (BIST) is recognized as a low cost, effective paradigm. Also, full adders are one of the basic building blocks of most arithmetic circuits in all processing units. In this paper, an optimized testable 2- bit full adder as a test building block is proposed. Then, a BIST procedure is introduced to scale up the building block and to generate a self testable n-bit full adders. The target design can achieve 100% fault coverage using insignificant amount of hardware redundancy. Moreover, Overall test time is reduced by utilizing polymorphic gates and also by testing full adder building blocks in parallel.

Keywords: BIST, Full Adder, Polymorphic Gate

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Authors: Chung To Kong, Siu Ming Yiu

Abstract:

Rubik's cube was invented in 1974. Since then, speedcubers all over the world try their best to break the world record again and again. The newest record is 3.47 seconds. There are many factors that affect the timing including turns per second (tps), algorithm, finger trick, and hardware of the cube. In this paper, the lower bound of the cube solving time will be discussed using convex optimization. Extended analysis of the world records will be used to understand how to improve the timing. With the understanding of each part of the solving step, the paper suggests a list of speed improvement technique. Based on the analysis of the world record, there is a high possibility that the 3 seconds mark will be broken soon.

Keywords: Rubik’s cube, convex optimization, speed cubing, CFOP.

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Authors: Hadjira Bentoumi, Pascal Gautron, Kadi Bouatouch

Abstract:

We present a method for fast volume rendering using graphics hardware (GPU). To our knowledge, it is the first implementation on the GPU. Based on the Shear-Warp algorithm, our GPU-based method provides real-time frame rates and outperforms the CPU-based implementation. When the number of slices is not sufficient, we add in-between slices computed by interpolation. This improves then the quality of the rendered images. We have also implemented the ray marching algorithm on the GPU. The results generated by the three algorithms (CPU-based and GPU-based Shear- Warp, GPU-based Ray Marching) for two test models has proved that the ray marching algorithm outperforms the shear-warp methods in terms of speed up and image quality.

Keywords: Volume rendering, graphics processors

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Authors: Zhan Haiyang, Zhang Lei, Ning Juan

Abstract:

This paper presents a configuration software solution in Linux, which is used for the control of space environment simulator. After introducing the structure and basic principle, it is said that the developing of QT software frame and the dynamic data exchanging between PLC and computer. The OPC driver in Linux is also developed. This driver realizes many-to-many communication between hardware devices and SCADA software. Moreover, an algorithm named “Scan PRI” is put forward. This algorithm is much more optimizable and efficient compared with "Scan in sequence" in Windows. This software has been used in practical project. It has a good control effect and can achieve the expected goal.

Keywords: Linux OS, configuration software, OPC server driver, MYSQL database.

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Authors: Aswir Premadi, Mohammad Syuhaimi Ab. Rahman, Mohamad Najib Moh. Saupe, KasmiranJumari

Abstract:

An optical fault monitoring in FTTH-PON using ACS is demonstrated. This device can achieve real-time fault monitoring for protection feeder fiber. In addition, the ACS can distinguish optical fiber fault from the transmission services to other customers in the FTTH-PON. It is essential to use a wavelength different from the triple-play services operating wavelengths for failure detection. ACS is using the operating wavelength 1625 nm for monitoring and failure detection control. Our solution works on a standard local area network (LAN) using a specially designed hardware interfaced with a microcontroller integrated Ethernet.

Keywords: ACS, monitoring tool, FTTH-PON.

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Authors: Doshi N. A., Dhobale S. B., Kakade S. R.

Abstract:

As chip manufacturing technology is suddenly on the threshold of major evaluation, which shrinks chip in size and performance, LFSR (Linear Feedback Shift Register) is implemented in layout level which develops the low power consumption chip, using recent CMOS, sub-micrometer layout tools. Thus LFSR counter can be a new trend setter in cryptography and is also beneficial as compared to GRAY & BINARY counter and variety of other applications. This paper compares 3 architectures in terms of the hardware implementation, CMOS layout and power consumption, using Microwind CMOS layout tool. Thus it provides solution to a low power architecture implementation of LFSR in CMOS VLSI.

Keywords: Chip technology, Layout level, LFSR, Pass transistor

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Authors: A. Inba Rexy, R. Seyezhai

Abstract:

Through the fast growing technologies, design of power factor correction (PFC) circuit is facing several challenges. In this paper, a two-phase interleaved boost converter with ripple steering technique is proposed. Among the various topologies, Interleaved Boost converter (IBC) is considered as superior due to enriched performance, lower ripple content, compact weight and size. A thorough investigation is presented here for the proposed topology. Simulation study for the IBC has been carried out using MATLAB/SIMULINK. Theoretical analysis and hardware prototype has been performed to validate the results.

Keywords: Interleaved Boost Converter (IBC), Power Factor Correction (PFC), Ripple Steering Technique, Ripple, and Simulation.

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Authors: Mahmoud Z. Iskandarani, Nidal F. Shilbayeh

Abstract:

The voltage/current characteristics and the effect of NO2 gas on the electrical conductivity of a PbPc gas sensor array is investigated. The gas sensor is manufactured using vacuum deposition of gold electrodes on sapphire substrate with the leadphathalocyanine vacuum sublimed on the top of the gold electrodes. Two versions of the PbPc gas sensor array are investigated. The tested types differ in the gap sizes between the deposited gold electrodes. The sensors are tested at different temperatures to account for conductivity changes as the molecular adsorption/desorption rate is affected by heat. The obtained results found to be encouraging as the sensors shoed stability and sensitivity towards low concentration of applied NO2 gas.

Keywords: Intelligent System, PbPc, Gas Sensor, Hardware, Software, Neural.

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Authors: Tarandeep Singh, Parvinder S. Sandhu

Abstract:

The Economic factors are leading to the rise of infrastructures provides software and computing facilities as a service, known as cloud services or cloud computing. Cloud services can provide efficiencies for application providers, both by limiting up-front capital expenses, and by reducing the cost of ownership over time. Such services are made available in a data center, using shared commodity hardware for computation and storage. There is a varied set of cloud services available today, including application services (salesforce.com), storage services (Amazon S3), compute services (Google App Engine, Amazon EC2) and data services (Amazon SimpleDB, Microsoft SQL Server Data Services, Google-s Data store). These services represent a variety of reformations of data management architectures, and more are on the horizon.

Keywords: Data Management in Cloud, AWS, EC2, S3, SQS, TQG.

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Authors: G. Ait Abdelmalek, R. Ziani

Abstract:

In this document, we have proposed a robust conceptual strategy, in order to improve the robustness against the manufacturing defects and thus the reliability of logic CMOS circuits. However, in order to enable the use of future CMOS technology nodes this strategy combines various types of design: DFR (Design for Reliability), techniques of tolerance: hardware redundancy TMR (Triple Modular Redundancy) for hard error tolerance, the DFT (Design for Testability. The Results on largest ISCAS and ITC benchmark circuits show that our approach improves considerably the reliability, by reducing the key factors, the area costs and fault tolerance probability.

Keywords: Design for reliability, design for testability, fault tolerance, manufacturing yield.

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Authors: Surafel Demissie, Frank Keenan, Fergal McCaffery

Abstract:

Emerging medical devices are highly relying on embedded software that runs on the specific platform in real time. The development of embedded software is different from ordinary software development due to the hardware-software dependency. MDevSPICE^® has been developed to provide guidance to support such development. To increase the flexibility of this framework agile practices have been introduced. This paper outlines the challenges for embedded medical device software development and the structure of MDevSPICE^® and suggests a suitable combination of agile practices that will help to add flexibility and address corresponding challenges of embedded medical device software development.

Keywords: Agile practices, challenges, embedded software, MDevSPICE®, medical device.

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Authors: Chanchai Supaartagorn

Abstract:

E-retailing is the sale of goods online that takes place over the Internet. The Internet has shrunk the entire World. World eretailing is growing at an exponential rate in the Americas, Europe and Asia. However, e-retailing costs require expensive investment, such as hardware, software, and security systems. Cloud computing technology is internet-based computing for the management and delivery of applications and services. Cloud-based e-retailing application models allow enterprises to lower their costs with their effective implementation of e-retailing activities. In this paper, we describe the concept of cloud computing and present the architecture of cloud computing, combining the features of e-retailing. In addition, we propose a strategy for implementing cloud computing with e-retailing. Finally, we explain the benefits from the architecture.

Keywords: Architecture, cloud computing, e-retailing, internet-based.

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Authors: A. Diaf, H. Aburideh, Z.Tigrine, D. Tassalit, F.Alaoui

Abstract:

The tray/multi-tray distillation process is a topic that has been investigated to great detail over the last decade by many teams such as Jubran et al. [1], Adhikari et al. [2], Mowla et al. [3], Shatat et al. [4] and Fath [5] to name a few. A significant amount of work and effort was spent focusing on modeling and/simulation of specific distillation hardware designs. In this work, we have focused our efforts on investigating and gathering experimental data on several engineering and design variables to quantify their influence on the yield of the multi-tray distillation process. Our goals are to generate experimental performance data to bridge some existing gaps in the design, engineering, optimization and theoretical modeling aspects of the multi-tray distillation process.

Keywords: Distillation, Desalination, Multi-Stage still, Solar Energy

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Authors: Qimin Yang

Abstract:

In this paper, 3X3 routing nodes are proposed to provide speedup and parallel processing capability in Data Vortex network architectures. The new design not only significantly improves network throughput and latency, but also eliminates the need for distributive traffic control mechanism originally embedded among nodes and the need for nodal buffering. The cost effectiveness is studied by a comparison study with the previously proposed 2- input buffered networks, and considerable performance enhancement can be achieved with similar or lower cost of hardware. Unlike previous implementation, the network leaves small probability of contention, therefore, the packet drop rate must be kept low for such implementation to be feasible and attractive, and it can be achieved with proper choice of operation conditions.

Keywords: Data Vortex, Packet Switch, Interconnection network, deflection, Network-on-chip

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Authors: Juan Blas, Alfonso Bahillo, Santiago Mazuelas, David Bullido, Patricia Fernandez, Ruben M. Lorenzo, Evaristo J. Abril

Abstract:

This paper presents a low cost automatic system for sampling the electric field in a limited area. The scanning area is a flat surface parallel to the ground at a selected height. We discuss in detail the hardware, software and all the arrangements involved in the system operation. In order to show the system performance we include a campaign of narrow band measurements with 6017 sample points in the surroundings of a cellular base station. A commercial isotropic antenna with three orthogonal axes was used as sampling device. The results are analyzed in terms of its space average, standard deviation and statistical distribution.

Keywords: measurement device, propagation, spatial sampling.

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Authors: Yu Ren Lin, Yu Hong Li

Abstract:

Vision-based intelligent vehicle applications often require large amounts of memory to handle video streaming and image processing, which in turn increases complexity of hardware and software. This paper presents an FPGA implement of a vision-based blind spot warning system. Using video frames, the information of the blind spot area turns into one-dimensional information. Analysis of the estimated entropy of image allows the detection of an object in time. This idea has been implemented in the XtremeDSP video starter kit. The blind spot warning system uses only 13% of its logic resources and 95k bits block memory, and its frame rate is over 30 frames per sec (fps).

Keywords: blind-spot area, image, FPGA

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Authors: T. Hui Teo, Wee Tiong Tan, Pradeep K. Gopalakrishnan, Victor K. H. Phay, Ma Su M. M. Shwe

Abstract:

A healthcare monitoring system is presented in this paper. This system is based on ultra-low power sensor nodes and a personal server, which is based on hardware and software extensions to a Personal Digital Assistant (PDA)/Smartphone. The sensor node collects data from the body of a patient and sends it to the personal server where the data is processed, displayed and made ready to be sent to a healthcare network, if necessary. The personal server consists of a compact low power receiver module and equipped with a Smartphone software. The receiver module takes less than 30 × 30 mm board size and consumes approximately 25 mA in active mode.

Keywords: healthcare monitoring, sensor node, personal server, wireless.

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Authors: Yu Ren Lin, Yi Feng Su

Abstract:

Using vision based solution in intelligent vehicle application often needs large memory to handle video stream and image process which increase complexity of hardware and software. In this paper, we present a FPGA implement of a vision based lane departure warning system. By taking frame of videos, the line gradient of line is estimated and the lane marks are found. By analysis the position of lane mark, departure of vehicle will be detected in time. This idea has been implemented in Xilinx Spartan6 FPGA. The lane departure warning system used 39% logic resources and no memory of the device. The average availability is 92.5%. The frame rate is more than 30 frames per second (fps).

Keywords: Lane departure warning system, image, FPGA.

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Authors: T. Taufik, R. Prasetyo, D. Dolan, D. Garinto

Abstract:

Today-s Voltage Regulator Modules (VRMs) face increasing design challenges as the number of transistors in microprocessors increases per Moore-s Law. These challenges have recently become even more demanding as microprocessors operate at sub voltage range at significantly high current. This paper presents a new multiphase topology with cell configuration for improved performance in low voltage and high current applications. A lab scale hardware prototype of the new topology was design and constructed. Laboratory tests were performed on the proposed converter and compared with a commercially available VRM. Results from the proposed topology exhibit improved performance compared to the commercially available counterpart.

Keywords: Voltage Regulator Modules, dc-dc converters, powerelectronics.

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Authors: S. Burgalat, L. Teilhac, A. Brand, E. Chastel, M. Jumeline

Abstract:

The paper presents actual benefits and drawbacks of a multidirectional autonomous hovercraft conceived with limited resources and designed for indoor exploration. Recent developments in the field have led to the apparition of very powerful automotive systems capable of very high calculation and exploration in complex unknown environments. They usually propose very complex algorithms, high precision/cost sensors and sometimes have heavy calculation consumption with complex data fusion. These systems are usually powerful but have a certain price, and the benefits may not be worth the cost, especially considering their hardware limitations and their power consumption. The present approach is to build a compromise between cost, power consumption and results preciseness.

Keywords: Hovercraft, Indoor Exploration, Autonomous, Multidirectional, Wireless Control.

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Authors: Seung-Jun Yu, Yeong-Seop Ahn, Young-Min Ko, Hyoung-Kyu Song

Abstract:

In order to achieve high data rate and increase the spectral efficiency, multiple input multiple output (MIMO) system has been proposed. However, multiple antennas are limited by size and cost. Therefore, recently developed cooperative diversity scheme, which profits the transmit diversity only with the existing hardware by constituting a virtual antenna array, can be a solution. However, most of the introduced cooperative techniques have a common fault of decreased transmission rate because the destination should receive the decodable compositions of symbols from the source and the relay. In this paper, we propose a cooperative cyclic delay diversity (CDD) scheme that use hierarchical modulation. This scheme is free from the rate loss and allows seamless cooperative communication.

Keywords: MIMO, Cooperative communication, CDD, Hierarchical modulation.

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Authors: Amir Ngah, Masita Abdul Jalil, Zailani Abdullah

Abstract:

The aim of software maintenance is to maintain the software system in accordance with advancement in software and hardware technology. One of the early works on software maintenance is to extract information at higher level of abstraction. In this paper, we present the process of how to design an information extraction tool for software maintenance. The tool can extract the basic information from old programs such as about variables, based classes, derived classes, objects of classes, and functions. The tool have two main parts; the lexical analyzer module that can read the input file character by character, and the searching module which users can get the basic information from the existing programs. We implemented this tool for a patterned sub-C++ language as an input file.

Keywords: Extraction tool, software maintenance, reverse engineering, C++.

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