Search results for: hardware architecture

Authors: Hassan Haghighi, Seyedeh Zahra Hosseini, Seyedeh Elahe Jalambadani

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ERP systems are often supposed to be implemented and deployed in multi-national companies. On the other hand, an ERP developer may plan to market and sale its product in various countries. Therefore, an EPR system should have the ability to communicate with its users, who usually have different languages and cultures, in a suitable way. EPR support of Multilanguage capability is a solution to achieve this objective. In this paper, an agent oriented architecture including several independent but cooperative agents has been suggested that helps to implement Multilanguage EPR systems.

Keywords: enterprise resource planning, Multilanguage, software architecture, agent oriented architecture, intelligence, learning, translation.

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Authors: Yaser Rezapour, Armin Jabbarieh, Fatemeh Behfar, Ahadollah Azami, Aidin Shamsalghorayi

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Social ideology, cultural values and principles shaping environment are inferred by environment and structural characteristics of construction site. In other words, this inference manifestation also indicates ideology and culture of its foundation and also applies its principles and values and somehow plays an important role in Cultural Revolution. All human behaviors and artifacts are affected and being influenced by culture. Culture is not abstract concept, it is a spiritual domain that an individual and society grow and develop in it. Social behaviors are affected by environmental comprehension, so the architecture work influences on its audience and it is the environment that fosters social behaviors. Indeed, sustainable architecture should be considered as background of culture for establishing optimal sustainable culture. Since unidentified architecture roots in cultural non identity and abnormalities, so the society possesses identity characteristics and life and as a consequence, the society and architecture are changed by transformation of life style. This article aims to investigate the interaction of architecture, society, environment and sustainable architecture formation in its cultural basis and analyzes the results approaching behavior and sustainable culture in recent era.

Keywords: Culture, Sustainable Architecture, Environment, Development

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Authors: Mohib ur Rehman, Imran Ihsan, Mobin Uddin Ahmed, Nadeem Iftikhar, Muhammad Abdul Qadir

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Multimedia, as it stands now is perhaps the most diverse and rich culture around the globe. One of the major needs of Multimedia is to have a single system that enables people to efficiently search through their multimedia catalogues. Many Domain Specific Systems and architectures have been proposed but up till now no generic and complete architecture is proposed. In this paper, we have suggested a generic architecture for Multimedia Database. The main strengths of our architecture besides being generic are Semantic Libraries to reduce semantic gap, levels of feature extraction for more specific and detailed feature extraction according to classes defined by prior level, and merging of two types of queries i.e. text and QBE (Query by Example) for more accurate yet detailed results.

Keywords: Multimedia Database Architecture, Semantics, Feature Extraction, Ontology.

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Authors: Hassan Haghighi, Sajad Ghorbani, Maryam Mohebati, Mohammad Mahdi Javanmard

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One of the most important aspects expected from ERP systems is to integrate various operations existing in administrative, financial, commercial, human resources, and production departments of the consumer organization. Also, it is often needed to integrate the new ERP system with the organization legacy systems when implementing the ERP package in the organization. Without relying on an appropriate software architecture to realize the required integration, ERP implementation processes become error prone and time consuming; in some cases, the ERP implementation may even encounters serious risks. In this paper, we propose a new architecture that is based on the agent oriented vision and supplies the integration expected from ERP systems using several independent but cooperator agents. Besides integration which is the main issue of this paper, the presented architecture will address some aspects of intelligence and learning capabilities existing in ERP systems

Keywords: enterprise resource planning, software architecture, agent oriented architecture, integration, intelligence, learning.

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Authors: E. Tomur, R. Deregozu, T. Genc

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In this study, we propose a network architecture for providing secure access to information resources of enterprise network from remote locations in a wireless fashion. Our proposed architecture offers a very promising solution for organizations which are in need of a secure, flexible and cost-effective remote access methodology. Security of the proposed architecture is based on Virtual Private Network technology and a special role based access control mechanism with location and time constraints. The flexibility mainly comes from the use of Internet as the communication medium and cost-effectiveness is due to the possibility of in-house implementation of the proposed architecture.

Keywords: Remote access, wireless networks, security, virtualprivate networks, RBAC.

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Authors: Tom Dowling, Adam Duffy

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This paper presents an architecture to assist in the development of tools to perform experimental analysis. Existing implementations of tools based on this architecture are also described in this paper. These tools are applied to the real world problem of fault attack emulation and detection in cryptographic algorithms.

Keywords: Software Architectures and Design, Software Componentsand Reuse, Engineering Secure Software.

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Authors: Saeideh Soltanmohammadlou, Pilar M Guerrieri, Amir Kianfar, Sara Sadeghian, Yasaman Nafezi, Emily Irvin

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Architecture is rooted in the experiences of the residents in a place. Its foundations are based on needs and circumstances of each territory in terms of climate, available materials, economics and governmental policies, and cultural ideals and ideas of the people that live there. The architectural history of Iran echoes these architectural origins and has revealed certain trends reflecting this territory and culture. However, in recent years, new architectural patterns are developing that diverge from what has previously been considered classic forms of Iranian architecture. This article investigates architectural elements that make up the architecture created by religious minorities after the Safavid dynasty (one of the most significant ruling dynasties of Iran (from 1501 to 1736) in Iranian cities: Isfahan, Tabriz, Kerman, and Uremia. Similarities and differences are revealed between the architecture that composes neighborhoods of religious minorities in Iran and common national architectural trends in each era after this dynasty. This dynasty is specific as a point of reference in this article because Islam was identified as the state religion of Iran during this era. This decision changed the course of architecture in the country to incorporate religious motifs and meanings. The study associated with this article was conducted as a survey that sought to find links between architecture of religious minorities with Iranian national architecture. Interestingly, a merging of architectural forms and trends occur as immigrants interact with Iranian Islamic meanings. These observations are significant within the context of modern architecture around the world and within Western discourse because what are considered religious minorities in Iran are the dominant religions in Western nations. This makes Iran’s architecture particularly unique as it creates a kind of inverse relationship, than that of Western nations, to the ways in which religion influences architectural history.

Keywords: Architecture, ethnic architecture, national architecture, religion architecture.

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Authors: Christian Mayr, Matthias Ehrlich, Stephan Henker, Karsten Wendt, René Schüffny

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Traditionally, VLSI implementations of spiking neural nets have featured large neuron counts for fixed computations or small exploratory, configurable nets. This paper presents the system architecture of a large configurable neural net system employing a dedicated mapping algorithm for projecting the targeted biology-analog nets and dynamics onto the hardware with its attendant constraints.

Keywords: Large scale VLSI neural net, topology mapping, complex pulse communication.

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Authors: Rekha V. Dundur , M.V.Latte, S.Y. Kulkarni, M.K.Venkatesha

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The advent of multi-million gate Field Programmable Gate Arrays (FPGAs) with hardware support for multiplication opens an opportunity to recreate a significant portion of the front end of a human cochlea using this technology. In this paper we describe the implementation of the cochlear filter and show that it is entirely suited to a single device XC3S500 FPGA implementation .The filter gave a good fit to real time data with efficiency of hardware usage.

Keywords: Cochlea, FPGA, IIR (Infinite Impulse Response), Multiplier.

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Authors: R. Damaševičius

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System-level design based on high-level abstractions is becoming increasingly important in hardware and embedded system design. This paper analyzes meta-design techniques oriented at developing meta-programs and meta-models for well-understood domains. Meta-design techniques include meta-programming and meta-modeling. At the programming level of design process, metadesign means developing generic components that are usable in a wider context of application than original domain components. At the modeling level, meta-design means developing design patterns that describe general solutions to the common recurring design problems, and meta-models that describe the relationship between different types of design models and abstractions. The paper describes and evaluates the implementation of meta-design in hardware design domain using object-oriented and meta-programming techniques. The presented ideas are illustrated with a case study.

Keywords: Design patterns, meta-design, meta-modeling, metaprogramming.

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Authors: Kar Foo Chong, Andreas Lee Astuti, Pradeep K. Gopalakrishnan, T. Hui Teo

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This paper describes design of a digital feedback loop for a low switching frequency dc-dc switching converters. Low switching frequencies were selected in this design. A look up table for the digital PID (proportional integrator differentiator) compensator was implemented using Altera Stratix II with built-in ADC (analog-to-digital converter) to achieve this hardware realization. Design guidelines are given for the PID compensator, high frequency DPWM (digital pulse width modulator) and moving average filter.

Keywords: dc-dc converter, FPGA, PID, power management, .

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Authors: Iyad F. Jafar, Sandra J. Alrawashdeh, Ban K. Alhamayel

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High level synthesis (HLS) is a process which generates register-transfer level design for digital systems from behavioral description. There are many HLS algorithms and commercial tools. However, most of these algorithms consider a behavioral description for the system when a single token is presented to the system. This approach does not exploit extra hardware efficiently, especially in the design of digital filters where common operations may exist between successive tokens. In this paper, we modify the behavioral description to process multiple tokens in parallel. However, this approach is unlike the full processing that requires full hardware replication. It exploits the presence of common operations between successive tokens. The performance of the proposed approach is better than sequential processing and approaches that of full parallel processing as the hardware resources are increased.

Keywords: Digital filters, High level synthesis, Sub-token forwarding

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Authors: S. Jalaja, A. M. Vijaya Prakash

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Recursive combination of an algorithm based on Karatsuba multiplication is exploited to design a generalized transpose and parallel Finite Impulse Response (FIR) Filter. Mid-range Karatsuba multiplication and Carry Save adder based on Karatsuba multiplication reduce time complexity for higher order multiplication implemented up to n-bit. As a result, we design modified N-tap Transpose and Parallel Symmetric FIR Filter Structure using Karatsuba algorithm. The mathematical formulation of the FFA Filter is derived. The proposed architecture involves significantly less area delay product (APD) then the existing block implementation. By adopting retiming technique, hardware cost is reduced further. The filter architecture is designed by using 90 nm technology library and is implemented by using cadence EDA Tool. The synthesized result shows better performance for different word length and block size. The design achieves switching activity reduction and low power consumption by applying with and without retiming for different combination of the circuit. The proposed structure achieves more than a half of the power reduction by adopting with and without retiming techniques compared to the earlier design structure. As a proof of the concept for block size 16 and filter length 64 for CKA method, it achieves a 51% as well as 70% less power by applying retiming technique, and for CSA method it achieves a 57% as well as 77% less power by applying retiming technique compared to the previously proposed design.

Keywords: Carry save adder Karatsuba multiplication, mid-range Karatsuba multiplication, modified FFA, transposed filter, retiming.

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Authors: Cyrille Lambert, Tatiana Kalganova, Emanuele Stomeo

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Since 1992, year where Hugo de Garis has published the first paper on Evolvable Hardware (EHW), a period of intense creativity has followed. It has been actively researched, developed and applied to various problems. Different approaches have been proposed that created three main classifications: extrinsic, mixtrinsic and intrinsic EHW. Each of these solutions has a real interest. Nevertheless, although the extrinsic evolution generates some excellent results, the intrinsic systems are not so advanced. This paper suggests 3 possible solutions to implement the run-time configuration intrinsic EHW system: FPGA-based Run-Time Configuration system, JBits-based Run-Time Configuration system and Multi-board functional-level Run-Time Configuration system. The main characteristic of the proposed architectures is that they are implemented on Field Programmable Gate Array. A comparison of proposed solutions demonstrates that multi-board functional-level run-time configuration is superior in terms of scalability, flexibility and the implementation easiness.

Keywords: Evolvable hardware, evolutionary computation, FPGA systems.

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Authors: Konstantin Movsovic, Emanuele Stomeo, Tatiana Kalganova

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The evolutionary design of electronic circuits, or evolvable hardware, is a discipline that allows the user to automatically obtain the desired circuit design. The circuit configuration is under the control of evolutionary algorithms. Several researchers have used evolvable hardware to design electrical circuits. Every time that one particular algorithm is selected to carry out the evolution, it is necessary that all its parameters, such as mutation rate, population size, selection mechanisms etc. are tuned in order to achieve the best results during the evolution process. This paper investigates the abilities of evolution strategy to evolve digital logic circuits based on programmable logic array structures when different mutation rates are used. Several mutation rates (fixed and variable) are analyzed and compared with each other to outline the most appropriate choice to be used during the evolution of combinational logic circuits. The experimental results outlined in this paper are important as they could be used by every researcher who might need to use the evolutionary algorithm to design digital logic circuits.

Keywords: Evolvable hardware, evolutionary algorithm, digitallogic circuit, mutation rate.

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Authors: Balasundaram Prasaant, Ploix Stephane, Delinchant Benoit, Muresan Cristian

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Hardware in Loop (HIL) testing is done to test and validate a particular product especially in building technology. When it comes to building technology, it is more important to test the products for their efficiency. The test rig in the HIL simulator may contribute to some uncertainties on measured efficiency. The uncertainties include physical uncertainties and scenario-based uncertainties. In this paper, a simple uncertainty analysis framework for an HIL setup is shown considering only the physical uncertainties. The entire modeling of the HIL setup is done in Dymola. The uncertain sources are considered based on available knowledge of the components and also on expert knowledge. For the propagation of uncertainty, Monte Carlo Simulation is used since it is the most reliable and easy to use. In this article it is shown how an HIL setup can be modeled and how uncertainty propagation can be performed on it. Such an approach is not common in building energy analysis.

Keywords: Energy in Buildings, Hardware in Loop, Modelica (Dymola), Monte Carlo Simulation, Uncertainty Propagation.

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Authors: Irina Pyrlina

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Author presents the results of a study conducted to identify criteria of efficient information system (IS) with serviceoriented architecture (SOA) realization and proposes a ranking method to evaluate SOA information systems using a set of architecture quality criteria before the systems are implemented. The method is used to compare 7 SOA projects and ranking result for SOA efficiency of the projects is provided. The choice of SOA realization project depends on following criteria categories: IS internal work and organization, SOA policies, guidelines and change management, processes and business services readiness, risk management and mitigation. The last criteria category was analyzed on the basis of projects statistics.

Keywords: multiple criteria threshold algorithm, serviceoriented architecture, SOA operational risks, efficiency criteria for IS architecture, projects ranking.

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Authors: Sung Kyu Kim, Yong Soo Kim

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Safety instrumented systems (SISs) are becoming increasingly complex and the proportion of programmable electronic parts is growing. The IEC 61508 global standard was established to ensure the functional safety of SISs, but it was expressed in highly macroscopic terms. This study introduces an evaluation process for hardware safety integrity levels through failure modes, effects, and diagnostic analysis (FMEDA).FMEDA is widely used to evaluate safety levels, and it provides the information on failure rates and failure mode distributions necessary to calculate a diagnostic coverage factor for a given component. In our evaluation process, the components of the SIS subsystem are first defined in terms of failure modes and effects. Then, the failure rate and failure mechanism distribution are assigned to each component. The safety mode and detectability of each failure mode are determined for each component. Finally, the hardware safety integrity level is evaluated based on the calculated results.

Keywords: Safety instrumented system; Safety integrity level; Failure modes, effects, and diagnostic analysis; IEC 61508.

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Authors: K. Akherfi, H. Harroud

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Cloud computing (CC) and mobile cloud computing (MCC) have advanced rapidly the last few years. Today, MCC undergoes fast improvement and progress in terms of hardware (memory, embedded sensors, power consumption, touch screen, etc.) software (more and more sophisticated mobile applications) and transmission (higher data transmission rates achieved with different technologies such as 3Gs). This paper presents a review on the concept of CC and MCC. Then, it discusses what has been done regarding middleware in cloud and mobile cloud computing. Later, it shows the architecture of our proposed middleware along with its functionalities which will be provided to mobile clients in order to overcome the well known problems (such as low battery power, slow CPU speed and little memory…).

Keywords: Context-aware, cloud computing, middleware, mobile cloud.

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Authors: May Phyo Thwal, Khin Htay Kyi, Kyaw Swar Soe

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According to the density of the chips, designers are trying to put so any facilities of computational and storage on single chips. Along with the complexity of computational and storage circuits, the designing, testing and debugging become more and more complex and expensive. So, hardware design will be built by using very high speed hardware description language, which is more efficient and cost effective. This paper will focus on the implementation of 32-bit ALU design based on Verilog hardware description language. Adder and subtracter operate correctly on both unsigned and positive numbers. In ALU, addition takes most of the time if it uses the ripple-carry adder. The general strategy for designing fast adders is to reduce the time required to form carry signals. Adders that use this principle are called carry look- ahead adder. The carry look-ahead adder is to be designed with combination of 4-bit adders. The syntax of Verilog HDL is similar to the C programming language. This paper proposes a unified approach to ALU design in which both simulation and formal verification can co-exist.

Keywords: Addition, arithmetic logic unit, carry look-ahead adder, Verilog HDL.

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Authors: Masafumi Kondo, Yoichiro Sato, Kazuyuki Tashiro, Tomoyuki Yokogawa, Michiyoshi Hayase

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Recently, most digital systems are designed as GALS (Globally Asynchronous Locally Synchronous) systems. Several architectures have been proposed as bus architectures for a GALS system : shared bus, segmented bus, ring bus, and so on. In this study, we propose a ring segmented bus architecture which is a combination of segmented bus and ring bus architecture with the aim of throughput enhancement. In a segmented bus architecture, segments are connected in series. By connecting the segments at the end of the bus and constructing the ring bus, it becomes possible to allocate a channel of the bus bidirectionally. The bus channel is allocated to the shortest path between segments. We consider a metastable operation caused by asynchronous communication between segments and a burst transfer between segments. According to the result of simulation, it is shown that the GALS system designed by the proposed method has the desired operations.

Keywords: GALS systems bus architecture, segmented bus, ring bus.

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Authors: N. Muthukumaran, R. Ravi

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The Simulation based VLSI Implementation of FELICS (Fast Efficient Lossless Image Compression System) Algorithm is proposed to provide the lossless image compression and is implemented in simulation oriented VLSI (Very Large Scale Integrated). To analysis the performance of Lossless image compression and to reduce the image without losing image quality and then implemented in VLSI based FELICS algorithm. In FELICS algorithm, which consists of simplified adjusted binary code for Image compression and these compression image is converted in pixel and then implemented in VLSI domain. This parameter is used to achieve high processing speed and minimize the area and power. The simplified adjusted binary code reduces the number of arithmetic operation and achieved high processing speed. The color difference preprocessing is also proposed to improve coding efficiency with simple arithmetic operation. Although VLSI based FELICS Algorithm provides effective solution for hardware architecture design for regular pipelining data flow parallelism with four stages. With two level parallelisms, consecutive pixels can be classified into even and odd samples and the individual hardware engine is dedicated for each one. This method can be further enhanced by multilevel parallelisms.

Keywords: Image compression, Pixel, Compression Ratio, Adjusted Binary code, Golumb Rice code, High Definition display, VLSI Implementation.

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Authors: Mahshid Kakouei, Mina Kakouei, Kumaran Suberamanian, Sabzali Musa Kahn, Afshin Jahangirzadeh, Shatirah Akib

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Human always tried to create a suitable situation for their life according to environmental conditions. In fact, geography has an important role in the shape of our living area. Iran also as a four-season country has different climate type: hot and humid, hot and dry, mid and humid, and cold; therefore, we can find different architecture styles in Iran. Gilan-s traditional architecture is a suitable sample of sustainable construction in Iran. Because the main factors of every dwelling are the climatic, social, economic and cultural effects which demonstrate the interaction between environment and people settlement. This paper was determined the interaction between environmental factors and the rural dwellings in the Gilan province. Also, traditional village (city) of Masouleh as a rare sample of rural and sustainable architecture was introduced.

Keywords: Masouleh, Traditional architecture, vernacular materials, sustainable architecture.

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Authors: Youngjae Jin, Daeshik Kim

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This paper describes a cycle accurate simulation results of weight values learned by an auto-encoder behavior model in terms of pre-route simulation. Given the results we visualized the first layer representations with natural images. Many common deep learning threads have focused on learning high-level abstraction of unlabeled raw data by unsupervised feature learning. However, in the process of handling such a huge amount of data, the learning method’s computation complexity and time limited advanced research. These limitations came from the fact these algorithms were computed by using only single core CPUs. For this reason, parallel-based hardware, FPGAs, was seen as a possible solution to overcome these limitations. We adopted and simulated the ready-made auto-encoder to design a behavior model in VerilogHDL before designing hardware. With the auto-encoder behavior model pre-route simulation, we obtained the cycle accurate results of the parameter of each hidden layer by using MODELSIM. The cycle accurate results are very important factor in designing a parallel-based digital hardware. Finally this paper shows an appropriate operation of behavior model based pre-route simulation. Moreover, we visualized learning latent representations of the first hidden layer with Kyoto natural image dataset.

Keywords: Auto-encoder, Behavior model simulation, Digital hardware design, Pre-route simulation, Unsupervised feature learning.

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Authors: Noman Khan, B. S. Chowdhry, A.Q.K Rajput

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Integrated fiber-wireless (FiWi) access networks are a viable solution that can deliver the high profile quadruple play services. Passive optical networks (PON) networks integrated with wireless access networks provide ubiquitous characteristics for high bandwidth applications. Operation of PON improves by employing a variety of multiplexing techniques. One of it is time division/wavelength division multiplexed (TDM/WDM) architecture that improves the performance of optical-wireless access networks. This paper proposes a novel feedback-based TDM/WDM-PON architecture and introduces a model of integrated PON-FiWi networks. Feedback-based link architecture is an efficient solution to improves the performance of optical-line-terminal (OLT) and interlink optical-network-units (ONUs) communication. Furthermore, the feedback-based WDM/TDM-PON architecture is compared with existing architectures in terms of capacity of network throughput.

Keywords: Fiber-wireless (FiWi), Passive Optical Network (PON), TDM/WDM architecture

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Authors: Rehab Abdullah Shendi

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The use of customised soft-core processors in which instructions can be integrated into a system in application hardware is increasing in the Field Programmable Gate Array (FPGA) field. Specifically, the partial run-time reconfiguration of FPGAs in specialised processors for a particular domain can be very beneficial. In this report, the design and implementation for the customisation of a soft-core MIPS processor using an FPGA and partial reconfiguration (PR) of FPGA technology will be addressed to achieve efficient resource use. This can be achieved using a PR design flow that helps the design fit into a smaller device. Moreover, the impact of static power consumption could be reduced due to runtime reconfiguration. This will be done by configurable custom instructions implemented in the hardware as an extension on the MIPS CPU. The aim of this project is to investigate the PR of FPGAs for run-time adaptations of the instruction set of a soft-core CPU, including the integration of custom instructions and the exploration of the potential to use the MultiBoot feature available in Xilinx FPGAs to carry out the PR process. The system will be evaluated and tested on a Nexus 3 development board featuring a Xilinx Spartran-6 FPGA. The system will be able to load reconfigurable custom instructions dynamically into user programs with the help of the trap handler when the custom instruction is called by the MIPS CPU. The results of this experiment demonstrate that custom instructions in hardware can speed up a certain function and many instructions can be saved when compared to a software implementation of the same function. Implementing custom instructions in hardware is perfectly possible and worth exploring.

Keywords: Customisation, FPGA, MIPS, partial reconfiguration.

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Authors: Amit Kumar, Himanshu Singal, Arnav Bhavsar

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In this modern era of automation, most of the academic exams and competitive exams are Multiple Choice Questions (MCQ). The responses of these MCQ based exams are recorded in the Optical Mark Reader (OMR) sheet. Evaluation of the OMR sheet requires separate specialized machines for scanning and marking. The sheets used by these machines are special and costs more than a normal sheet. Available process is non-economical and dependent on paper thickness, scanning quality, paper orientation, special hardware and customized software. This study tries to tackle the problem of evaluating the OMR sheet without any special hardware and making the whole process economical. We propose an image processing based algorithm which can be used to read and evaluate the scanned OMR sheets with no special hardware required. It will eliminate the use of special OMR sheet. Responses recorded in normal sheet is enough for evaluation. The proposed system takes care of color, brightness, rotation, little imperfections in the OMR sheet images.

Keywords: OMR, image processing, hough circle transform, interpolation, detection, Binary Thresholding.

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Authors: Shankar Kambhampaty, Harish Rohan Kambhampaty

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Data in IT systems in enterprises have been growing at phenomenal pace. This has provided opportunities to run analytics to gather intelligence on key business parameters that enable them to provide better products and services to customers. While there are several Artificial Intelligence/Machine Learning (AI/ML) and Business Intelligence (BI) tools and technologies available in marketplace to run analytics, there is a need for an integrated view when developing intelligent solutions in enterprises. This paper progressively elaborates a reference model for enterprise solutions, builds an integrated view of data, information and intelligence components and presents a reference architecture for intelligent enterprise solutions. Finally, it applies the reference architecture to an insurance organization. The reference architecture is the outcome of experience and insights gathered from developing intelligent solutions for several organizations.

Keywords: Architecture, model, intelligence, artificial intelligence, business intelligence, AI, BI, ML, analytics, enterprise.

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Authors: Yi-Haur Shiau, Sun-In Lin, Shi-Wei Lo, Hsiu-Mei Chou, Yi-Hsuan Chen

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This paper proposes a novel multi-format stream grid architecture for real-time image monitoring system. The system, based on a three-tier architecture, includes stream receiving unit, stream processor unit, and presentation unit. It is a distributed computing and a loose coupling architecture. The benefit is the amount of required servers can be adjusted depending on the loading of the image monitoring system. The stream receive unit supports multi capture source devices and multi-format stream compress encoder. Stream processor unit includes three modules; they are stream clipping module, image processing module and image management module. Presentation unit can display image data on several different platforms. We verified the proposed grid architecture with an actual test of image monitoring. We used a fast image matching method with the adjustable parameters for different monitoring situations. Background subtraction method is also implemented in the system. Experimental results showed that the proposed architecture is robust, adaptive, and powerful in the image monitoring system.

Keywords: Motion detection, grid architecture, image monitoring system, and background subtraction.

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Authors: D. Moussazadeh, A. Aytug

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The architecture of the museum is the most exciting space for an architecture to discover and investigate. Undoubtedly, those museums that have been largely supported by people have come to be cultural memorabilia, moreover holding competitions in museums, producing new publications for theoretical or intellectual debates, and new designs lead the museums to be the most effective and attractive place for work and study. The importance of museums as centers of knowledge, science and art has increased over the last century. Museums have moved from being a place specific to the first-class of the community, to a place used by the whole community widely. By considering these reasons, the value and importance of museums in today's society is imperative. Finding common features for museum architecture in the decades after 1990s has become more difficult than previous decades. The purpose of this article is to examine the effect of museums and their position in society on architectural design of museums from the beginning to the present. In other words, this research aims to investigate the history of museums, their roles, duties, uses, their relationship with users and their position and, consequently, the impact of all these factors on the design of museum architecture. Finally, the main objective of this article is to find the position of museums in the community and their architectural form in the present century.

Keywords: Museum, form, architecture.

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