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A Ring Segmented Bus Architecture for Globally Asynchronous Locally Synchronous System

Authors: Masafumi Kondo, Yoichiro Sato, Kazuyuki Tashiro, Tomoyuki Yokogawa, Michiyoshi Hayase

Abstract:

Recently, most digital systems are designed as GALS (Globally Asynchronous Locally Synchronous) systems. Several architectures have been proposed as bus architectures for a GALS system : shared bus, segmented bus, ring bus, and so on. In this study, we propose a ring segmented bus architecture which is a combination of segmented bus and ring bus architecture with the aim of throughput enhancement. In a segmented bus architecture, segments are connected in series. By connecting the segments at the end of the bus and constructing the ring bus, it becomes possible to allocate a channel of the bus bidirectionally. The bus channel is allocated to the shortest path between segments. We consider a metastable operation caused by asynchronous communication between segments and a burst transfer between segments. According to the result of simulation, it is shown that the GALS system designed by the proposed method has the desired operations.

Keywords: GALS systems bus architecture, segmented bus, ring bus.

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1085353

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References:


[1] T. Nanya, "A perspective on asynchronous microprocessor," Journal of Information Processing Society of Japan, vol. 39, no. 3, pp. 181-186, 1998, (in Japanese).
[2] I. Sutherland and S. Fairbanks, "Gasp: a minimal fifo control," Seventh International Symposium on Asynchronous Circuits and Systems (ASYNC 2001), pp. 46-53, 2001.
[3] T. Villiger, H. Kaslin, F. K. Gurkaynak, S. Oetiker, and W. Fichtner, "Self-timed ring for globally-asynchronous locally-synchronous systems," in ASYNC '03: Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems. Washington, DC, USA: IEEE Computer Society, 2003, p. 141.
[4] J. Plosila, T. Seceleanu, and P. Liljeberg, "Implementation of a self-timed segmented bus," IEEE Design and Test of Computers, vol. 20, no. 6, pp. 44-50, 2003.
[5] M. Stein, "Crossing the abyss: asynchronous signals in a synchronous world," EDN Magazine, pp. 59-69, 7 2003.
[6] Y. Yamasoto, Y. Sato, H. Kagotani, and T. Okamoto, "A formula for performance evaluation of synchronizers constructed with cascaded cmos d flip-flops," Transactions of the Institute of Electronics, Information and Communication Engineers, vol. J84, no. D-1, pp. 1484-1492, 1999, (in Japanese).