Search results for: Very High speedIntegrated Circuit (VHSIC) Hardware Description Language(VHDL)

Authors: Sungsik Jo, Hyeonwoo Kim, Iksu Choi, Hunmo Kim

Abstract:

In the SHP, LVDT sensor is for detecting the length changes of the EHA output, and the thrust of the EHA is controlled by the pressure sensor. Sensor is possible to cause hardware fault by internal problem or external disturbance. The EHA of SHP is able to be uncontrollable due to control by feedback from uncertain information, on this paper; the sliding mode observer algorithm estimates the original sensor output information in permanent sensor fault. The proposed algorithm shows performance to recovery fault of disconnection and short circuit basically, also the algorithm detect various of sensor fault mode.

Keywords: Smart Hybrid Powerpack (SHP), Electro Hydraulic Actuator (EHA), Permanent Sensor fault tolerance, Sliding mode observer (SMO), Graphic User Interface (GUI).

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Authors: Sikder Mohammad Faruk, Mir Mofajjal Hossain, Muhibul Haque Bhuyan

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In this investigative research paper, we have presented the simulation results of a three-phase rectifier circuit to improve the input side current using the passive filters, such as capacitors and inductors at the output and input terminals of the rectifier circuit respectively. All simulation works were performed in a personal computer using the PSPICE simulator software, which is a virtual circuit design and simulation software package. The output voltages and currents were measured across a resistive load of 1 k. We observed that the output voltage levels, input current wave shapes, harmonic contents through the harmonic spectrum, and total harmonic distortion improved due to the use of such filters.

Keywords: input current wave, three-phase rectifier, passive filter, PSPICE Simulation

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Authors: A. AlKalbany, H. Al hassan, M. Saeb

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The “PYRAMIDS" Block Cipher is a symmetric encryption algorithm of a 64, 128, 256-bit length, that accepts a variable key length of 128, 192, 256 bits. The algorithm is an iterated cipher consisting of repeated applications of a simple round transformation with different operations and different sequence in each round. The algorithm was previously software implemented in Cµ code. In this paper, a hardware implementation of the algorithm, using Field Programmable Gate Arrays (FPGA), is presented. In this work, we discuss the algorithm, the implemented micro-architecture, and the simulation and implementation results. Moreover, we present a detailed comparison with other implemented standard algorithms. In addition, we include the floor plan as well as the circuit diagrams of the various micro-architecture modules.

Keywords: FPGA, VHDL, micro-architecture, encryption, cryptography, algorithm, data communication security.

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Authors: Man Li, Wanting Zhou, Lei Li

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Communication stability is the primary concern of communication satellites. Communication satellites are easily affected by particle radiation to generate single event effects (SEE), which leads to soft errors (SE) of combinational logic circuit. The existing research on soft error rates (SER) of combined logic circuit is mostly based on the assumption that the logic gates being bombarded have the same pulse width. However, in the actual radiation environment, the pulse widths of the logic gates being bombarded are different due to different linear energy transfers (LET). In order to improve the accuracy of SER evaluation model, this paper proposes a soft error rates evaluation method based on LET. In this paper, we analyze the influence of LET on the pulse width of combinational logic and establish the pulse width model based on LET. Based on this model, the error rate of test circuit ISCAS’85 is calculated. Experimental results show that this model can be used for SER evaluation.

Keywords: Communication satellite, pulse width, soft error rates, linear energy transfer, LET.

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Authors: D. Krishnaveni, M. Geetha Priya

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Applications of reversible logic gates in the design of complex integrated circuits provide power optimization.  This technique finds a great use in low power CMOS design, optical computing, quantum computing and nanotechnology. This paper proposes a reversible signed division circuit that can divide an n-bit signed dividend with an n-bit signed divisor using non-restoration division logic. The proposed design adequately addresses the ‘delay’ there by improving the efficiency of the circuit. An attempt is made to design a reversible signed division circuit. This paper provides a threshold to build more complex arithmetic systems using reversible logic, thus increasing the performance of computing systems.

Keywords: Low power CMOS, quantum computing, reversible logic gates, shift register, signed division.

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Authors: V.Sekar, T.G.Palanivelu, B.Revathi

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Electromagnetic interference (EMI) is one of the serious problems in most electrical and electronic appliances including fluorescent lamps. The electronic ballast used to regulate the power flow through the lamp is the major cause for EMI. The interference is because of the high frequency switching operation of the ballast. Formerly, some EMI mitigation techniques were in practice, but they were not satisfactory because of the hardware complexity in the circuit design, increased parasitic components and power consumption and so on. The majority of the researchers have their spotlight only on EMI mitigation without considering the other constraints such as cost, effective operation of the equipment etc. In this paper, we propose a technique for EMI mitigation in fluorescent lamps by integrating Frequency Modulation and Evolutionary Programming. By the Frequency Modulation technique, the switching at a single central frequency is extended to a range of frequencies, and so, the power is distributed throughout the range of frequencies leading to EMI mitigation. But in order to meet the operating frequency of the ballast and the operating power of the fluorescent lamps, an optimal modulation index is necessary for Frequency Modulation. The optimal modulation index is determined using Evolutionary Programming. Thereby, the proposed technique mitigates the EMI to a satisfactory level without disturbing the operation of the fluorescent lamp.

Keywords: Ballast, Electromagnetic interference (EMI), EMImitigation, Evolutionary programming (EP), Fluorescent lamp, Frequency Modulation (FM), Modulation index.

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Authors: S. Chahba, R. Sehab, A. Akrad, C. Morel

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Nowadays, the electric machines used in urban electric vehicles are, in most cases, three-phase electric machines with or without a magnet in the rotor. Permanent Magnet Synchronous Machine (PMSM) and Induction Machine (IM) are the main components of drive trains of electric and hybrid vehicles. These machines have very good performance in healthy operation mode, but they are not redundant to ensure safety in faulty operation mode. Faced with the continued growth in the demand for electric vehicles in the automotive market, improving the reliability of electric vehicles is necessary over the lifecycle of the electric vehicle. Multiphase electric machines respond well to this constraint because, on the one hand, they have better robustness in the event of a breakdown (opening of a phase, opening of an arm of the power stage, intern-turn short circuit) and, on the other hand, better power density. In this work, a diagnosis approach using a neural network for an open circuit fault or more of a five-phase induction machine is developed. Validation on the simulator of the vehicle drivetrain, at reduced power, is carried out, creating one and more open circuit stator phases showing the efficiency and the reliability of the new approach to detect and to locate on-line one or more open phases of a five-induction machine.

Keywords: Electric vehicle drivetrain, multiphase drives, induction machine, control, open circuit fault diagnosis, artificial neural network.

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Authors: Yaw-Juen Wang, Po-Chun Hsu

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This paper presents an equivalent circuit model based on piecewise linear parallel branches (PLPB) to study solar cell modules which are partially shaded. The PLPB model can easily be used in circuit simulation software such as the ElectroMagnetic Transients Program (EMTP). This PLPB model allows the user to simulate several different configurations of solar cells, the influence of partial shadowing on a single or multiple cells, the influence of the number of solar cells protected by a bypass diode and the effect of the cell connection configuration on partial shadowing.

Keywords: Cell Connection Configurations, EMTP, Equivalent Circuit, Partial Shading, Photovoltaic Module

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Authors: J. H. Kim, J. H. Kwon, J. S. Park, K. J. Lim

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This paper has been investigated a technique that predicts the performance of a bar-type unimorph piezoelectric vibration actuator depending on the frequency. This paper has been proposed an equivalent circuit that can be easily analyzed for the bar-type unimorph piezoelectric vibration actuator. In the dynamic analysis, rigidity and resonance frequency, which are important mechanical elements, were derived using the basic beam theory. In the equivalent circuit analysis, the displacement and bandwidth of the piezoelectric vibration actuator depending on the frequency were predicted. Also, for the reliability of the derived equations, the predicted performance depending on the shape change was compared with the result of a finite element analysis program.

Keywords: Actuator, performance, piezoelectric, unimorph.Actuator, performance, piezoelectric, unimorph.

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Authors: Jason Chien-Hsun Tseng, Nguyen Dong-Thai Dao, Chong-Ching Chang

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A novel PDE solver using the multidimensional wave digital filtering (MDWDF) technique to achieve the solution of a 2D seismic wave system is presented. In essence, the continuous physical system served by a linear Kirchhoff circuit is transformed to an equivalent discrete dynamic system implemented by a MD wave digital filtering (MDWDF) circuit. This amounts to numerically approximating the differential equations used to describe elements of a MD passive electronic circuit by a grid-based difference equations implemented by the so-called state quantities within the passive MDWDF circuit. So the digital model can track the wave field on a dense 3D grid of points. Details about how to transform the continuous system into a desired discrete passive system are addressed. In addition, initial and boundary conditions are properly embedded into the MDWDF circuit in terms of state quantities. Graphic results have clearly demonstrated some physical effects of seismic wave (P-wave and S–wave) propagation including radiation, reflection, and refraction from and across the hard boundaries. Comparison between the MDWDF technique and the finite difference time domain (FDTD) approach is also made in terms of the computational efficiency.

Keywords: Seismic Wave Propagation, Multi-dimension WaveDigital Filters, Partial Differential Equations.

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Authors: Ivan Yatchev, Ewen Ritchie

Abstract:

Comparison of two approaches for the simulation of the dynamic behaviour of a permanent magnet linear actuator is presented. These are full coupled model, where the electromagnetic field, electric circuit and mechanical motion problems are solved simultaneously, and decoupled model, where first a set of static magnetic filed analysis is carried out and then the electric circuit and mechanical motion equations are solved employing bi-cubic spline approximations of the field analysis results. The results show that the proposed decoupled model is of satisfactory accuracy and gives more flexibility when the actuator response is required to be estimated for different external conditions, e.g. external circuit parameters or mechanical loads.

Keywords: Coupled problems, dynamic models, finite elementanalysis, linear actuators, permanent magnets.

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Authors: H. Sediki, S. Djennoune

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The switching lag-time and the voltage drop across the power devices cause serious waveform distortions and fundamental voltage drop in pulse width-modulated inverter output. These phenomenons are conspicuous when both the output frequency and voltage are low. To estimate the output voltage from the PWM reference signal it is essential to take account of these imperfections and to correct them. In this paper, on-line compensation method is presented. It needs three simple blocs to add at the ideal reference voltages. This method does not require any additional hardware circuit and off- line experimental measurement. The paper includes experimental results to demonstrate the validity of the proposed method. It is applied, finally, in case of indirect vector controlled induction machine and implemented using dSpace card.

Keywords: Dead time, field-oriented control, Induction motor, PWM inverter, voltage drop.

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Authors: I Made Darmayuda, Chai Tshun Chuan Kevin, Je Minkyu

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Plenty researches have reported techniques to harvest energy from piezoelectric transducer. In the earlier years, the researches mainly report linear energy harvesting techniques whereby interface circuitry is designed to have input impedance that match with the impedance of the piezoelectric transducer. In recent years non-linear techniques become more popular. The non-linear technique employs voltage waveform manipulation to boost the available-for-extraction energy at the time of energy transfer.  The fact that non-linear energy extraction provides larger available-for-extraction energy doesn’t mean the linear energy extraction is completely obsolete. In some scenarios, such as where initial power is not available, linear energy extraction is still preferred. A modified Buck Boost circuit which is capable of harvesting piezoelectric energy using both linear and non-linear techniques is reported in this paper. Efficiency of at least 64% can be achieved using this circuit. For linear extraction, the modified Buck Boost circuit is controlled using a fix frequency and duty cycle clock. A voltage sensor and a pulse generator are added as the controller for the non-linear extraction technique. 

Keywords: Buck boost, energy harvester, linear energy harvester, non-linear energy harvester, piezoelectric, synchronized charge extraction.

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Authors: Zina Saheb, Ezz El-Masry, Jean-François Bousquet

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This paper presents an enhanced efficiency simultaneous dual band energy harvesting system for wireless body area network. A bulk biasing is used to enhance the efficiency of the adapted rectifier design to reduce V_th of MOSFET. The presented circuit harvests the radio frequency (RF) energy from two frequency bands: 1 GHz and 2.4 GHz. It is designed with TSMC 65-nm CMOS technology and high quality factor dual matching network to boost the input voltage. Full circuit analysis and modeling is demonstrated. The simulation results demonstrate a harvester with an efficiency of 23% at 1 GHz and 46% at 2.4 GHz at an input power as low as -30 dBm.

Keywords: Energy harvester, simultaneous, dual band, CMOS, differential rectifier, voltage boosting, TSMC 65nm.

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Authors: Yuzman Yusoff, Siti Noor Harun, Noor Shelida Sallehand Tan Kong Yew

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This paper presents the design and characterization of analog readout interface circuits for ion sensitive field effect transistor (ISFET) and ion selective electrode (ISE) based sensor. These interface circuits are implemented using MIMOS’s 0.35um CMOS technology and experimentally characterized under 24-leads QFN package. The characterization evaluates the circuit’s functionality, output sensitivity and output linearity. Commercial sensors for both ISFET and ISE are employed together with glass reference electrode during testing. The test result shows that the designed interface circuits manage to readout signals produced by both sensors with measured sensitivity of ISFET and ISE sensor are 54mV/pH and 62mV/decade, respectively. The characterized output linearity for both circuits achieves above 0.999 rsquare. The readout also has demonstrated reliable operation by passing all qualifications in reliability test plan.

Keywords: Readout interface circuit (ROIC), analog interface circuit, ion sensitive field effect transistor (ISFET), ion selective electrode (ISE), and ion sensor electronics.

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Authors: Yuzman Yusoff, Siti Noor Harun, Noor Shelida Sallehand, Tan Kong Yew

Abstract:

This paper presents the design and characterization of analog readout interface circuits for ion sensitive field effect transistor (ISFET) and ion selective electrode (ISE) based sensor. These interface circuits are implemented using MIMOS’s 0.35um CMOS technology and experimentally characterized under 24-leads QFN package. The characterization evaluates the circuit’s functionality, output sensitivity and output linearity. Commercial sensors for both ISFET and ISE are employed together with glass reference electrode during testing. The test result shows that the designed interface circuits manage to readout signals produced by both sensors with measured sensitivity of ISFET and ISE sensor are 54mV/pH and 62mV/decade, respectively. The characterized output linearity for both circuits achieves above 0.999 Rsquare. The readout also has demonstrated reliable operation by passing all qualifications in reliability test plan.

Keywords: Readout interface circuit (ROIC), analog interface circuit, ion sensitive field effect transistor (ISFET), ion selective electrode (ISE), ion sensor electronics.

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Authors: Igor Luiz Bernardes de Moura, Luan Carlos de Sena Monteiro Ozelim, Fabiano Araujo Soares

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The development of an low cost acquisition system of S-EMG signals which are reliable, comfortable for the user and with high mobility shows to be a relevant proposition in modern biomedical engineering scenario. In the study, the sampling capacity of the Arduino microcontroller Atmel Atmega328 with an A / D converter with 10-bit resolution and its reconstructing capability of a signal of surface electromyography is analyzed. An electronic circuit to capture the signal through two differential channels was designed, signals from Biceps Brachialis of a healthy man of 21 years was acquired to test the system prototype. ARV, MDF, MNF and RMS estimators were used to compare de acquired signals with physiological values. The Arduino was configured with a sampling frequency of 1.5kHz for each channel, and the tests with the circuit designed offered a SNR of 20.57dB.

Keywords: Eletromyography, Arduino, Low-Cost, Atmel Atmega328 microcontroller.

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Authors: M. Ghareh, L. Sepahi

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Temperature rise in a transformer depends on variety of parameters such as ambient temperature, output current and type of the core. Considering these parameters, temperature rise estimation is still complicated procedure. In this paper, we present a new model based on simple electrical equivalent circuit. This method avoids the complication associated to accurate estimation and is in very good agreement with practice.

Keywords: Thermal modeling, temperature rise, equivalent thermal circuit.

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Authors: N. Muthukumaran, R. Ravi

Abstract:

The Simulation based VLSI Implementation of FELICS (Fast Efficient Lossless Image Compression System) Algorithm is proposed to provide the lossless image compression and is implemented in simulation oriented VLSI (Very Large Scale Integrated). To analysis the performance of Lossless image compression and to reduce the image without losing image quality and then implemented in VLSI based FELICS algorithm. In FELICS algorithm, which consists of simplified adjusted binary code for Image compression and these compression image is converted in pixel and then implemented in VLSI domain. This parameter is used to achieve high processing speed and minimize the area and power. The simplified adjusted binary code reduces the number of arithmetic operation and achieved high processing speed. The color difference preprocessing is also proposed to improve coding efficiency with simple arithmetic operation. Although VLSI based FELICS Algorithm provides effective solution for hardware architecture design for regular pipelining data flow parallelism with four stages. With two level parallelisms, consecutive pixels can be classified into even and odd samples and the individual hardware engine is dedicated for each one. This method can be further enhanced by multilevel parallelisms.

Keywords: Image compression, Pixel, Compression Ratio, Adjusted Binary code, Golumb Rice code, High Definition display, VLSI Implementation.

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Authors: Rohana Musa, Yuzman Yusoff, Chia Chieu Yin, Hanif Che Lah

Abstract:

This paper presents the design and characterization of a low power Complementary Metal Oxide Semiconductor (CMOS) process sensor. The design is targeted for implementation using Silterra’s 180 nm CMOS process technology. The proposed process sensor employs a voltage threshold (V_th) extractor architecture for detection of variations in the fabrication process. The process sensor generates output voltages in the range of 401 mV (fast-fast corner) to 443 mV (slow-slow corner) at nominal condition. The power dissipation for this process sensor is 6.3 µW with a supply voltage of 1.8V with a silicon area of 190 µm X 60 µm. The preliminary result of this process sensor that was fabricated indicates a close resemblance between test and simulated results.

Keywords: CMOS Process sensor, Process, Voltage and Temperature (PVT) sensor, threshold extractor circuit, Vth extractor circuit.

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Authors: Saih Mohamed, Rouijaa Hicham, Ghammaz Abdelilah

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This paper presents circuit models to analyze the conducted susceptibility of multiconductor shielded cables in frequency domains using Branin’s method, which is referred to as the method of characteristics. These models, which can be used directly in the time and frequency domains, take into account the presence of both the transfer impedance and admittance. The conducted susceptibility is studied by using an injection current on the cable shield as the source. Two examples are studied; a coaxial shielded cable and shielded cables with two parallel wires (i.e., twinax cables). This shield has an asymmetry (one slot on the side). Results obtained by these models are in good agreement with those obtained by other methods.

Keywords: Circuit models, multiconductor shielded cables, Branin’s method, coaxial shielded cable, twinax cables.

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Authors: Mohamed EL Boujnouni, Mohamed Jedra, Noureddine Zahid

Abstract:

Support Vector Domain Description (SVDD) is one of the best-known one-class support vector learning methods, in which one tries the strategy of using balls defined on the feature space in order to distinguish a set of normal data from all other possible abnormal objects. As all kernel-based learning algorithms its performance depends heavily on the proper choice of the kernel parameter. This paper proposes a new approach to select kernel's parameter based on maximizing the distance between both gravity centers of normal and abnormal classes, and at the same time minimizing the variance within each class. The performance of the proposed algorithm is evaluated on several benchmarks. The experimental results demonstrate the feasibility and the effectiveness of the presented method.

Keywords: Gravity centers, Kernel’s parameter, Support Vector Domain Description, Variance.

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Authors: Marcus Banda

Abstract:

In this article the influence of higher frequency effects in addition to a special damper design on the electrical behavior of a synchronous generator main exciter machine is investigated. On the one hand these machines are often highly stressed by harmonics from the bridge rectifier thus facing additional eddy current losses. On the other hand the switching may cause the excitation of dangerous voltage peaks in resonant circuits formed by the diodes of the rectifier and the commutation reactance of the machine. Therefore modern rotating exciters are treated like synchronous generators usually modeled with a second order equivalent circuit. Hence the well known Standstill Frequency Response Test (SSFR) method is applied to a test machine in order to determine parameters for the simulation. With these results it is clearly shown that higher frequencies have a strong impact on the conventional equivalent circuit model. Because of increasing field displacement effects in the stranded armature winding the sub-transient reactance is even smaller than the armature leakage at high frequencies. As a matter of fact this prevents the algorithm to find an equivalent scheme. This issue is finally solved using Laplace transfer functions fully describing the transient behavior at the model ports.

Keywords: Synchronous exciter machine, Linear transfer function, SSFR, Equivalent Circuit

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Authors: Rekha V. Dundur , M.V.Latte, S.Y. Kulkarni, M.K.Venkatesha

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The advent of multi-million gate Field Programmable Gate Arrays (FPGAs) with hardware support for multiplication opens an opportunity to recreate a significant portion of the front end of a human cochlea using this technology. In this paper we describe the implementation of the cochlear filter and show that it is entirely suited to a single device XC3S500 FPGA implementation .The filter gave a good fit to real time data with efficiency of hardware usage.

Keywords: Cochlea, FPGA, IIR (Infinite Impulse Response), Multiplier.

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Authors: L. Tani, N. El Ouzzani

Abstract:

Crosstalk among interconnects and printed-circuit board (PCB) traces is a major limiting factor of signal quality in highspeed digital and communication equipments especially when fast data buses are involved. Such a bus is considered as a planar multiconductor transmission line. This paper will demonstrate how the finite difference time domain (FDTD) method provides an exact solution of the transmission-line equations to analyze the near end and the far end crosstalk. In addition, this study makes it possible to analyze the rise time effect on the near and far end voltages of the victim conductor. The paper also discusses a statistical analysis, based upon a set of several simulations. Such analysis leads to a better understanding of the phenomenon and yields useful information.

Keywords: Multiconductor transmission line, Crosstalk, Finite difference time domain (FDTD), printed-circuit board (PCB), Rise time, Statistical analysis.

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Authors: K. Horáková, K. Fraňa, V. Honzejk

Abstract:

This part of study deals with description of unsteady isothermal melt flow in the container with cuboid shape. This melt flow is driven by rotating magnetic field. Input data (instantaneous velocities, grid coordinates and Lorentz forces) were obtained from in-house CFD code (called NS-FEM3D) which uses DDES method of computing. Description of the flow was performed by contours of Lorentz forces and caused velocity field. Taylor magnetic numbers of the flow were used 1.10^6, 5.10^6 and 1.10^7, flow was in 3D turbulent flow regime.

Keywords: In-house computing code, Lorentz forces, magnetohydrodynamics, rotating magnetic field.

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Authors: Jawad Ahmad, Hee-Jun Kim

Abstract:

This paper describes the design of a voltage based maximum power point tracker (MPPT) for photovoltaic (PV) applications. Of the various MPPT methods, the voltage based method is considered to be the simplest and cost effective. The major disadvantage of this method is that the PV array is disconnected from the load for the sampling of its open circuit voltage, which inevitably results in power loss. Another disadvantage, in case of rapid irradiance variation, is that if the duration between two successive samplings, called the sampling period, is too long there is a considerable loss. This is because the output voltage of the PV array follows the unchanged reference during one sampling period. Once a maximum power point (MPP) is tracked and a change in irradiation occurs between two successive samplings, then the new MPP is not tracked until the next sampling of the PV array voltage. This paper proposes an MPPT circuit in which the sampling interval of the PV array voltage, and the sampling period have been shortened. The sample and hold circuit has also been simplified. The proposed circuit does not utilize a microcontroller or a digital signal processor and is thus suitable for low cost and low power applications.

Keywords: Maximum power point tracker, Sample and hold amplifier, Sampling interval, Sampling period.

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Authors: B. Sathyanandhi, P. M. Balasubramaniam

Abstract:

This paper presents Buck-Boost converter topology to maintain the input power factor by using the power factor stage control and regulation stage control. Suppose, if we are using the RL load the power factor will be reduced due to the presence of total harmonic distortion in the current wave. To improve the power factor the current waveform should follow the fundamental component of the voltage waveform. These can be achieved by using the high -frequency power converter. Based on the resonant circuit the converter is able to perform the function of Buck, Boost, and buck-boost converter. Here ,we have used Buck-Boost converter, because, the buck-boost converter has more advantages than the boost converter. Here the switching action of the power converter can  take place by using the external zero comparator PFC stage control. The power converter consisting of the resonant  circuit which is used to control the output voltage gain of the converter. The power converter is operated at a very high switching frequency in the range of 400KHz in order to overcome the switching losses of the power converter. Due to  presence of high switching frequency, the power factor will improve. Therefore, the total harmonics distortion present in the current waveform has also reduced. These results has generated in the form of simulation by using MATLAB/SIMULINK software.  Similar to the Buck and Boost converters, the operation of the Buck-Boost has best understood, in terms of the inductor's "reluctance" for allowing rapid change in current, which also reduces the Total Harmonic Distortion (THD) in the input current waveform, which can improve the input Power factor, based on the type of load used.

Keywords: Buck-boost converter, High switching frequency, Power factor correction, power factor correction stage Regulation stage, Total harmonic distortion (THD).

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Authors: Cyrille Lambert, Tatiana Kalganova, Emanuele Stomeo

Abstract:

Since 1992, year where Hugo de Garis has published the first paper on Evolvable Hardware (EHW), a period of intense creativity has followed. It has been actively researched, developed and applied to various problems. Different approaches have been proposed that created three main classifications: extrinsic, mixtrinsic and intrinsic EHW. Each of these solutions has a real interest. Nevertheless, although the extrinsic evolution generates some excellent results, the intrinsic systems are not so advanced. This paper suggests 3 possible solutions to implement the run-time configuration intrinsic EHW system: FPGA-based Run-Time Configuration system, JBits-based Run-Time Configuration system and Multi-board functional-level Run-Time Configuration system. The main characteristic of the proposed architectures is that they are implemented on Field Programmable Gate Array. A comparison of proposed solutions demonstrates that multi-board functional-level run-time configuration is superior in terms of scalability, flexibility and the implementation easiness.

Keywords: Evolvable hardware, evolutionary computation, FPGA systems.

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Authors: Iqbalur Rahman, Miftahur Rahman, Abul L Haque, Mostafizur Rahman,

Abstract:

In this paper, RSA encryption algorithm and its hardware implementation in Xilinx-s Virtex Field Programmable Gate Arrays (FPGA) is analyzed. The issues of scalability, flexible performance, and silicon efficiency for the hardware acceleration of public key crypto systems are being explored in the present work. Using techniques based on the interleaved math for exponentiation, the proposed RSA calculation architecture is compared to existing FPGA-based solutions for speed, FPGA utilization, and scalability. The paper covers the RSA encryption algorithm, interleaved multiplication, Miller Rabin algorithm for primality test, extended Euclidean math, basic FPGA technology, and the implementation details of the proposed RSA calculation architecture. Performance of several alternative hardware architectures is discussed and compared. Finally, conclusion is drawn, highlighting the advantages of a fully flexible & parameterized design.

Keywords: Crypto Accelerator, FPGA, Public Key Cryptography, RSA.

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