Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 16

Search results for: Tcad Silvaco.

16 Comparison between the Efficiency of Heterojunction Thin Film InGaP\GaAs\Ge and InGaP\GaAs Solar Cell

Authors: F. Djaafar, B. Hadri, G. Bachir

Abstract:

This paper presents the design parameters for a thin film 3J InGaP/GaAs/Ge solar cell with a simulated maximum efficiency of 32.11% using Tcad Silvaco. Design parameters include the doping concentration, molar fraction, layers’ thickness and tunnel junction characteristics. An initial dual junction InGaP/GaAs model of a previous published heterojunction cell was simulated in Tcad Silvaco to accurately predict solar cell performance. To improve the solar cell’s performance, we have fixed meshing, material properties, models and numerical methods. However, thickness and layer doping concentration were taken as variables. We, first simulate the InGaP\GaAs dual junction cell by changing the doping concentrations and thicknesses which showed an increase in efficiency. Next, a triple junction InGaP/GaAs/Ge cell was modeled by adding a Ge layer to the previous dual junction InGaP/GaAs model with an InGaP /GaAs tunnel junction.

Keywords: Heterojunction, modeling, simulation, thin film, Tcad Silvaco.

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15 3D Quantum Numerical Simulation of Horizontal Rectangular Dual Metal Gate\Gate All Around MOSFETs

Authors: M. Khaouani, A. Guen-Bouazza, B. Bouazza, Z. Kourdi

Abstract:

The integrity and issues related to electrostatic performance associated with scaling Si MOSFET bulk sub 10nm channel length promotes research in new device architectures such as SOI, double gate and GAA MOSFET. In this paper, we present some novel characteristic of horizontal rectangular gate\gate all around MOSFETs with dual metal of gate we obtained using SILVACO TCAD tools. We will also exhibit some simulation results we obtained relating to the influence of some parameters variation on our structure, that having a direct impact on their threshold voltage and drain current. In addition, our TFET showed reasonable ION/IOFF ratio of (104) and low drain induced barrier lowering (DIBL) of 39 mV/V.

Keywords: GAA, SILVACO, QUANTUM, MOSFETs.

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14 Simulation of High Performance Nanoscale Partially Depleted SOI n-MOSFET Transistors

Authors: Fatima Zohra Rahou, A. Guen Bouazza, B. Bouazza

Abstract:

Invention of transistor is the foundation of electronics industry. Metal Oxide Semiconductor Field Effect Transistor (MOSFET) has been the key for the development of nanoelectronics technology. In the first part of this manuscript, we present a new generation of MOSFET transistors based on SOI (Silicon-On-Insulator) technology. It is a partially depleted Silicon-On-Insulator (PD SOI MOSFET) transistor simulated by using SILVACO software. This work was completed by the presentation of some results concerning the influence of parameters variation (channel length L and gate oxide thickness Tox) on our PDSOI n-MOSFET structure on its drain current and kink effect.

Keywords: SOI technology, PDSOI MOSFET, FDSOI MOSFET, Kink Effect, SILVACO TCAD.

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13 Impact of Height of Silicon Pillar on Vertical DG-MOSFET Device

Authors: K. E. Kaharudin, A. H. Hamidon, F. Salehuddin

Abstract:

Vertical Double Gate (DG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is believed to suppress various short channel effect problems. The gate to channel coupling in vertical DG-MOSFET are doubled, thus resulting in higher current density. By having two gates, both gates are able to control the channel from both sides and possess better electrostatic control over the channel. In order to ensure that the transistor possess a superb turn-off characteristic, the subs-threshold swing (SS) must be kept at minimum value (60-90mV/dec). By utilizing SILVACO TCAD software, an n-channel vertical DG-MOSFET was successfully designed while keeping the sub-threshold swing (SS) value as minimum as possible. From the observation made, the value of sub-threshold swing (SS) was able to be varied by adjusting the height of the silicon pillar. The minimum value of sub-threshold swing (SS) was found to be 64.7mV/dec with threshold voltage (VTH) of 0.895V. The ideal height of the vertical DG-MOSFET pillar was found to be at 0.265 µm.

Keywords: DG-MOSFET, pillar, SCE, vertical

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12 On the Operation Mechanism and Device Modeling of AlGaN/GaN High Electron Mobility Transistors (HEMTs)

Authors: Li Yuan, Weizhu Wang, Kean Boon Lee, Haifeng Sun, Susai Lawrence Selvaraj, Shane Todd, Guo-Qiang Lo

Abstract:

In this work, the physical based device model of AlGaN/GaN high electron mobility transistors (HEMTs) has been established and the corresponding device operation behavior has been investigated also by using Sentaurus TCAD from Synopsys. Advanced AlGaN/GaN hetero-structures with GaN cap layer and AlN spacer have been considered and the GaN cap layer and AlN spacer are found taking important roles on the gate leakage blocking and off-state breakdown voltage enhancement.

Keywords: AlGaN/GaN, HEMT, Physical mechanism, TCAD simulation

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11 A Physically-Based Analytical Model for Reduced Surface Field Laterally Double Diffused MOSFETs

Authors: M. Abouelatta, A. Shaker, M. El-Banna, G. T. Sayah, C. Gontrand, A. Zekry

Abstract:

In this paper, a methodology for physically modeling the intrinsic MOS part and the drift region of the n-channel Laterally Double-diffused MOSFET (LDMOS) is presented. The basic physical effects like velocity saturation, mobility reduction, and nonuniform impurity concentration in the channel are taken into consideration. The analytical model is implemented using MATLAB. A comparison of the simulations from technology computer aided design (TCAD) and that from the proposed analytical model, at room temperature, shows a satisfactory accuracy which is less than 5% for the whole voltage domain.

Keywords: LDMOS, MATLAB, RESURF, modeling, TCAD.

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10 Static and Dynamic Characteristics of an Appropriated and Recessed n-GaN/AlGaN/GaN HEMT

Authors: A. Hamdoune, M. Abdelmoumene, A. Hamroun

Abstract:

The objective of this paper is to simulate static I-V and dynamic characteristics of an appropriated and recessed n-GaN/AlxGa1-xN/GaN high electron mobility (HEMT). Using SILVACO TCAD device simulation, and optimized technological parameters; we calculate the drain-source current (lDS) as a function of the drain-source voltage (VDS) for different values ​​of the gate-source voltage (VGS), and the drain-source current (lDS) depending on the gate-source voltage (VGS) for a drain-source voltage (VDS) of 20 V, for various temperatures. Then, we calculate the cut-off frequency and the maximum oscillation frequency for different temperatures.

We obtain a high drain-current equal to 60 mA, a low knee voltage (Vknee) of 2 V, a high pinch-off voltage (VGS0) of 53.5 V, a transconductance greater than 600 mS/mm, a cut-off frequency (fT) of about 330 GHz, and a maximum oscillation frequency (fmax) of about 1 THz.

Keywords: n-GaN/AlGaN/GaN HEMT, drain-source current (IDS), transconductance (gm), cut-off frequency (fT), maximum oscillation frequency (fmax).

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9 SCR-Based Advanced ESD Protection Device for Low Voltage Application

Authors: Bo Bae Song, Byung Seok Lee, Hyun Young Kim, Chung Kwang Lee, Yong Seo Koo

Abstract:

This paper proposed a silicon controller rectifier (SCR) based ESD protection device to protect low voltage ESD for integrated circuit. The proposed ESD protection device has low trigger voltage and high holding voltage compared with conventional SCR-based ESD protection devices. The proposed ESD protection circuit is verified and compared by TCAD simulation. This paper verified effective low voltage ESD characteristics with low trigger voltage of 5.79V and high holding voltage of 3.5V through optimization depending on design variables (D1, D2, D3 and D4).

Keywords: ESD, SCR, Holding voltage, Latch-up.

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8 Analysis of SCR-Based ESD Protection Circuit on Holding Voltage Characteristics

Authors: Yong Seo Koo, Jong Ho Nam, Yong Nam Choi, Dae Yeol Yoo, Jung Woo Han

Abstract:

This paper presents a silicon controller rectifier (SCR) based ESD protection circuit for IC. The proposed ESD protection circuit has low trigger voltage and high holding voltage compared with conventional SCR ESD protection circuit. Electrical characteristics of the proposed ESD protection circuit are simulated and analyzed using TCAD simulator. The proposed ESD protection circuit verified effective low voltage ESD characteristics with low trigger voltage and high holding voltage.

Keywords: ESD (Electro-Static Discharge), SCR (Silicon Controlled Rectifier), holding Voltage.

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7 Performance of InGaN/GaN Laser Diode Based on Quaternary Alloys Stopper and Superlattice Layers

Authors: S. M. Thahab, H. Abu Hassan, Z. Hassan

Abstract:

The optical properties of InGaN/GaN laser diode based on quaternary alloys stopper and superlattice layers are numerically studied using ISE TCAD (Integrated System Engineering) simulation program. Improvements in laser optical performance have been achieved using quaternary alloy as superlattice layers in InGaN/GaN laser diodes. Lower threshold current of 18 mA and higher output power and slope efficiency of 22 mW and 1.6 W/A, respectively, at room temperature have been obtained. The laser structure with InAlGaN quaternary alloys as an electron blocking layer was found to provide better laser performance compared with the ternary AlxGa1-xN blocking layer.

Keywords: Nitride semiconductors, InAlGaN quaternary, laserdiode, superlattice.

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6 A Silicon Controlled Rectifier-Based ESD Protection Circuit with High Holding Voltage and High Robustness Characteristics

Authors: Kyoung-il Do, Byung-seok Lee, Hee-guk Chae, Jeong-yun Seo Yong-seo Koo

Abstract:

In this paper, a Silicon Controlled Rectifier (SCR)-based Electrostatic Discharge (ESD) protection circuit with high holding voltage and high robustness characteristics is proposed. Unlike conventional SCR, the proposed circuit has low trigger voltage and high holding voltage and provides effective ESD protection with latch-up immunity. In addition, the TCAD simulation results show that the proposed circuit has better electrical characteristics than the conventional SCR. A stack technology was used for voltage-specific applications. Consequentially, the proposed circuit has a trigger voltage of 17.60 V and a holding voltage of 3.64 V.

Keywords: ESD, SCR, latch-up, power clamp, holding voltage.

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5 Suppressing Ambipolar Conduction Using Dual Material Gate in Tunnel-FETs Having Heavily Doped Drain

Authors: Dawit Burusie Abdi, Mamidala Jagadesh Kumar

Abstract:

In this paper, using 2D TCAD simulations, the application of a dual material gate (DMG) for suppressing ambipolar conduction in a tunnel field effect transistor (TFET) is demonstrated. Using the proposed DMG concept, the ambipolar conduction can be effectively suppressed even if the drain doping is as high as that of the source doping. Achieving this symmetrical doping, without the ambipolar conduction in TFETs, gives the advantage of realizing both n-type and p-type devices with the same doping sequences. Furthermore, the output characteristics of the DMG TFET exhibit a good saturation when compared to that of the gate-drain underlap approach. This improved behavior of the DMG TFET makes it a good candidate for inverter based logic circuits.

Keywords: Dual material gate, suppressing ambipolar current, symmetrically doped TFET, tunnel FETs, PNPN TFET.

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4 Characterization of the LMOS with Different Channel Structure

Authors: Hung-Pei Hsu, Jyi-Tsong Lin, Po-Hsieh Lin, Cheng-Hsien Chang, Ming-Tsung Shih, Chan-Hsiang Chang, Shih-Chuan Tseng, Min-Yan Lin, Shih-Wen Hsu

Abstract:

In this paper, we propose a novel metal oxide semiconductor field effect transistor with L-shaped channel structure (LMOS), and several type of L-shaped structures are also designed, studied and compared with the conventional MOSFET device for the same average gate length (Lavg). The proposed device electrical characteristics are analyzed and evaluated by three dimension (3-D) ISE-TCAD simulator. It can be confirmed that the LMOS devices have higher on-state drain current and both lower drain-induced barrier lowering (DIBL) and subthreshold swing (S.S.) than its conventional counterpart has. In addition, the transconductance and voltage gain properties of the LMOS are also improved.

Keywords: Average gate length (Lavg), drain-induced barrier lowering (DIBL), L-shaped channel MOSFET (LMOS), subthreshold swing (S.S.).

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3 SCR-Stacking Structure with High Holding Voltage for I/O and Power Clamp

Authors: Hyun-Young Kim, Chung-Kwang Lee, Han-Hee Cho, Sang-Woon Cho, Yong-Seo Koo

Abstract:

In this paper, we proposed a novel SCR (Silicon Controlled Rectifier) - based ESD (Electrostatic Discharge) protection device for I/O and power clamp. The proposed device has a higher holding voltage characteristic than conventional SCR. These characteristics enable to have latch-up immunity under normal operating conditions as well as superior full chip ESD protection. The proposed device was analyzed to figure out electrical characteristics and tolerance robustness in term of individual design parameters (D1, D2, D3). They are investigated by using the Synopsys TCAD simulator. As a result of simulation, holding voltage increased with different design parameters. The holding voltage of the proposed device changes from 3.3V to 7.9V. Also, N-Stack structure ESD device with the high holding voltage is proposed. In the simulation results, 2-stack has holding voltage of 6.8V and 3-stack has holding voltage of 10.5V. The simulation results show that holding voltage of stacking structure can be larger than the operation voltage of high-voltage application.

Keywords: ESD, SCR, holding voltage, stack, power clamp.

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2 Optimization of HALO Structure Effects in 45nm p-type MOSFETs Device Using Taguchi Method

Authors: F. Salehuddin, I. Ahmad, F. A. Hamid, A. Zaharim, H. A. Elgomati, B. Y. Majlis, P. R. Apte

Abstract:

In this study, the Taguchi method was used to optimize the effect of HALO structure or halo implant variations on threshold voltage (VTH) and leakage current (ILeak) in 45nm p-type Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) device. Besides halo implant dose, the other process parameters which used were Source/Drain (S/D) implant dose, oxide growth temperature and silicide anneal temperature. This work was done using TCAD simulator, consisting of a process simulator, ATHENA and device simulator, ATLAS. These two simulators were combined with Taguchi method to aid in design and optimize the process parameters. In this research, the most effective process parameters with respect to VTH and ILeak are halo implant dose (40%) and S/D implant dose (52%) respectively. Whereas the second ranking factor affecting VTH and ILeak are oxide growth temperature (32%) and halo implant dose (34%) respectively. The results show that after optimizations approaches is -0.157V at ILeak=0.195mA/μm.

Keywords: Optimization, p-type MOSFETs device, HALO Structure, Taguchi Method.

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1 InAlGaN Quaternary Multi-Quantum Wells UVLaser Diode Performance and Characterization

Authors: S. M. Thahab, H. Abu Hassan, Z. Hassan

Abstract:

The InAlGaN alloy has only recently began receiving serious attention into its growth and application. High quality InGaN films have led to the development of light emitting diodes (LEDs) and blue laser diodes (LDs). The quaternary InAlGaN however, represents a more versatile material since the bandgap and lattice constant can be independently varied. We report an ultraviolet (UV) quaternary InAlGaN multi-quantum wells (MQWs) LD study by using the simulation program of Integrated System Engineering (ISE TCAD). Advanced physical models of semiconductor properties were used in order to obtain an optimized structure. The device performance which is affected by piezoelectric and thermal effects was studied via drift-diffusion model for carrier transport, optical gain and loss. The optical performance of the UV LD with different numbers of quantum wells was numerically investigated. The main peak of the emission wavelength for double quantum wells (DQWs) was shifted from 358 to 355.8 nm when the forward current was increased. Preliminary simulated results indicated that better output performance and lower threshold current could be obtained when the quantum number is four, with output power of 130 mW and threshold current of 140 mA.

Keywords: Nitride semiconductors, InAlGaN quaternary, UVLD, numerical simulation.

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