A Physically-Based Analytical Model for Reduced Surface Field Laterally Double Diffused MOSFETs
In this paper, a methodology for physically modeling the intrinsic MOS part and the drift region of the n-channel Laterally Double-diffused MOSFET (LDMOS) is presented. The basic physical effects like velocity saturation, mobility reduction, and nonuniform impurity concentration in the channel are taken into consideration. The analytical model is implemented using MATLAB. A comparison of the simulations from technology computer aided design (TCAD) and that from the proposed analytical model, at room temperature, shows a satisfactory accuracy which is less than 5% for the whole voltage domain.
Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1130923Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 696
 M. Mehrad, and A. A. Orouji, “Injected charges in partial SOI LDMOSFETs: a new technique for improving the breakdown voltage,” Superlattices Microstruct., vol. 57, pp. 77-84, May 2013.
 N. Prasad, P. Sarangapani, K. N. S. Nikhil, N. Das Gupta, A. Das Gupta, and A. Chakravorty, “An improved Quasi-Saturation and charge model for SOI-LDMOS transistors,” IEEE Trans. Elect. Devices, vol. 62, no. 3, pp. 919-926, Mar 2015.
 J. F. Yao, Y. F. Guo, T. Xia, J. Zhang, and H. Lin, “3D analytical model for the SOI LDMOS with alternating silicon and high-k dielectric pillars,” Superlattices and Microstructures, vol. 96, pp. 95-103, Aug 2016.
 J. Victory., C. C. McAndrew, R. Thoma, K. Joardar, M. Kniffin, S. Merchant, and D. Moncoqut, “A Physically-Based Compact Model for LDMOS Transistors,” IEEE Proc. International Conference on Simulation of Semiconductor Processes and Devices SISPAD, pp. 271-274, 1998.
 Y.-S. Kim, J. G. Fossum, and R. K. Williams, “New Physical Insights and Models for High-Voltage LDMOST IC CAD,” IEEE Trans. Electron Devices, vol. 38, pp.1641-1649, July 1991.
 J. Jang, O. Tornblad, T. Arnborg, Q. Chen, K. Banerjee, Z. Yu, and R. W. Dutton, “RF LDMOS characterization and its compact modeling,” IEEE MTT S INT MICROWAVE SYMP DIG, vol. 2, pp. 967-970, May 2001.
 J. Jang et al., “Circuit Model for Power LDMOS including Quasi-Saturation", Proc. SISPAD, pp. 15-18, 1999.
 M. Y. Hong, and D. A. Antoniadis, “Theoretical Analysis and Modeling of Submicron Channel Length DMOS Transistors", IEEE Trans. Electron Devices, vol. 42, no 9, pp. 1614-1622, 1995.
 Y. Chung, "LADISPICE-1.2: A Nonplanar-Drift Lateral DMOS Transistor Model and its Application to Power IC TCAD", IEE Proc. Circuits Devices Syst., vol. 147, no 4, pp. 219-227, 2000.
 R. Kraus, and H. Mattausch, “Status and Trends of Power Semiconductor Device Models for Circuit Simulation”, IEEE Trans. Power Electronics, vol. 13, no 3, May 1998.
 W. Fichtner, N. Braga, M. Ciappa, V. Mickevicius, and M. Schenkel, “Progress in Technology CAD for Power Devices, Circuits and Systems”, IEEE Proc. ISPSD, pp. 1 – 9, 2005.
 Modelling of high-voltage LDMOS in power ICs, Agilent, 2006. http://www.paper.edu.cn/download_feature_paper.php?serial_number=Agilent2006D002.
 C. Anghel, High voltage devices for standard MOS technologies-characterisation and modelling, Ph.D. dissertation, EPFL, 2004. http://biblion.epfl.ch/EPFL/theses/2004/3116/EPFL_TH3116.pdf.
 Y. S. Chauhan, C. Anghel, F. Krummenacher, A. M. Ionescu, M. Declercq, R. Gillon, S. Frere, and B. Desoete, “A Highly Scalable High Voltage MOSFET Model”, IEEE Proc. ESSDERC, pp.270-273, 2006.
 C. W. Tang, and K. Y. Tong, “A compact large signal model of LDMOS,” Solid-State Electronics, vol. 46, no. 12, pp. 2111-2115, 2002.
 J. Meng, S. Gao, J. Ning, and C. D. Ming Ke, “The analysis and modeling of on-resistance in high-voltage LDMOS”, IEEE Proc. International Conference on Solid-State and Integrated Circuit Technology ICSICT, pp. 1327 – 1329, 2006.
 A. Aarts, N. D'Halleweyn, and R. van Langevelde, “A surfacepotential-based high-voltage compact LDMOS transistor model,” IEEE Trans. Electron Devices, vol. 52, no. 5, pp. 999- 1007, 2005.
 J. C. W. Ng, and J. K. O. Sin, “Extraction of the Inversion and Accumulation Layer Mobilities in n-Channel Trench DMOSFETs”, IEEE Tran. Electron Devices, vol. 53, no. 8, pp. 1914 – 1921, 2006.