In this paper, a methodology for physically modeling the intrinsic MOS part and the drift region of the n-channel Laterally Double-diffused MOSFET (LDMOS) is presented. The basic physical effects like velocity saturation, mobility reduction, and nonuniform impurity concentration in the channel are taken into consideration. The analytical model is implemented using MATLAB. A comparison of the simulations from technology computer aided design (TCAD) and that from the proposed analytical model, at room temperature, shows a satisfactory accuracy which is less than 5% for the whole voltage domain.<\/p>\r\n","references":"[1]\tM. Mehrad, and A. A. Orouji, \u201cInjected charges in partial SOI LDMOSFETs: a new technique for improving the breakdown voltage,\u201d Superlattices Microstruct., vol. 57, pp. 77-84, May 2013.\r\n[2]\tN. Prasad, P. Sarangapani, K. N. S. Nikhil, N. Das Gupta, A. Das Gupta, and A. Chakravorty, \u201cAn improved Quasi-Saturation and charge model for SOI-LDMOS transistors,\u201d IEEE Trans. Elect. Devices, vol. 62, no. 3, pp. 919-926, Mar 2015.\r\n[3]\tJ. F. Yao, Y. F. Guo, T. Xia, J. Zhang, and H. Lin, \u201c3D analytical model for the SOI LDMOS with alternating silicon and high-k dielectric pillars,\u201d Superlattices and Microstructures, vol. 96, pp. 95-103, Aug 2016. \r\n[4]\tJ. Victory., C. C. McAndrew, R. Thoma, K. Joardar, M. Kniffin, S. Merchant, and D. Moncoqut, \u201cA Physically-Based Compact Model for LDMOS Transistors,\u201d IEEE Proc. International Conference on Simulation of Semiconductor Processes and Devices SISPAD, pp. 271-274, 1998.\r\n[5]\tY.-S. Kim, J. G. Fossum, and R. K. Williams, \u201cNew Physical Insights and Models for High-Voltage LDMOST IC CAD,\u201d IEEE Trans. Electron Devices, vol. 38, pp.1641-1649, July 1991.\r\n[6]\tJ. Jang, O. Tornblad, T. Arnborg, Q. Chen, K. Banerjee, Z. Yu, and R. W. Dutton, \u201cRF LDMOS characterization and its compact modeling,\u201d IEEE MTT S INT MICROWAVE SYMP DIG, vol. 2, pp. 967-970, May 2001.\r\n[7]\tJ. Jang et al., \u201cCircuit Model for Power LDMOS including Quasi-Saturation\", Proc. SISPAD, pp. 15-18, 1999. \r\n[8]\tM. Y. Hong, and D. A. Antoniadis, \u201cTheoretical Analysis and Modeling of Submicron Channel Length DMOS Transistors\", IEEE Trans. Electron Devices, vol. 42, no 9, pp. 1614-1622, 1995.\r\n[9]\tY. Chung, \"LADISPICE-1.2: A Nonplanar-Drift Lateral DMOS Transistor Model and its Application to Power IC TCAD\", IEE Proc. Circuits Devices Syst., vol. 147, no 4, pp. 219-227, 2000.\r\n[10]\tR. Kraus, and H. Mattausch, \u201cStatus and Trends of Power Semiconductor Device Models for Circuit Simulation\u201d, IEEE Trans. Power Electronics, vol. 13, no 3, May 1998.\r\n[11]\tW. Fichtner, N. Braga, M. Ciappa, V. Mickevicius, and M. Schenkel, \u201cProgress in Technology CAD for Power Devices, Circuits and Systems\u201d, IEEE Proc. ISPSD, pp. 1 \u2013 9, 2005.\r\n[12]\tModelling of high-voltage LDMOS in power ICs, Agilent, 2006. http:\/\/www.paper.edu.cn\/download_feature_paper.php?serial_number=Agilent2006D002.\r\n[13]\tC. Anghel, High voltage devices for standard MOS technologies-characterisation and modelling, Ph.D. dissertation, EPFL, 2004. http:\/\/biblion.epfl.ch\/EPFL\/theses\/2004\/3116\/EPFL_TH3116.pdf.\r\n[14]\tY. S. Chauhan, C. Anghel, F. Krummenacher, A. M. Ionescu, M. Declercq, R. Gillon, S. Frere, and B. Desoete, \u201cA Highly Scalable High Voltage MOSFET Model\u201d, IEEE Proc. ESSDERC, pp.270-273, 2006.\r\n[15]\tC. W. Tang, and K. Y. Tong, \u201cA compact large signal model of LDMOS,\u201d Solid-State Electronics, vol. 46, no. 12, pp. 2111-2115, 2002.\r\n[16]\tJ. Meng, S. Gao, J. Ning, and C. D. Ming Ke, \u201cThe analysis and modeling of on-resistance in high-voltage LDMOS\u201d, IEEE Proc. International Conference on Solid-State and Integrated Circuit Technology ICSICT, pp. 1327 \u2013 1329, 2006.\r\n[17]\tA. Aarts, N. D'Halleweyn, and R. van Langevelde, \u201cA surfacepotential-based high-voltage compact LDMOS transistor model,\u201d IEEE Trans. Electron Devices, vol. 52, no. 5, pp. 999- 1007, 2005.\r\n[18]\tJ. C. W. Ng, and J. K. O. Sin, \u201cExtraction of the Inversion and Accumulation Layer Mobilities in n-Channel Trench DMOSFETs\u201d, IEEE Tran. Electron Devices, vol. 53, no. 8, pp. 1914 \u2013 1921, 2006.","publisher":"World Academy of Science, Engineering and Technology","index":"Open Science Index 126, 2017"}