Search results for: Montgomery multiplication

Authors: Rupali Verma, Maitreyee Dutta, Renu Vig

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Encryption and decryption in RSA are done by modular exponentiation which is achieved by repeated modular multiplication. Hence efficiency of modular multiplication directly determines the efficiency of RSA cryptosystem. This paper designs a Modified Montgomery Modular Multiplication in which addition of operands is computed by 4:2 compressor. The basic logic operations in addition are partitioned over two iterations such that parallel computations are performed. This reduces the critical path delay of proposed Montgomery design. The proposed design and RSA are implemented on Virtex 2 and Virtex 5 FPGAs. The two factors partitioning and parallelism have improved the frequency and throughput of proposed design.

Keywords: RSA, Montgomery modular multiplication, 4:2 compressor, FPGA.

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Authors: Ahmad M. Abdel Fattah, Ayman M. Bahaa El-Din, Hossam M.A. Fahmy

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Modular multiplication is the basic operation in most public key cryptosystems, such as RSA, DSA, ECC, and DH key exchange. Unfortunately, very large operands (in order of 1024 or 2048 bits) must be used to provide sufficient security strength. The use of such big numbers dramatically slows down the whole cipher system, especially when running on embedded processors. So far, customized hardware accelerators - developed on FPGAs or ASICs - were the best choice for accelerating modular multiplication in embedded environments. On the other hand, many algorithms have been developed to speed up such operations. Examples are the Montgomery modular multiplication and the interleaved modular multiplication algorithms. Combining both customized hardware with an efficient algorithm is expected to provide a much faster cipher system. This paper introduces an enhanced architecture for computing the modular multiplication of two large numbers X and Y modulo a given modulus M. The proposed design is compared with three previous architectures depending on carry save adders and look up tables. Look up tables should be loaded with a set of pre-computed values. Our proposed architecture uses the same carry save addition, but replaces both look up tables and pre-computations with an enhanced version of sign detection techniques. The proposed architecture supports higher frequencies than other architectures. It also has a better overall absolute time for a single operation.

Keywords: Montgomery multiplication, modular multiplication, efficient architecture, FPGA, RSA

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Authors: Hyun-Ho Lee, Kee-Won Kim

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The arithmetic operations over GF(2m) have been extensively used in error correcting codes and public-key cryptography schemes. Finite field arithmetic includes addition, multiplication, division and inversion operations. Addition is very simple and can be implemented with an extremely simple circuit. The other operations are much more complex. The multiplication is the most important for cryptosystems, such as the elliptic curve cryptosystem, since computing exponentiation, division, and computing multiplicative inverse can be performed by computing multiplication iteratively. In this paper, we present a parallel computation algorithm that operates Montgomery multiplication over finite field using redundant basis. Also, based on the multiplication algorithm, we present an efficient semi-systolic multiplier over finite field. The multiplier has less space and time complexities compared to related multipliers. As compared to the corresponding existing structures, the multiplier saves at least 5% area, 50% time, and 53% area-time (AT) complexity. Accordingly, it is well suited for VLSI implementation and can be easily applied as a basic component for computing complex operations over finite field, such as inversion and division operation.

Keywords: Finite field, Montgomery multiplication, systolic array, cryptography.

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Authors: Harpreet Singh Dhillon, Abhijit Mitra

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A reduced-bit multiplication algorithm based on the ancient Vedic multiplication formulae is proposed in this paper. Both the Vedic multiplication formulae, Urdhva tiryakbhyam and Nikhilam, are first discussed in detail. Urdhva tiryakbhyam, being a general multiplication formula, is equally applicable to all cases of multiplication. It is applied to the digital arithmetic and is shown to yield a multiplier architecture which is very similar to the popular array multiplier. Due to its structure, it leads to a high carry propagation delay in case of multiplication of large numbers. Nikhilam Sutra, on the other hand, is more efficient in the multiplication of large numbers as it reduces the multiplication of two large numbers to that of two smaller numbers. The framework of the proposed algorithm is taken from this Sutra and is further optimized by use of some general arithmetic operations such as expansion and bit-shifting to take advantage of bit-reduction in multiplication. We illustrate the proposed algorithm by reducing a general 4x4-bit multiplication to a single 2 x 2-bit multiplication operation.

Keywords: Multiplication, algorithm, Vedic mathematics, digital arithmetic, reduced-bit.

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Authors: Shunsuke Miyoshi, Yasuyuki Nogami, Takuya Kusaka, Nariyoshi Yamai

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Elliptic curve discrete logarithm problem(ECDLP) is one of problems on which the security of pairing-based cryptography is based. This paper considers Pollard’s rho method to evaluate the security of ECDLP on Barreto-Naehrig(BN) curve that is an efficient pairing-friendly curve. Some techniques are proposed to make the rho method efficient. Especially, the group structure on BN curve, distinguished point method, and Montgomery trick are well-known techniques. This paper applies these techniques and shows its optimization. According to the experimental results for which a large-scale parallel system with MySQL is applied, 94-bit ECDLP was solved about 28 hours by parallelizing 71 computers.

Keywords: Pollard’s rho method, BN curve, Montgomery multiplication.

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Authors: Manduth Ramchander

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Evaluating expressions involving multiplication and division can give rise to the fallacy that brackets can be arbitrarily inserted into expressions involving multiplication and division. The aim of this article was to draw upon mathematical theory to prove that brackets cannot be arbitrarily inserted into expressions involving multiplication and division and in particular in expressions where division precedes multiplication. In doing so, it demonstrates that the notion that two different answers are possible, when evaluating expressions involving multiplication and division, is indeed a false one. Searches conducted in a number of scholarly databases unearthed the rules to be applied when removing brackets from expressions, which revealed that consideration needs to be given to sign changes when brackets are removed. The rule pertaining to expressions involving multiplication and division was then extended upon, in its reverse format, to prove that brackets cannot be arbitrarily inserted into expressions involving multiplication and division. The application of the rule demonstrates that an expression involving multiplication and division can have only one correct answer. It is recommended that both the rule and its reverse be included in the curriculum, preferably at the juncture when manipulation with brackets is introduced.

Keywords: Brackets, multiplication, division, operations, order.

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Authors: Ridha Ghayoula, ElAmjed Hajlaoui, Talel Korkobi, Mbarek Traii, Hichem Trabelsi

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In this paper, the hardware implementation of the RSA public-key cryptographic algorithm is presented. The RSA cryptographic algorithm is depends on the computation of repeated modular exponentials. The Montgomery algorithm is used and modified to reduce hardware resources and to achieve reasonable operating speed for FPGA. An efficient architecture for modular multiplications based on the array multiplier is proposed. We have implemented a RSA cryptosystem based on Montgomery algorithm. As a result, it is shown that proposed architecture contributes to small area and reasonable speed.

Keywords: RSA, Cryptosystem, Montgomery, Implementation.FPGA.

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Authors: Raveen R. Goundar, Ken-ichi Shiota, Masahiko Toyonaga

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The major building block of most elliptic curve cryptosystems are computation of multi-scalar multiplication. This paper proposes a novel algorithm for simultaneous multi-scalar multiplication, that is by employing addition chains. The previously known methods utilizes double-and-add algorithm with binary representations. In order to accomplish our purpose, an efficient empirical method for finding addition chains for multi-exponents has been proposed.

Keywords: elliptic curve cryptosystems, multi-scalar multiplication, addition chains, Fibonacci sequence.

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Authors: P. Asadee

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Multiplication algorithms have considerable effect on processors performance. A new high-speed, low-power multiplication algorithm has been presented using modified Dadda tree structure. Three important modifications have been implemented in inner product generation step, inner product reduction step and final addition step. Optimized algorithms have to be used into basic computation components, such as multiplication algorithms. In this paper, we proposed a new algorithm to reduce power, delay, and transistor count of a multiplication algorithm implemented using low power modified counter. This work presents a novel design for Dadda multiplication algorithms. The proposed multiplication algorithm includes structured parts, which have important effect on inner product reduction tree. In this paper, a 1.3V, 64-bit carry hybrid adder is presented for fast, low voltage applications. The new 64-bit adder uses a new circuit to implement the proposed carry hybrid adder. The new adder using 80 nm CMOS technology has been implemented on 700 MHz clock frequency. The proposed multiplication algorithm has achieved 14 percent improvement in transistor count, 13 percent reduction in delay and 12 percent modification in power consumption in compared with conventional designs.

Keywords: adder, CMOS, counter, Dadda tree, encoder.

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Authors: Shiji Hu, Lei Li, Wanting Zhou, Daohong Yang

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The data encryption is the foundation of today’s communication. On this basis, to improve the speed of data encryption and decryption is always an important goal for high-speed applications. This paper proposed an elliptic curve crypto processor architecture based on SM2 prime field. Regarding hardware implementation, we optimized the algorithms in different stages of the structure. For modulo operation on finite field, we proposed an optimized improvement of the Karatsuba-Ofman multiplication algorithm and shortened the critical path through the pipeline structure in the algorithm implementation. Based on SM2 recommended prime field, a fast modular reduction algorithm is used to reduce 512-bit data obtained from the multiplication unit. The radix-4 extended Euclidean algorithm was used to realize the conversion between the affine coordinate system and the Jacobi projective coordinate system. In the parallel scheduling point operations on elliptic curves, we proposed a three-level parallel structure of point addition and point double based on the Jacobian projective coordinate system. Combined with the scalar multiplication algorithm, we added mutual pre-operation to the point addition and double point operation to improve the efficiency of the scalar point multiplication. The proposed ECC hardware architecture was verified and implemented on Xilinx Virtex-7 and ZYNQ-7 platforms, and each 256-bit scalar multiplication operation took 0.275ms. The performance for handling scalar multiplication is 32 times that of CPU (dual-core ARM Cortex-A9).

Keywords: Elliptic curve cryptosystems, SM2, modular multiplication, point multiplication.

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Authors: Massoud Masoumi, Hosseyn Mahdizadeh

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A new and highly efficient architecture for elliptic curve scalar point multiplication which is optimized for a binary field recommended by NIST and is well-suited for elliptic curve cryptographic (ECC) applications is presented. To achieve the maximum architectural and timing improvements we have reorganized and reordered the critical path of the Lopez-Dahab scalar point multiplication architecture such that logic structures are implemented in parallel and operations in the critical path are diverted to noncritical paths. With G=41, the proposed design is capable of performing a field multiplication over the extension field with degree 163 in 11.92 s with the maximum achievable frequency of 251 MHz on Xilinx Virtex-4 (XC4VLX200) while 22% of the chip area is occupied, where G is the digit size of the underlying digit-serial finite field multiplier.

Keywords: Elliptic curve cryptography, FPGA implementation, scalar point multiplication.

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Authors: Halil Snopce, Ilir Spahiu

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In this paper is investigated a possible optimization of some linear algebra problems which can be solved by parallel processing using the special arrays called systolic arrays. In this paper are used some special types of transformations for the designing of these arrays. We show the characteristics of these arrays. The main focus is on discussing the advantages of these arrays in parallel computation of matrix product, with special approach to the designing of systolic array for matrix multiplication. Multiplication of large matrices requires a lot of computational time and its complexity is O(n3 ). There are developed many algorithms (both sequential and parallel) with the purpose of minimizing the time of calculations. Systolic arrays are good suited for this purpose. In this paper we show that using an appropriate transformation implicates in finding more optimal arrays for doing the calculations of this type.

Keywords: Data dependences, matrix multiplication, systolicarray, transformation matrix.

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Authors: S. Jalaja, A. M. Vijaya Prakash

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Recursive combination of an algorithm based on Karatsuba multiplication is exploited to design a generalized transpose and parallel Finite Impulse Response (FIR) Filter. Mid-range Karatsuba multiplication and Carry Save adder based on Karatsuba multiplication reduce time complexity for higher order multiplication implemented up to n-bit. As a result, we design modified N-tap Transpose and Parallel Symmetric FIR Filter Structure using Karatsuba algorithm. The mathematical formulation of the FFA Filter is derived. The proposed architecture involves significantly less area delay product (APD) then the existing block implementation. By adopting retiming technique, hardware cost is reduced further. The filter architecture is designed by using 90 nm technology library and is implemented by using cadence EDA Tool. The synthesized result shows better performance for different word length and block size. The design achieves switching activity reduction and low power consumption by applying with and without retiming for different combination of the circuit. The proposed structure achieves more than a half of the power reduction by adopting with and without retiming techniques compared to the earlier design structure. As a proof of the concept for block size 16 and filter length 64 for CKA method, it achieves a 51% as well as 70% less power by applying retiming technique, and for CSA method it achieves a 57% as well as 77% less power by applying retiming technique compared to the previously proposed design.

Keywords: Carry save adder Karatsuba multiplication, mid-range Karatsuba multiplication, modified FFA, transposed filter, retiming.

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Authors: Muhammad Ridhuan Tony Lim Abdullah, Zulqarnain Abu Bakar, Razol Mahari Ali, Ibrahima Faye, Hilmi Hasan

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This paper describes a research project on Year 3 primary school students in Malaysia in their use of computer-based video game to enhance learning of multiplication facts (tables) in the Mathematics subject. This study attempts to investigate whether video games could actually contribute to positive effect on children-s learning or otherwise. In conducting this study, the researchers assume a neutral stand in the investigation as an unbiased outcome of the study would render reliable response to the impact of video games in education which would contribute to the literature of technology-based education as well as impact to the pedagogical aspect of formal education. In order to conduct the study, a subject (Mathematics) with a specific topic area in the subject (multiplication facts) is chosen. The study adopts a causal-comparative research to investigate the impact of the inclusion of a computer-based video game designed to teach multiplication facts to primary level students. Sample size is 100 students divided into two i.e., A: conventional group and B conventional group aided by video games. The conventional group (A) would be taught multiplication facts (timetables) and skills conventionally. The other group (B) underwent the same lessons but with supplementary activity: a computer-based video game on multiplication which is called Timez-Attack. Analysis of marks accrued from pre-test will be compared to post- test using comparisons of means, t tests, and ANOVA tests to investigate the impact of computer games as an added learning activity. The findings revealed that video games as a supplementary activity to classroom learning brings significant and positive effect on students- retention and mastery of multiplication tables as compared to students who rely only upon formal classroom instructions.

Keywords: Technology for education, Gaming for education, Computer-based video games, Cognitive learning

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Authors: Sharmila Karim, Haslinda Ibrahim, Zurni Omar

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In this paper, a new recursive strategy is proposed for determining $\frac{(n-1)!}{2}$ of $n$th order diagrams. The generalization of $n$th diagram for cross multiplication method were proposed by Pavlovic and Bankier but the specific rule of determining $\frac{(n-1)!}{2}$ of the $n$th order diagrams for square matrix is yet to be discovered. Thus using combinatorial approach, $\frac{(n-1)!}{2}$ of the $n$th order diagrams will be presented as $\frac{(n-1)!}{2}$ starter sets. These starter sets will be generated based on exchanging one element. The advantages of this new strategy are the discarding process was eliminated and the sign of starter set is alternated to each others.

Keywords: starter sets, permutation, exchanging one element, determinant

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Authors: Qiuyu Dai, Haochong Zhang, Xiangrong Liu

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Efficient matrix-vector multiplication with diagonal sparse matrices is pivotal in a multitude of computational domains, ranging from scientific simulations to machine learning workloads. When encoded in the conventional Diagonal (DIA) format, these matrices often induce computational overheads due to extensive zero-padding and non-linear memory accesses, which can hamper the computational throughput, and elevate the usage of precious compute and memory resources beyond necessity. The ’DIA-Adaptive’ approach, a methodological enhancement introduced in this paper, confronts these challenges head-on by leveraging the advanced parallel instruction sets embedded within Machine Learning Units (MLUs). This research presents a thorough analysis of the DIA-Adaptive scheme’s efficacy in optimizing Sparse Matrix-Vector Multiplication (SpMV) operations. The scope of the evaluation extends to a variety of hardware architectures, examining the repercussions of distinct thread allocation strategies and cluster configurations across multiple storage formats. A dedicated computational kernel, intrinsic to the DIA-Adaptive approach, has been meticulously developed to synchronize with the nuanced performance characteristics of MLUs. Empirical results, derived from rigorous experimentation, reveal that the DIA-Adaptive methodology not only diminishes the performance bottlenecks associated with the DIA format but also exhibits pronounced enhancements in execution speed and resource utilization. The analysis delineates a marked improvement in parallelism, showcasing the DIA-Adaptive scheme’s ability to adeptly manage the interplay between storage formats, hardware capabilities, and algorithmic design. The findings suggest that this approach could set a precedent for accelerating SpMV tasks, thereby contributing significantly to the broader domain of high-performance computing and data-intensive applications.

Keywords: Adaptive method, DIA, diagonal sparse matrices, MLU, sparse matrix-vector multiplication.

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Authors: Pratibha Gupta, Satyawati Sharma, Sanjay Saxena

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Stevia rebaudiana Bertoni (natural sweetener) belongs to Asteraceae family and can be used as substitute of artificial sweeteners for diabetic patients. Conventionally, it is cultivated by seeds or stem cutting, but seed viability rate is poor. A protocol for callus induction and multiplication was developed to produce large no. of calli in short period. Surface sterilized nodal, leaf and root explants were cultured on Murashige and Skoog (MS) medium with different concentrations of plant hormone like, IBA, kinetin, NAA, 2,4-D, and NAA in combination with 2,4-D. 100% callusing was observed from leaf explants cultured on combination of NAA and 2,4-D after three weeks while with 2,4-D, only 10% callusing was observed. Calli obtained from leaf and root explants were shiny green while with nodal explants it was hard and brown. The present findings deal with induction of callusing in Stevia to achieve the rapid callus multiplication for study of steviol glycosides in callus culture.

Keywords: 2, 4-D, Callusing, NAA, Stevia, Steviol glycosides

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Authors: T. Citarasu, M. Michaelbabu V. N. Vakharia

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The rhizome of Java grass, Cyperus rotundus was extracted different organic polar and non-polar solvents and performed the in vitro antiviral and immunostimulant activities against White Spot Syndrome Virus (WSSV) and Vibrio harveyi respectively. Based on the initial screening the ethyl acetate extract of C. rotundus was strong activities and further it was purified through silica column chromatography and the fractions were screened again for antiviral and immunostimulant activity. Among the different fractions screened against the WSSV and V. harveyi, the fractions, FIII to FV had strong activities. In order to study the in vivo influence of C. rotundus, the fractions (F-III to FV) were pooled and delivered to the F. indicus through artificial feed for 30 days. After the feeding trail the experimental and control diet fed F. indicus were challenged with virulent WSSV and studied the survival, molecular diagnosis, biochemical, haematological, and immunological parameters. Surprisingly, the pooled fractions (F-IV to FVI) incorporated diets helped to significantly (P<0.01) suppressed viral multiplication, showed significant (P<0.01) differences in protein and glucose levels, improved total haemocyte count (THC), coagulase activity, significantly increased (P <= 0.001) prophenol oxidase and intracellular superoxide anion production compared to the control shrimps. Based on the results, C. rotundus extracts effectively suppressed WSSV multiplication and improve the immune system in F. indicus against WSSV infection and this knowledge will helps to develop novel drugs from C. rotundus against WSSV.

Keywords: Antiviral drugs, Cyperus rotundus, Fenneropenaeus indicus, WSSV.

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Authors: M.Machhout, M.Zeghid, W.El hadj youssef, B.Bouallegue, A.Baganne, R.Tourki

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Long number multiplications (n ≥ 128-bit) are a primitive in most cryptosystems. They can be performed better by using Karatsuba-Ofman technique. This algorithm is easy to parallelize on workstation network and on distributed memory, and it-s known as the practical method of choice. Multiplying long numbers using Karatsuba-Ofman algorithm is fast but is highly recursive. In this paper, we propose different designs of implementing Karatsuba-Ofman multiplier. A mixture of sequential and combinational system design techniques involving pipelining is applied to our proposed designs. Multiplying large numbers can be adapted flexibly to time, area and power criteria. Computationally and occupation constrained in embedded systems such as: smart cards, mobile phones..., multiplication of finite field elements can be achieved more efficiently. The proposed designs are compared to other existing techniques. Mathematical models (Area (n), Delay (n)) of our proposed designs are also elaborated and evaluated on different FPGAs devices.

Keywords: finite field, Karatsuba-Ofman, long numbers, multiplication, mathematical model, recursivity.

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Authors: Chiou-Yng Lee, Wen-Yo Lee, Chieh-Tsai Wu, Cheng-Chen Yang

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Shifted polynomial basis (SPB) is a variation of polynomial basis representation. SPB has potential for efficient bit level and digi -level implementations of multiplication over binary extension fields with subquadratic space complexity. For efficient implementation of pairing computation with large finite fields, this paper presents a new SPB multiplication algorithm based on Karatsuba schemes, and used that to derive a novel scalable multiplier architecture. Analytical results show that the proposed multiplier provides a trade-off between space and time complexities. Our proposed multiplier is modular, regular, and suitable for very large scale integration (VLSI) implementations. It involves less area complexity compared to the multipliers based on traditional decomposition methods. It is therefore, more suitable for efficient hardware implementation of pairing based cryptography and elliptic curve cryptography (ECC) in constraint driven applications.

Keywords: Digit-serial systolic multiplier, elliptic curve cryptography (ECC), Karatsuba algorithm (KA), shifted polynomial basis (SPB), pairing computation.

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Authors: R. Varalakshmi

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For the last decade, researchers have started to focus their interest on Multicast Group Key Management Framework. The central research challenge is secure and efficient group key distribution. The present paper is based on the Bit model based Secure Multicast Group key distribution scheme using the most popular absolute encoder output type code named Gray Code. The focus is of two folds. The first fold deals with the reduction of computation complexity which is achieved in our scheme by performing fewer multiplication operations during the key updating process. To optimize the number of multiplication operations, an O(1) time algorithm to multiply two N-bit binary numbers which could be used in an N x N bit-model of reconfigurable mesh is used in this proposed work. The second fold aims at reducing the amount of information stored in the Group Center and group members while performing the update operation in the key content. Comparative analysis to illustrate the performance of various key distribution schemes is shown in this paper and it has been observed that this proposed algorithm reduces the computation and storage complexity significantly. Our proposed algorithm is suitable for high performance computing environment.

Keywords: Multicast Group key distribution, Bit model, Integer Multiplications, reconfigurable mesh, optimal algorithm, Gray Code, Computation Complexity, Storage Complexity.

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Authors: Jaeyoung Lee

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Autonomous driving systems require high reliability to provide people with a safe and comfortable driving experience. However, despite the development of a number of vehicle sensors, it is difficult to always provide high perceived performance in driving environments that vary from time to season. The image segmentation method using deep learning, which has recently evolved rapidly, provides high recognition performance in various road environments stably. However, since the system controls a vehicle in real time, a highly complex deep learning network cannot be used due to time and memory constraints. Moreover, efficient networks are optimized for GPU environments, which degrade performance in embedded processor environments equipped simple hardware accelerators. In this paper, a semantic segmentation network, matrix multiplication accelerator network (MMANet), optimized for matrix multiplication accelerator (MMA) on Texas instrument digital signal processors (TI DSP) is proposed to improve the recognition performance of autonomous driving system. The proposed method is designed to maximize the number of layers that can be performed in a limited time to provide reliable driving environment information in real time. First, the number of channels in the activation map is fixed to fit the structure of MMA. By increasing the number of parallel branches, the lack of information caused by fixing the number of channels is resolved. Second, an efficient convolution is selected depending on the size of the activation. Since MMA is a fixed, it may be more efficient for normal convolution than depthwise separable convolution depending on memory access overhead. Thus, a convolution type is decided according to output stride to increase network depth. In addition, memory access time is minimized by processing operations only in L3 cache. Lastly, reliable contexts are extracted using the extended atrous spatial pyramid pooling (ASPP). The suggested method gets stable features from an extended path by increasing the kernel size and accessing consecutive data. In addition, it consists of two ASPPs to obtain high quality contexts using the restored shape without global average pooling paths since the layer uses MMA as a simple adder. To verify the proposed method, an experiment is conducted using perfsim, a timing simulator, and the Cityscapes validation sets. The proposed network can process an image with 640 x 480 resolution for 6.67 ms, so six cameras can be used to identify the surroundings of the vehicle as 20 frame per second (FPS). In addition, it achieves 73.1% mean intersection over union (mIoU) which is the highest recognition rate among embedded networks on the Cityscapes validation set.

Keywords: Edge network, embedded network, MMA, matrix multiplication accelerator and semantic segmentation network.

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Authors: S. Gharbi, S. Labidi, M. Mars, M. Chelli, F. Ladeb

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The purpose of this study is to reduce radiation dose for chest CT examination by including Tube Current Modulation (TCM) to a standard CT protocol. A scan of an anthropomorphic male Alderson phantom was performed on a 128-slice scanner. The estimation of effective dose (ED) in both scans with and without mAs modulation was done via multiplication of Dose Length Product (DLP) to a conversion factor. Results were compared to those measured with a CT-Expo software. The size specific dose estimation (SSDE) values were obtained by multiplication of the volume CT dose index (CTDIvol) with a conversion size factor related to the phantom’s effective diameter. Objective assessment of image quality was performed with Signal to Noise Ratio (SNR) measurements in phantom. SPSS software was used for data analysis. Results showed including CARE Dose 4D; ED was lowered by 48.35% and 51.51% using DLP and CT-expo, respectively. In addition, ED ranges between 7.01 mSv and 6.6 mSv in case of standard protocol, while it ranges between 3.62 mSv and 3.2 mSv with TCM. Similar results are found for SSDE; dose was higher without TCM of 16.25 mGy and was lower by 48.8% including TCM. The SNR values calculated were significantly different (p=0.03<0.05). The highest one is measured on images acquired with TCM and reconstructed with Filtered back projection (FBP). In conclusion, this study proves the potential of TCM technique in SSDE and ED reduction and in conserving image quality with high diagnostic reference level for thoracic CT examinations.

Keywords: Anthropomorphic phantom, computed tomography, CT-expo, radiation dose.

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Authors: S. C. Arora, Ritu Kathuria

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A slant weighted Toeplitz operator Aφ is an operator on L2(β) defined as Aφ = WMφ where Mφ is the weighted multiplication operator and W is an operator on L2(β) given by We2n = βn β2n en, {en}n∈Z being the orthonormal basis. In this paper, we generalise Aφ to the k-th order slant weighted Toeplitz operator Uφ and study its properties.

Keywords: Slant weighted Toeplitz operator, weighted multiplicationoperator.

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Authors: T. Punjansing, M. Nakkuntod, S. Homchan, P. Inthima, A. Kongbangkerd

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The influence of organic supplements on growth and multiplication efficiency of Phaius tankervilleae var. alba seedlings was investigated. 12 week-old seedlings were cultured on half-strength semi-solid Murashige and Skoog (MS) medium supplemented with 30 g/L sucrose, 8 g/L agar and various concentrations of coconut water (0, 50, 100, 150 and 200 mL/L) combined with potato extract (0, 25 and 50 g/L) and the pH was adjusted to 5.8 prior to autoclaving. The cultures were then kept under constant photoperiod (16 h light: 8 h dark) at 25 ± 2 °C for 12 weeks. The highest number of shoots (3.0 shoots/explant) was obtained when cultured on the medium added with 50 ml/L coconut water and 50 g/L potato extract whereas the highest number of leaves (5.9 leaves/explant) and roots (6.1 roots/explant) could receive on the medium supplemented with 150 ml/L coconut water and 50 g/L potato extract. with 150 ml/L coconut water and 50 g/L potato extract. Additionally, plantlets of P. tankervilleae var. alba were transferred to grow into seven different substrates i.e. soil, sand, coconut husk chip, soil-sand mix (1: 1), soil-coconut husk chip mix (1: 1), sand-coconut husk chip mix (1: 1) and soil-sand-coconut husk chip mix (1: 1: 1) for four weeks. The results found that acclimatized plants showed 100% of survivals when sand, coconut husk chip and sand-coconut husk chip mix are used as substrates. The number of leaves induced by sand-coconut husk chip mix was significantly higher than that planted in other substrates (P > 0.05). Meanwhile, no significant difference in new shoot formation among these substrates was observed (P < 0.05). This precursory developing protocol was likely to be applied for more large scale of plant production as well as conservation of germplasm of this orchid species.

Keywords: Acclimatization, coconut water, orchid, Phaius tankervilleae var. alba., potato extract.

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Authors: Hajji Lobna, Chattaoui Mayssa, Regaieg Hajer, M'Hamdi-Boughalleb Naima, Rhouma Ali, Horrigue-Raouani Najet

Abstract:

In this study, three local isolates of Trichoderma (Tr1: T. viride, Tr2: T. harzianum and Tr3: T. asperellum) were isolated and evaluated for their biocontrol effectiveness under in vitro conditions and in greenhouse. In vitro bioassay revealed a biopotential control against Fusarium oxysporum f. sp. radicis lycopersici and Meloidogyne javanica (RKN) separately. All species of Trichoderma exhibited biocontrol performance and (Tr1) Trichoderma viride was the most efficient. In fact, growth rate inhibition of Fusarium oxysporum f. sp. radicis lycopersici (FORL) was reached 75.5% with Tr1. Parasitism rate of root-knot nematode was 60% for juveniles and 75% for eggs with the same one. Pots experiment results showed that Tr1 and Tr2, compared to chemical treatment, enhanced the plant growth and exhibited better antagonism against root-knot nematode and root-rot fungi separated or combined. All Trichoderma isolates revealed a bioprotection potential against Fusarium oxysporum f. sp. radicis lycopersici. When pathogen fungi inoculated alone, Fusarium wilt index and browning vascular rate were reduced significantly with Tr1 (0.91, 2.38%) and Tr2 (1.5, 5.5%), respectively. In the case of combined infection with Fusarium and nematode, the same isolate of Trichoderma Tr1 and Tr2 decreased Fusarium wilt index at 1.1 and 0.83 and reduced the browning vascular rate at 6.5% and 6%, respectively. Similarly, the isolate Tr1 and Tr2 caused maximum inhibition of nematode multiplication. Multiplication rate was declined at 4% with both isolates either tomato infected by nematode separately or concomitantly with Fusarium. The chemical treatment was moderate in activity against Meloidogyne javanica and Fusarium oxysporum f. sp. radicis lycopersici alone and combined.

Keywords: Trichoderma spp., Meloidogyne javanica, Fusarium oxysporum f.sp. radicis lycopersici, biocontrol.

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Authors: V.K.Ananthashayana, Geetha.K.S

Abstract:

In this paper, a recursive algorithm for the computation of 2-D DCT using Ramanujan Numbers is proposed. With this algorithm, the floating-point multiplication is completely eliminated and hence the multiplierless algorithm can be implemented using shifts and additions only. The orthogonality of the recursive kernel is well maintained through matrix factorization to reduce the computational complexity. The inherent parallel structure yields simpler programming and hardware implementation and provides log 1 2 3 2 N N-N+ additions and N N 2 log 2 shifts which is very much less complex when compared to other recent multiplierless algorithms.

Keywords: DCT, Multilplerless, Ramanujan Number, Recursive.

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Authors: Shinoj T. K, Sunil Jacob John

Abstract:

In this paper a new concept named Intuitionistic Fuzzy Multiset is introduced. The basic operations on Intuitionistic Fuzzy Multisets such as union, intersection, addition, multiplication etc. are discussed. An application of Intuitionistic Fuzzy Multiset in Medical diagnosis problem using a distance function is discussed in detail.

Keywords: Intuitionistic Fuzzy set, Multiset, Intuitionistic Fuzzy Multiset

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Authors: Leonardo Herrera, Shield B. Lin, Stephen J. Montgomery-Smith, Ziraguen O. Williams

Abstract:

A one-directional dynamic model of a Stewart Platform was developed to assist NASA in analyzing the dynamic response in spacecraft docking operations. A simplified mechanical drawing was created, capturing the physical structure's main features. A simplified schematic diagram was developed into a lumped mass model from the mechanical drawing. Three differential equations were derived according to the schematic diagram. A Simulink diagram was created using MATLAB to represent the three equations. System parameters, including spring constants and masses, are derived in detail from the physical system. The model can be used for further analysis via computer simulation in predicting dynamic response in its main docking direction, i.e., up-and-down motion.

Keywords: Stewart platform, docking operation, spacecraft, spring constant.

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Authors: Rekha V. Dundur , M.V.Latte, S.Y. Kulkarni, M.K.Venkatesha

Abstract:

The advent of multi-million gate Field Programmable Gate Arrays (FPGAs) with hardware support for multiplication opens an opportunity to recreate a significant portion of the front end of a human cochlea using this technology. In this paper we describe the implementation of the cochlear filter and show that it is entirely suited to a single device XC3S500 FPGA implementation .The filter gave a good fit to real time data with efficiency of hardware usage.

Keywords: Cochlea, FPGA, IIR (Infinite Impulse Response), Multiplier.

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