**Commenced**in January 2007

**Frequency:**Monthly

**Edition:**International

**Paper Count:**30174

##### An Efficient Architecture for Interleaved Modular Multiplication

**Authors:**
Ahmad M. Abdel Fattah,
Ayman M. Bahaa El-Din,
Hossam M.A. Fahmy

**Abstract:**

**Keywords:**
Montgomery multiplication,
modular multiplication,
efficient architecture,
FPGA,
RSA

**Digital Object Identifier (DOI):**
doi.org/10.5281/zenodo.1057273

**References:**

[1] Peter L. Montgomery, "Modular multiplication without trial division," in Mathematics of Computation. April 1985, vol. 44, pp. 519-521, American Mathematical Society.

[2] G. R. Blakley, "A computer algorithm for the product AB modulo M," IEEE Transactions on Computers, pp. 497 - 500, May 1983.

[3] D. Narh Amanor, C. Paar, J. Pelzl, V. Bunimov, and M. Schimmler, "Efficient hardware architectures for modular multiplication on FPGAs," International Conference on Field Programmable Logic and Applications, pp. 539-542, 2005.

[4] V. Bunimov and M. Schimmler, "Area and time efficient modular multiplication of large integers," in IEEE 14th International Conference on Application specific Systems, Architectures and Processors, June 2003.

[5] Q.K. Kop and C.Y. Hung, "Fast algorithm for modular reduction," in IEE Proceedings, Computers and Digital Techniques, July 1998, vol. 145, pp. 265-271.

[6] David Narh Amanor, "Efficient hardware architectures for modular multiplication," M.S. thesis, University of Applied Sciences Offenburg, Germany, February 2005.