Search results for: Hardware in Loop

Authors: Nagulapati Kiran, V. Rangavalli, B. Vanajakshi

Abstract:

This paper designs the four-phase Boost Converter which overcomes the problem of high input ripple current and output ripple voltage. Digital control is more convenient for such a topology on basis of synchronization, phase shift operation, etc. Simulation results are presented for open-loop and closed-loop for four phase boost converter. This control scheme is applicable for PFC rectifiers as well. Thus a comparative analysis based on the obtained results is performed.

Keywords: Boost Converter, Bode plot, PI Controller, Four phase.

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Authors: Truong Nguyen Luan Vu, Le Hieu Giang, Le Linh

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The fractional–order proportional integral (FOPI) controller tuning rules based on the fractional calculus for the cascade control system are systematically proposed in this paper. Accordingly, the ideal controller is obtained by using internal model control (IMC) approach for both the inner and outer loops, which gives the desired closed-loop responses. On the basis of the fractional calculus, the analytical tuning rules of FOPI controller for the inner loop can be established in the frequency domain. Besides, the outer loop is tuned by using any integer PI/PID controller tuning rules in the literature. The simulation study is considered for the stable process model and the results demonstrate the simplicity, flexibility, and effectiveness of the proposed method for the cascade control system in compared with the other methods.

Keywords: Fractional calculus, fractional–order proportional integral controller, cascade control system, internal model control approach.

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Authors: R .H. Talwekar, S. S Limaye

Abstract:

The designing of charge pump with high gain Op- Amp is a challenging task for getting faithful response .Design of high performance phase locked loop require ,a design of high performance charge pump .We have designed a operational amplifier for reducing the error caused by high speed glitch in a transistor and mismatch currents . A separate Op-Amp has designed in 180 nm CMOS technology by CADENCE VIRTUOSO tool. This paper describes the design of high performance charge pump for GHz CMOS PLL targeting orthogonal frequency division multiplexing (OFDM) application. A high speed low power consumption Op-Amp with more than 500 MHz bandwidth has designed for increasing the speed of charge pump in Phase locked loop.

Keywords: Charge pump (CP) Orthogonal frequency divisionmultiplexing (OFDM), Phase locked loop (PLL), Phase frequencydetector (PFD), Voltage controlled oscillator (VCO),

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Authors: H. Asiaban, E. Farshidi

Abstract:

This paper presents a new true RMS-to-DC converter circuit based on a square-root-domain squarer/divider. The circuit is designed by employing up-down translinear loop and using of MOSFET transistors that operate in strong inversion saturation region. The converter offer advantages of two-quadrant input current, low circuit complexity, low supply voltage (1.2V) and immunity from the body effect. The circuit has been simulated by HSPICE. The simulation results are seen to conform to the theoretical analysis and shows benefits of the proposed circuit.

Keywords: Current-mode, squarer/divider, low-pass filter, converter, translinear loop, RMS-to-DC.

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Authors: Niti Kammuang-lue, Kritsada On-ai, Phrut Sakulchangsatjatai, Pradit Terdtoon

Abstract:

The objectives of this paper are to investigate effects of dimensionless numbers on thermal performance of the vertical closed-loop pulsating heat pipe (VCLPHP) and to establish a correlation to predict the thermal performance of the VCLPHP. The CLPHPs were made of long copper capillary tubes with inner diameters of 1.50, 1.78, and 2.16mm and bent into 26 turns. Then, both ends were connected together to form a loop. The evaporator, adiabatic, and condenser sections length were equal to 50 and 150 mm. R123, R141b, acetone, ethanol, and water were chosen as variable working fluids with constant filling ratio of 50% by total volume. Inlet temperature of heating medium and adiabatic section temperature was constantly controlled at 80 and 50^oC, respectively. Thermal performance was represented in a term of Kutateladze number (Ku). It can be concluded that when Prandtl number of liquid working fluid (Pr_l), and Karman number (Ka) increases, thermal performance increases. On contrary, when Bond number (Bo), Jacob number (Ja), and Aspect ratio (L_e/D_i) increases, thermal performance decreases. Moreover, the correlation to predict more precise thermal performance has been successfully established by analyzing on all dimensionless numbers that have effect on the thermal performance of the VCLPHP.

Keywords: Vertical closed-loop pulsating heat pipe, working fluid, thermal performance, dimensionless parameter.

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Authors: M.H.Ghaffari

Abstract:

A theoretical study is conducted to design and explore the effect of different parameters such as heat loads, the tube size of piping system, wick thickness, porosity and hole size on the performance and capability of a Loop Heat Pipe(LHP). This paper presents a steady state model that describes the different phenomena inside a LHP. Loop Heat Pipes(LHPs) are two-phase heat transfer devices with capillary pumping of a working fluid. By their original design comparing with heat pipes and special properties of the capillary structure, they-re capable of transferring heat efficiency for distances up to several meters at any orientation in the gravity field, or to several meters in a horizontal position. This theoretical model is described by different relations to satisfy important limits such as capillary and nucleate boiling. An algorithm is developed to predict the size of the LHP satisfying the limitations mentioned above for a wide range of applied loads. Finally, to assess and evaluate the algorithm and all the relations considered, we have used to design a new kind of LHP to recover the heat from the exhaust of an actual Gas Turbine. By finding the results, it showed that we can use the LHP as a very high efficient device to recover the heat even in high amount of loads(exhaust of a gas turbine). The sizes of all parts of the LHP were obtained using the developed algorithm.

Keywords: Loop Heat Pipe, Head Load, Liquid-Vapor Interface, Heat Transfer, Design Algorithm

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Authors: Peng Shen Ong, Yoong Choon Chang, Chee Pun Ooi, Ettikan K. Karuppiah, Shahirina Mohd Tahir

Abstract:

Falling has been one of the major concerns and threats to the independence of the elderly in their daily lives. With the worldwide significant growth of the aging population, it is essential to have a promising solution of fall detection which is able to operate at high accuracy in real-time and supports large scale implementation using multiple cameras. Field Programmable Gate Array (FPGA) is a highly promising tool to be used as a hardware accelerator in many emerging embedded vision based system. Thus, it is the main objective of this paper to present an FPGA-based solution of visual based fall detection to meet stringent real-time requirements with high accuracy. The hardware architecture of visual based fall detection which utilizes the pixel locality to reduce memory accesses is proposed. By exploiting the parallel and pipeline architecture of FPGA, our hardware implementation of visual based fall detection using FGPA is able to achieve a performance of 60fps for a series of video analytical functions at VGA resolutions (640x480). The results of this work show that FPGA has great potentials and impacts in enabling large scale vision system in the future healthcare industry due to its flexibility and scalability.

Keywords: Fall detection, FPGA, hardware implementation.

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Authors: P. Gunnasegaran, M. Z. Abdullah, M. Z. Yusoff, Nur Irmawati

Abstract:

This study presents experimental and optimization of nanoparticle mass concentration and heat input based on the total thermal resistance (Rth) of loop heat pipe (LHP), employed for PCCPU cooling. In this study, silica nanoparticles (SiO2) in water with particle mass concentration ranged from 0% (pure water) to 1% is considered as the working fluid within the LHP. The experimental design and optimization is accomplished by the design of experimental tool, Response Surface Methodology (RSM). The results show that the nanoparticle mass concentration and the heat input have significant effect on the Rth of LHP. For a given heat input, the Rth is found to decrease with the increase of the nanoparticle mass concentration up to 0.5% and increased thereafter. It is also found that the Rth is decreased when the heat input is increased from 20W to 60W. The results are optimized with the objective of minimizing the Rth, using Design-Expert software, and the optimized nanoparticle mass concentration and heat input are 0.48% and 59.97W, respectively, the minimum thermal resistance being 2.66 (ºC/W).

Keywords: Loop heat pipe, nanofluid, optimization, thermal resistance.

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Authors: Rekha V. Dundur , M.V.Latte, S.Y. Kulkarni, M.K.Venkatesha

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The advent of multi-million gate Field Programmable Gate Arrays (FPGAs) with hardware support for multiplication opens an opportunity to recreate a significant portion of the front end of a human cochlea using this technology. In this paper we describe the implementation of the cochlear filter and show that it is entirely suited to a single device XC3S500 FPGA implementation .The filter gave a good fit to real time data with efficiency of hardware usage.

Keywords: Cochlea, FPGA, IIR (Infinite Impulse Response), Multiplier.

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Authors: R. Damaševičius

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System-level design based on high-level abstractions is becoming increasingly important in hardware and embedded system design. This paper analyzes meta-design techniques oriented at developing meta-programs and meta-models for well-understood domains. Meta-design techniques include meta-programming and meta-modeling. At the programming level of design process, metadesign means developing generic components that are usable in a wider context of application than original domain components. At the modeling level, meta-design means developing design patterns that describe general solutions to the common recurring design problems, and meta-models that describe the relationship between different types of design models and abstractions. The paper describes and evaluates the implementation of meta-design in hardware design domain using object-oriented and meta-programming techniques. The presented ideas are illustrated with a case study.

Keywords: Design patterns, meta-design, meta-modeling, metaprogramming.

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Authors: Iyad F. Jafar, Sandra J. Alrawashdeh, Ban K. Alhamayel

Abstract:

High level synthesis (HLS) is a process which generates register-transfer level design for digital systems from behavioral description. There are many HLS algorithms and commercial tools. However, most of these algorithms consider a behavioral description for the system when a single token is presented to the system. This approach does not exploit extra hardware efficiently, especially in the design of digital filters where common operations may exist between successive tokens. In this paper, we modify the behavioral description to process multiple tokens in parallel. However, this approach is unlike the full processing that requires full hardware replication. It exploits the presence of common operations between successive tokens. The performance of the proposed approach is better than sequential processing and approaches that of full parallel processing as the hardware resources are increased.

Keywords: Digital filters, High level synthesis, Sub-token forwarding

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Authors: Yuekun Chen, Yousef Sardahi, Salam Hajjar, Christopher Greer

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This paper presents a multi-objective optimal design of a cascade control system for an underactuated mechanical system. Cascade control structures usually include two control algorithms (inner and outer). To design such a control system properly, the following conflicting objectives should be considered at the same time: 1) the inner closed-loop control must be faster than the outer one, 2) the inner loop should fast reject any disturbance and prevent it from propagating to the outer loop, 3) the controlled system should be insensitive to measurement noise, and 4) the controlled system should be driven by optimal energy. Such a control problem can be formulated as a multi-objective optimization problem such that the optimal trade-offs among these design goals are found. To authors best knowledge, such a problem has not been studied in multi-objective settings so far. In this work, an underactuated mechanical system consisting of a rotary servo motor and a ball and beam is used for the computer simulations, the setup parameters of the inner and outer control systems are tuned by NSGA-II (Non-dominated Sorting Genetic Algorithm), and the dominancy concept is used to find the optimal design points. The solution of this problem is not a single optimal cascade control, but rather a set of optimal cascade controllers (called Pareto set) which represent the optimal trade-offs among the selected design criteria. The function evaluation of the Pareto set is called the Pareto front. The solution set is introduced to the decision-maker who can choose any point to implement. The simulation results in terms of Pareto front and time responses to external signals show the competing nature among the design objectives. The presented study may become the basis for multi-objective optimal design of multi-loop control systems.

Keywords: Cascade control, multi-loop control systems, multi-objective optimization, optimal control.

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Authors: Ali Shatnawi

Abstract:

Signal processing applications which are iterative in nature are best represented by data flow graphs (DFG). In these applications, the maximum sampling frequency is dependent on the topology of the DFG, the cyclic dependencies in particular. The determination of the iteration bound, which is the reciprocal of the maximum sampling frequency, is critical in the process of hardware implementation of signal processing applications. In this paper, a novel technique to compute the iteration bound is proposed. This technique is different from all previously proposed techniques, in the sense that it is based on the natural flow of tokens into the DFG rather than the topology of the graph. The proposed algorithm has lower run-time complexity than all known algorithms. The performance of the proposed algorithm is illustrated through analytical analysis of the time complexity, as well as through simulation of some benchmark problems.

Keywords: Data flow graph, Iteration period bound, Rateoptimalscheduling, Recursive DSP algorithms.

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Authors: Lari Kela

Abstract:

An adaptive Helmholtz resonator was designed and adapted to hydraulics. The resonator was controlled by open- and closed-loop controls so that 20 dB attenuation of the peak-to-peak value of the pulsating pressure was maintained. The closed-loop control was noted to be better, albeit it was slower because of its low pressure and temperature variation, which caused variation in the effective bulk modulus of the hydraulic system. Low-pressure hydraulics contains air, which affects the stiffness of the hydraulics, and temperature variation changes the viscosity of the oil. Thus, an open-loop control loses its efficiency if a condition such as temperature or the amount of air changes after calibration. The instability of the low-pressure hydraulic system reduced the operational frequency range of the Helmholtz resonator when compared with the results of an analytical model. Different dampers for hydraulics are presented. Then analytical models of a hydraulic pipe and a hydraulic pipe with a Helmholtz resonator are presented. The analytical models are based on the wave equation of sound pressure. Finally, control methods and the results of experiments are presented.

Keywords: adaptive, damper, hydraulics, pressure, pulsating

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Authors: Mahdi Yaghobi, Mohammad Haeri

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In this paper, we show that the stability can not be achieved with current stabilizing MPC methods for some unstable processes. Hence we present a new method for stabilizing these processes. The main idea is to use a new time varying weighted cost function for traditional GPC. This stabilizes the closed loop system without adding soft or hard constraint in optimization problem. By studying different examples it is shown that using the proposed method, the closed-loop stability of unstable nonminimum phase process is achieved.

Keywords: GPC, Stability, Varying Weighting Coefficients.

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Authors: Cyrille Lambert, Tatiana Kalganova, Emanuele Stomeo

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Since 1992, year where Hugo de Garis has published the first paper on Evolvable Hardware (EHW), a period of intense creativity has followed. It has been actively researched, developed and applied to various problems. Different approaches have been proposed that created three main classifications: extrinsic, mixtrinsic and intrinsic EHW. Each of these solutions has a real interest. Nevertheless, although the extrinsic evolution generates some excellent results, the intrinsic systems are not so advanced. This paper suggests 3 possible solutions to implement the run-time configuration intrinsic EHW system: FPGA-based Run-Time Configuration system, JBits-based Run-Time Configuration system and Multi-board functional-level Run-Time Configuration system. The main characteristic of the proposed architectures is that they are implemented on Field Programmable Gate Array. A comparison of proposed solutions demonstrates that multi-board functional-level run-time configuration is superior in terms of scalability, flexibility and the implementation easiness.

Keywords: Evolvable hardware, evolutionary computation, FPGA systems.

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Authors: Konstantin Movsovic, Emanuele Stomeo, Tatiana Kalganova

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The evolutionary design of electronic circuits, or evolvable hardware, is a discipline that allows the user to automatically obtain the desired circuit design. The circuit configuration is under the control of evolutionary algorithms. Several researchers have used evolvable hardware to design electrical circuits. Every time that one particular algorithm is selected to carry out the evolution, it is necessary that all its parameters, such as mutation rate, population size, selection mechanisms etc. are tuned in order to achieve the best results during the evolution process. This paper investigates the abilities of evolution strategy to evolve digital logic circuits based on programmable logic array structures when different mutation rates are used. Several mutation rates (fixed and variable) are analyzed and compared with each other to outline the most appropriate choice to be used during the evolution of combinational logic circuits. The experimental results outlined in this paper are important as they could be used by every researcher who might need to use the evolutionary algorithm to design digital logic circuits.

Keywords: Evolvable hardware, evolutionary algorithm, digitallogic circuit, mutation rate.

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Authors: Iqbalur Rahman, Miftahur Rahman, Abul L Haque, Mostafizur Rahman,

Abstract:

In this paper, RSA encryption algorithm and its hardware implementation in Xilinx-s Virtex Field Programmable Gate Arrays (FPGA) is analyzed. The issues of scalability, flexible performance, and silicon efficiency for the hardware acceleration of public key crypto systems are being explored in the present work. Using techniques based on the interleaved math for exponentiation, the proposed RSA calculation architecture is compared to existing FPGA-based solutions for speed, FPGA utilization, and scalability. The paper covers the RSA encryption algorithm, interleaved multiplication, Miller Rabin algorithm for primality test, extended Euclidean math, basic FPGA technology, and the implementation details of the proposed RSA calculation architecture. Performance of several alternative hardware architectures is discussed and compared. Finally, conclusion is drawn, highlighting the advantages of a fully flexible & parameterized design.

Keywords: Crypto Accelerator, FPGA, Public Key Cryptography, RSA.

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Authors: Rawad Asfour, Salam Khamas, Edward A. Ball

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This paper is focused on the design of an mm-wave phased array. To date, linear polarization is adapted in the reported designs of phased arrays. However, linear polarization faces several well-known challenges. As such, an advanced design for phased array antennas is required that offers circularly polarized (CP) radiation. A feasible solution for achieving CP phased array antennas is proposed using open-circular loop antennas. To this end, a 3-element circular loop phased array antenna is designed to operate at 28 GHz. In addition, the array ability to control the direction of the main lobe is investigated. The results show that the highest achievable field of view (FOV) is 100°, i.e. 50° to the left and 50° to the right-hand side directions. The results are achieved with a CP bandwidth of 15%. Furthermore, the results demonstrate that a high broadside gain of circa 11 dBi can be achieved for the steered beam. Besides, radiation efficiency of 97% can also be achieved based on the proposed design.

Keywords: loop antenna, phased array, beam steering, wide bandwidth, circular polarization, CST

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Authors: Sung Kyu Kim, Yong Soo Kim

Abstract:

Safety instrumented systems (SISs) are becoming increasingly complex and the proportion of programmable electronic parts is growing. The IEC 61508 global standard was established to ensure the functional safety of SISs, but it was expressed in highly macroscopic terms. This study introduces an evaluation process for hardware safety integrity levels through failure modes, effects, and diagnostic analysis (FMEDA).FMEDA is widely used to evaluate safety levels, and it provides the information on failure rates and failure mode distributions necessary to calculate a diagnostic coverage factor for a given component. In our evaluation process, the components of the SIS subsystem are first defined in terms of failure modes and effects. Then, the failure rate and failure mechanism distribution are assigned to each component. The safety mode and detectability of each failure mode are determined for each component. Finally, the hardware safety integrity level is evaluated based on the calculated results.

Keywords: Safety instrumented system; Safety integrity level; Failure modes, effects, and diagnostic analysis; IEC 61508.

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Authors: F. Esmaeilzadeh, Y. Fayazi, J. Fathikaljahi

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Gas hydrates form when a number of factors co-exist: free water, hydrocarbon gas, cold temperatures and high pressures are typical of the near mud-line conditions in a deepwater drilling operation. Subsequently, when drilling with water based muds, particularly on exploration wells, the risk of hydrate formation associated with a gas influx is high. The consequences of gas hydrate formation while drilling are severe, and as such, every effort should be made to ensure the risk of hydrate formation is either eliminated or significantly reduced. Thermodynamic inhibitors are used to reduce the free water content of a drilling mud, and thus suppress the hydrate formation temperature. Very little experimental work has been performed by oil and gas research companies on the evaluation of gas hydrate formation in a water-based drilling mud. The main objective of this paper is to investigate the experimental gas hydrate formation for a mixture of methane, carbon dioxide & nitrogen in a water-based drilling mud with or without presence of different concentrations of thermodynamic inhibitors including pure salt and a combination of salt with methanol or ethylene glycol at different concentrations in a static loop apparatus. The experiments were performed using a static loop apparatus consisting of a 2.4307 cm inside diameter and 800 cm long pipe. All experiments were conducted at 2200 psia. The temperature in the loop was decreased at a rate of 3.33 °F/h from initial temperature of 80 °F.

Keywords: Hydrate formation, thermodynamic inhibitor, waterbaseddrilling mud, salt, static loop apparatus.

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Authors: May Phyo Thwal, Khin Htay Kyi, Kyaw Swar Soe

Abstract:

According to the density of the chips, designers are trying to put so any facilities of computational and storage on single chips. Along with the complexity of computational and storage circuits, the designing, testing and debugging become more and more complex and expensive. So, hardware design will be built by using very high speed hardware description language, which is more efficient and cost effective. This paper will focus on the implementation of 32-bit ALU design based on Verilog hardware description language. Adder and subtracter operate correctly on both unsigned and positive numbers. In ALU, addition takes most of the time if it uses the ripple-carry adder. The general strategy for designing fast adders is to reduce the time required to form carry signals. Adders that use this principle are called carry look- ahead adder. The carry look-ahead adder is to be designed with combination of 4-bit adders. The syntax of Verilog HDL is similar to the C programming language. This paper proposes a unified approach to ALU design in which both simulation and formal verification can co-exist.

Keywords: Addition, arithmetic logic unit, carry look-ahead adder, Verilog HDL.

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Authors: Benmabrouk. Zaineb, Ben Hamed. Mouna, Lassad. Sbita

Abstract:

This article deals to describe the simulation investigation of the digital phase locked loop implemented in software (SDPLL). SDPLL has been developed for speed drives of an induction motor in scalar strategy. A drive was implemented and simulation results are presented to verify the robustness against motor parameter variation and regulation speed.

Keywords: Induction motor, Software Digital Phase LockedLoop, Speed control, Simulation.

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Authors: Ionel Zagan, Vasile Gheorghita Gaitan

Abstract:

Minimizing the response time to asynchronous events in a real-time system is an important factor in increasing the speed of response and an interesting concept in designing equipment fast enough for the most demanding applications. The present article will present the results regarding the validation of the nMPRA (Multi Pipeline Register Architecture) architecture using the FPGA Virtex-7 circuit. The nMPRA concept is a hardware processor with the scheduler implemented at the processor level; this is done without affecting a possible bus communication, as is the case with the other CPU solutions. The implementation of static or dynamic scheduling operations in hardware and the improvement of handling interrupts and events by the real-time executive described in the present article represent a key solution for eliminating the overhead of the operating system functions. The nMPRA processor is capable of executing a preemptive scheduling, using various algorithms without a software scheduler. Therefore, we have also presented various scheduling methods and algorithms used in scheduling the real-time tasks.

Keywords: nMPRA architecture, pipeline processor, preemptive scheduling, real-time system.

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Authors: Bambang Ariantara, Nandy Putra, Rangga Aji Pamungkas

Abstract:

The development of electric vehicle batteries have resulted in very high energy density lithium-ion batteries. However, this progress is accompanied by the risk of thermal runaway, which can result in serious accidents. Heat pipes are heat exchangers that are suitable to be applied in electric vehicle battery thermal management for their lightweight, compact size and do not require external power supply. This paper aims to examine experimentally a Flat Plate Loop Heat Pipe (FPLHP) performance as a heat exchanger in thermal management system of lithium-ion battery for electric vehicle application. The heat generation of the battery was simulated using a cartridge heater. Stainless steel screen mesh was used as the capillary wick. Distilled water, alcohol and acetone were used as working fluids with a filling ratio of 60%. It was found that acetone gives the best performance that produces thermal resistance of 0.22 W/°C with 50°C evaporator temperature at heat flux load of 1.61 W/cm2.

Keywords: Electric vehicle, flat plate loop heat pipe, lithium-ion battery, thermal management system.

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Authors: Youngjae Jin, Daeshik Kim

Abstract:

This paper describes a cycle accurate simulation results of weight values learned by an auto-encoder behavior model in terms of pre-route simulation. Given the results we visualized the first layer representations with natural images. Many common deep learning threads have focused on learning high-level abstraction of unlabeled raw data by unsupervised feature learning. However, in the process of handling such a huge amount of data, the learning method’s computation complexity and time limited advanced research. These limitations came from the fact these algorithms were computed by using only single core CPUs. For this reason, parallel-based hardware, FPGAs, was seen as a possible solution to overcome these limitations. We adopted and simulated the ready-made auto-encoder to design a behavior model in VerilogHDL before designing hardware. With the auto-encoder behavior model pre-route simulation, we obtained the cycle accurate results of the parameter of each hidden layer by using MODELSIM. The cycle accurate results are very important factor in designing a parallel-based digital hardware. Finally this paper shows an appropriate operation of behavior model based pre-route simulation. Moreover, we visualized learning latent representations of the first hidden layer with Kyoto natural image dataset.

Keywords: Auto-encoder, Behavior model simulation, Digital hardware design, Pre-route simulation, Unsupervised feature learning.

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Authors: Rehab Abdullah Shendi

Abstract:

The use of customised soft-core processors in which instructions can be integrated into a system in application hardware is increasing in the Field Programmable Gate Array (FPGA) field. Specifically, the partial run-time reconfiguration of FPGAs in specialised processors for a particular domain can be very beneficial. In this report, the design and implementation for the customisation of a soft-core MIPS processor using an FPGA and partial reconfiguration (PR) of FPGA technology will be addressed to achieve efficient resource use. This can be achieved using a PR design flow that helps the design fit into a smaller device. Moreover, the impact of static power consumption could be reduced due to runtime reconfiguration. This will be done by configurable custom instructions implemented in the hardware as an extension on the MIPS CPU. The aim of this project is to investigate the PR of FPGAs for run-time adaptations of the instruction set of a soft-core CPU, including the integration of custom instructions and the exploration of the potential to use the MultiBoot feature available in Xilinx FPGAs to carry out the PR process. The system will be evaluated and tested on a Nexus 3 development board featuring a Xilinx Spartran-6 FPGA. The system will be able to load reconfigurable custom instructions dynamically into user programs with the help of the trap handler when the custom instruction is called by the MIPS CPU. The results of this experiment demonstrate that custom instructions in hardware can speed up a certain function and many instructions can be saved when compared to a software implementation of the same function. Implementing custom instructions in hardware is perfectly possible and worth exploring.

Keywords: Customisation, FPGA, MIPS, partial reconfiguration.

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Authors: Amit Kumar, Himanshu Singal, Arnav Bhavsar

Abstract:

In this modern era of automation, most of the academic exams and competitive exams are Multiple Choice Questions (MCQ). The responses of these MCQ based exams are recorded in the Optical Mark Reader (OMR) sheet. Evaluation of the OMR sheet requires separate specialized machines for scanning and marking. The sheets used by these machines are special and costs more than a normal sheet. Available process is non-economical and dependent on paper thickness, scanning quality, paper orientation, special hardware and customized software. This study tries to tackle the problem of evaluating the OMR sheet without any special hardware and making the whole process economical. We propose an image processing based algorithm which can be used to read and evaluate the scanned OMR sheets with no special hardware required. It will eliminate the use of special OMR sheet. Responses recorded in normal sheet is enough for evaluation. The proposed system takes care of color, brightness, rotation, little imperfections in the OMR sheet images.

Keywords: OMR, image processing, hough circle transform, interpolation, detection, Binary Thresholding.

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Authors: Kazutaka Kobayashi, Norihiko Yoshida, Shuji Narazaki

Abstract:

This paper presents a dynamic adaptation scheme for the frequency of inter-deme migration in distributed genetic algorithms (GA), and its VLSI hardware design. Distributed GA, or multi-deme-based GA, uses multiple populations which evolve concurrently. The purpose of dynamic adaptation is to improve convergence performance so as to obtain better solutions. Through simulation experiments, we proved that our scheme achieves better performance than fixed frequency migration schemes.

Keywords: Genetic algorithms, dynamic adaptation, VLSI hardware.

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Authors: Jarrod Trevathan, Trina Myers

Abstract:

Proprietary sensor network systems are typically expensive, rigid and difficult to incorporate technologies from other vendors. When using competing and incompatible technologies, a non-proprietary system is complex to create because it requires significant technical expertise and effort, which can be more expensive than a proprietary product. This paper presents the Sensor Abstraction Layer (SAL) that provides middleware architectures with a consistent and uniform view of heterogeneous sensor networks, regardless of the technologies involved. SAL abstracts and hides the hardware disparities and specificities related to accessing, controlling, probing and piloting heterogeneous sensors. SAL is a single software library containing a stable hardware-independent interface with consistent access and control functions to remotely manage the network. The end-user has near-real-time access to the collected data via the network, which results in a cost-effective, flexible and simplified system suitable for novice users. SAL has been used for successfully implementing several low-cost sensor network systems.

Keywords: Sensor networks, hardware abstraction, middleware integration platform, sensor web enablement.

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