Search results for: Field Programmable gate array (FPGA)

Authors: Ju-Hong Lee, Ching-Wei Liao, Kun-Che Lee

Abstract:

This paper deals with the problem of using antenna sensors for adaptive beamforming in the presence of random steering mismatch. We present an efficient adaptive array beamformer with robustness to deal with the considered problem. The robustness of the proposed beamformer comes from the efficient designation of the steering vector. Using the received array data vector, we construct an appropriate correlation matrix associated with the received array data vector and a correlation matrix associated with signal sources. Then, the eigenvector associated with the largest eigenvalue of the constructed signal correlation matrix is designated as an appropriate estimate of the steering vector. Finally, the adaptive weight vector required for adaptive beamforming is obtained by using the estimated steering vector and the constructed correlation matrix of the array data vector. Simulation results confirm the effectiveness of the proposed method.

Keywords: Adaptive beamforming, antenna array, linearly constrained minimum variance, robustness, steering vector.

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Authors: Mustafa Abdalla, Khaled A. Madi, Rajab Farhat

Abstract:

An array antenna system with innovative signal processing can improve the resolution of a source direction of arrival (DoA) estimation. High resolution techniques take the advantage of array antenna structures to better process the incoming waves. They also have the capability to identify the direction of multiple targets. This paper investigates performance of the DOA estimation algorithm namely; Capon and MUSIC on the uniform linear array (ULA). The simulation results show that in Capon and MUSIC algorithm the resolution of the DOA techniques improves as number of snapshots, number of array elements, signal-to-noise ratio and separation angle between the two sources θ increases.

Keywords: Antenna array, Capon, MUSIC, Direction-of-arrival estimation, signal processing, uniform linear arrays.

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Authors: Somayeh Komeylian

Abstract:

Array signal processing techniques have been recently developing in a variety application of the performance enhancement of receivers by refraining the power of jamming and interference signals. In this scenario, biases induced to the antenna array receiver degrade significantly the accurate estimation of the carrier phase. Owing to the integration of frequency becomes the carrier phase, we have obtained the unbiased doppler frequency for the high precision estimation of carrier phase. The unbiased characteristic of Doppler frequency to the power jamming and the other interference signals allows achieving the highly accurate estimation of phase carrier. In this study, we have rigorously investigated the unbiased characteristic of Doppler frequency to the variation of the antenna array geometries. The simulation results have efficiently verified that the Doppler frequency remains also unbiased and accurate to the variation of antenna array geometries.

Keywords: Array signal processing, unbiased Doppler frequency, GNSS, carrier phase, slowly fluctuating point target.

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Authors: Olesya Bolkhovskaya, Alexey Davydov, Alexander Maltsev

Abstract:

In this paper, approach to incoherent signal detection in multi-element antenna array are researched and modeled. Two types of useful signals with unknown wavefront were considered: first one, deterministic (Barker code), and second one, random (Gaussian distribution). The derivation of the sufficient statistics took into account the linearity of the antenna array. The performance characteristics and detecting curves are modeled and compared for different useful signals parameters and for different number of elements of the antenna array. Results of researches in case of some additional conditions can be applied to a digital communications systems.

Keywords: Antenna array, detection curves, performance characteristics, quadrature processing, signal detection.

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Authors: Rishikesh Pandey, Maneesha Gupta

Abstract:

A new low-voltage floating gate MOSFET (FGMOS) based squarer using square law characteristic of the FGMOS is proposed in this paper. The major advantages of the squarer are simplicity, rail-to-rail input dynamic range, low total harmonic distortion, and low power consumption. The proposed circuit is biased without body effect. The circuit is designed and simulated using SPICE in 0.25μm CMOS technology. The squarer is operated at the supply voltages of ±0.75V . The total harmonic distortion (THD) for the input signal 0.75Vpp at 25 KHz, and maximum power consumption were found to be less than 1% and 319μW respectively.

Keywords: Analog signal processing, floating gate MOSFETs, low-voltage, Spice, squarer.

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Authors: Saurabh Chanana, Monika Arora

Abstract:

Demand response is getting increased attention these days due to the increase in electricity demand and introduction of renewable resources in the existing power grid. Traditionally demand response programs involve large industrial consumers but with technological advancement, demand response is being implemented for small residential and commercial consumers also. In this paper, demand response program aims to reduce the peak demand as well as overall energy consumption of the residential customers. Air conditioners are the major reason of peak load in residential sector in summer, so a dynamic model of air conditioning load with thermostat action has been considered for applying demand response programs. A programmable communicating thermostat (PCT) is a device that uses real time pricing (RTP) signals to control the thermostat setting. A new model incorporating PCT in air conditioning load has been proposed in this paper. Results show that introduction of PCT in air conditioner is useful in reducing the electricity payments of customers as well as reducing the peak demand. 

Keywords: Demand response, Home energy management Programmable communicating thermostat, Thermostatically controlled appliances.

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Authors: Sheng Ge, Jian-Peng Wang, Hai-Ying Tang, Xi Xiao, Wen Wu

Abstract:

This research proposed a new design of helmet-shaped array transcranial magnetic stimulation coil system. It was constructed using several sagittal directional wires and several coronal directional wires. By varying the current direction and strength on each wire, this array coil system could be constructed into the circular coil and figure-eight coil of different size. Also, this proposed coil system can flexibly not only change the stimulation location, range, type and strength, but also change the shape and the channel number of coil dynamically.

Keywords: TMS, circular coils, figure-eight coil, array coil

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Authors: Dia I. Abu-Al-Nadi, M. J. Mismar, T. H. Ismail

Abstract:

A technique for estimating the direction-of-arrival (DOA) of unknown number of source signals is presented using the eigen-approach. The eigenvector corresponding to the minimum eigenvalue of the autocorrelation matrix yields the minimum output power of the array. Also, the array polynomial with this eigenvector possesses roots on the unit circle. Therefore, the pseudo-spectrum is found by perturbing the phases of the roots one by one and calculating the corresponding array output power. The results indicate that the DOAs and the number of source signals are estimated accurately in the presence of a wide range of input noise levels.

Keywords: Array signal processing, direction-of-arrival, antenna arrays, eigenvalues, eigenvectors.

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Authors: F. Smach, M. Atri, J. Mitéran, M. Abid

Abstract:

Face detection and recognition has many applications in a variety of fields such as security system, videoconferencing and identification. Face classification is currently implemented in software. A hardware implementation allows real-time processing, but has higher cost and time to-market. The objective of this work is to implement a classifier based on neural networks MLP (Multi-layer Perceptron) for face detection. The MLP is used to classify face and non-face patterns. The systm is described using C language on a P4 (2.4 Ghz) to extract weight values. Then a Hardware implementation is achieved using VHDL based Methodology. We target Xilinx FPGA as the implementation support.

Keywords: Classification, Face Detection, FPGA Hardware description, MLP.

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Authors: Chiang-Ho Cheng, Hong-Yih Cheng, An-Shik Yang, Tung-Hsun Hsu

Abstract:

This paper reports a novel actuating design that uses the shear deformation of a piezoelectric actuator to deflect a bulge-diaphragm for driving an array microdroplet ejector. In essence, we employed a circular-shaped actuator poled radial direction with remnant polarization normal to the actuating electric field for inducing the piezoelectric shear effect. The array microdroplet ejector consists of a shear type piezoelectric actuator, a vibration plate, two chamber plates, two channel plates and a nozzle plate. The vibration, chamber and nozzle plate components are fabricated using nickel electroforming technology, whereas the channel plate is fabricated by etching of stainless steel. The diaphragm displacement was measured by the laser two-dimensional scanning vibrometer. The ejected droplets of the microejector were also observed via an optic visualization system.

Keywords: Actuator, nozzle, microejector, piezoelectric.

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Authors: V. Masilamani, D.K. Sheena Christy, D.G. Thomas

Abstract:

Image synthesis is an important area in image processing. To synthesize images various systems are proposed in the literature. In this paper, we propose a bio-inspired system to synthesize image and to study the generating power of the system, we define the class of languages generated by our system. We call image as array in this paper. We use a primitive called iso-array to synthesize image/array. The operation is double splicing on iso-arrays. The double splicing operation is used in DNA computing and we use this to synthesize image. A comparison of the family of languages generated by the proposed self restricted double splicing systems on iso-arrays with the existing family of local iso-picture languages is made. Certain closure properties such as union, concatenation and rotation are studied for the family of languages generated by the proposed model.

Keywords: DNA computing, splicing system, iso-picture languages, iso-array double splicing system, iso-array self splicing.

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Authors: Suguru Ochiai, Toru Yabuki, Yoshiki Yamaguchi, Yuetsu Kodama

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In this paper, we propose a Connect6 solver which adopts a hybrid approach based on a tree-search algorithm and image processing techniques. The solver must deal with the complicated computation and provide high performance in order to make real-time decisions. The proposed approach enables the solver to be implemented on a single Spartan-6 XC6SLX45 FPGA produced by XILINX without using any external devices. The compact implementation is achieved through image processing techniques to optimize a tree-search algorithm of the Connect6 game. The tree search is widely used in computer games and the optimal search brings the best move in every turn of a computer game. Thus, many tree-search algorithms such as Minimax algorithm and artificial intelligence approaches have been widely proposed in this field. However, there is one fundamental problem in this area; the computation time increases rapidly in response to the growth of the game tree. It means the larger the game tree is, the bigger the circuit size is because of their highly parallel computation characteristics. Here, this paper aims to reduce the size of a Connect6 game tree using image processing techniques and its position symmetric property. The proposed solver is composed of four computational modules: a two-dimensional checkmate strategy checker, a template matching module, a skilful-line predictor, and a next-move selector. These modules work well together in selecting next moves from some candidates and the total amount of their circuits is small. The details of the hardware design for an FPGA implementation are described and the performance of this design is also shown in this paper.

Keywords: Connect6, pattern matching, game-tree reduction, hardware direct computation

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Authors: Hai-Qing Xie, Yun Zeng, Yong-Hong Yan, Jian-Ping Zeng, Tai-Hong Wang

Abstract:

Photo-BJMOSFET (Bipolar Junction Metal-Oxide- Semiconductor Field Effect Transistor) fabricated on SOI film was proposed. ITO film is adopted in the device as gate electrode to reduce light absorption. Depletion region but not inversion region is formed in film by applying gate voltage (but low reverse voltage) to achieve high photo-to-dark-current ratio. Comparisons of photoelectriccharacteristics executed among VGK=0V, 0.3V, 0.6V, 0.9V and 1.0V (reverse voltage VAK is equal to 1.0V for total area of 10×10μm2). The results indicate that the greatest improvement in photo-to-dark-current ratio is achieved up to 2.38 at VGK=0.6V. In addition, photo-BJMOSFET is compatible with CMOS integration due to big input resistance

Keywords: Photo-BJMOSFET, Responsivity, Sensitivity, Spectral response.

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Authors: Mansi Jhamb, R. K. Sharma, A. K. Gupta

Abstract:

The distribution of a single global clock across a chip has become the major design bottleneck for high performance VLSI systems owing to the power dissipation, process variability and multicycle cross-chip signaling. A Network-on-Chip (NoC) architecture partitioned into several synchronous blocks has become a promising approach for attaining fine-grain power management at the system level. In a NoC architecture the communication between the blocks is handled asynchronously. To interface these blocks on a chip operating at different frequencies, an asynchronous FIFO interface is inevitable. However, these asynchronous FIFOs are not required if adjacent blocks belong to the same clock domain. In this paper, we have designed and analyzed a 16-bit asynchronous micropipelined FIFO of depth four, with the awareness of place and route on an FPGA device. We have used a commercially available Spartan 3 device and designed a high speed implementation of the asynchronous 4-phase micropipeline. The asynchronous FIFO implemented on the FPGA device shows 76 Mb/s throughput and a handshake cycle of 109 ns for write and 101.3 ns for read at the simulation under the worst case operating conditions (voltage = 0.95V) on a working chip at the room temperature.

Keywords: Asynchronous, FIFO, FPGA, GALS, Network-on- Chip (NoC), VHDL.

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Authors: Paris Kitsos

Abstract:

In this paper the FPGA implementations for four stream ciphers are presented. The two stream ciphers, MUGI and SNOW 2.0 are recently adopted by the International Organization for Standardization ISO/IEC 18033-4:2005 standard. The other two stream ciphers, MICKEY 128 and TRIVIUM have been submitted and are under consideration for the eSTREAM, the ECRYPT (European Network of Excellence for Cryptology) Stream Cipher project. All ciphers were coded using VHDL language. For the hardware implementation, an FPGA device was used. The proposed implementations achieve throughputs range from 166 Mbps for MICKEY 128 to 6080 Mbps for MUGI.

Keywords: Cryptography, ISO/IEC 18033-4:2005 standard, Hardware implementation, Stream ciphers

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Authors: Hamid Abdi, Abolfazl Salami, Abolfazl Ahmadi

Abstract:

Programmable logic controllers are the main controllers in the today's industries; they are used for several applications in industrial control systems and there are lots of examples exist from the PLC applications in industries especially in big companies and plants such as refineries, power plants, petrochemical companies, steel companies, and food and production companies. In the PLCs there are some functions in the function library in software that can be used in PLC programs as basic program elements. The aim of this project are introducing and implementing a new function block of a neural network to the function library of PLC. This block can be applied for some control applications or nonlinear functions calculations after it has been trained for these applications. The implemented neural network is a Perceptron neural network with three layers, three input nodes and one output node. The block can be used in manual or automatic mode. In this paper the structure of the implemented function block, the parameters and the training method of the network are presented by considering the especial method of PLC programming and its complexities. Finally the application of the new block is compared with a classic simulated block and the results are presented.

Keywords: Programmable Logic Controller, PLC Programming, Neural Networks, Perception Network, Intelligent Control.

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Authors: Youguo Wang, Lenan Wu

Abstract:

We discuss the signal detection through nonlinear threshold systems. The detection performance is assessed by the probability of error Per . We establish that: (1) when the signal is complete suprathreshold, noise always degrades the signal detection both in the single threshold system and in the parallel array of threshold devices. (2) When the signal is a little subthreshold, noise degrades signal detection in the single threshold system. But in the parallel array, noise can improve signal detection, i.e., stochastic resonance (SR) exists in the array. (3) When the signal is predominant subthreshold, noise always can improve signal detection and SR always exists not only in the single threshold system but also in the parallel array. (4) Array can improve signal detection by raising the number of threshold devices. These results extend further the applicability of SR in signal detection.

Keywords: Probability of error, signal detection, stochasticresonance, threshold system.

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Authors: Ahmet Turer

Abstract:

Middle-gate is located in Hasankeyf, Batman dating back to 1800 BC and is one of the important historical structures in Turkey. The ancient structure has suffered major structural cracks due to aging as well as lateral pressure of a cracked rock which is predicted to be about 100 tons. The existing support system was found to be inadequate to support the load especially after a recent rock fall in the close vicinity. Concerns were increased since the existing support system that is integral with a damaged and cracked gate wall needed to be replaced by a new support system. The replacement process must be carefully monitored by crackmeters and control mechanisms should be integrated to prevent cracks to expand while the same crack width needs to be maintained after the operation. The control system and actions taken during the intervention are explained in this paper.

Keywords: structural control, crack width, replacement, support

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Authors: Chi-Fang Huang, Xi-Zhang Lin, Yi-Ru Yang

Abstract:

Aiming the application of localized hyperthermia, a magnetic induction system with new approaches is proposed. The techniques in this system for improving the effectiveness of localized hyperthermia are that using magnetic circuit and the multiple-coil array instead of a giant coil for generating magnetic field. Specially, amorphous metal is adopted as the material of magnetic circuit. Detail design parameters of hardware are well described. Simulation tool is employed for this work and experiment result is reported as well.

Keywords: cancer therapy, hyperthermia, Helmholtz coil, induction heating, magnetic circuit.

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Authors: N. Massoum, A. Guen. Bouazza, B. Bouazza, A. El Ouchdi

Abstract:

The progress of industry integrated circuits in recent years has been pushed by continuous miniaturization of transistors. With the reduction of dimensions of components at 0.1 micron and below, new physical effects come into play as the standard simulators of two dimensions (2D) do not consider. In fact the third dimension comes into play because the transverse and longitudinal dimensions of the components are of the same order of magnitude. To describe the operation of such components with greater fidelity, we must refine simulation tools and adapted to take into account these phenomena. After an analytical study of the static characteristics of the component, according to the different operating modes, a numerical simulation is performed of field-effect transistor with submicron gate MESFET GaInP. The influence of the dimensions of the gate length is studied. The results are used to determine the optimal geometric and physical parameters of the component for their specific applications and uses.

Keywords: Monte Carlo simulation, transient electron transport, MESFET device.

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Authors: Fasil Endalamaw

Abstract:

Digital magnitude comparators based on Gate Diffusion Input (GDI) implementation technique are high speed and area-efficient, and they consume less power as compared to other implementation techniques. However, they are less efficient for some logic gates and have no full voltage swing. In this paper, we made a performance comparison between the GDI implementation technique and other implementation methods, such as Static CMOS, Pass Transistor Logic (PTL), and Transmission Gate (TG) in 90 nm, 120 nm, and 180 nm CMOS technologies using BSIM4 MOS model. We proposed a methodology (hybrid implementation) of implementing digital magnitude comparators which significantly improved the power, speed, area, and voltage swing requirements. Simulation results revealed that the hybrid implementation of digital magnitude comparators show a 10.84% (power dissipation), 41.6% (propagation delay), 47.95% (power-delay product (PDP)) improvement compared to the usual GDI implementation method. We used Microwind & Dsch Version 3.5 as well as the Tanner EDA 16.0 tools for simulation purposes.

Keywords: Efficient, gate diffusion input, high speed, low power, CMOS.

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Authors: K. E. Kaharudin, A. H. Hamidon, F. Salehuddin

Abstract:

Vertical Double Gate (DG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is believed to suppress various short channel effect problems. The gate to channel coupling in vertical DG-MOSFET are doubled, thus resulting in higher current density. By having two gates, both gates are able to control the channel from both sides and possess better electrostatic control over the channel. In order to ensure that the transistor possess a superb turn-off characteristic, the subs-threshold swing (SS) must be kept at minimum value (60-90mV/dec). By utilizing SILVACO TCAD software, an n-channel vertical DG-MOSFET was successfully designed while keeping the sub-threshold swing (SS) value as minimum as possible. From the observation made, the value of sub-threshold swing (SS) was able to be varied by adjusting the height of the silicon pillar. The minimum value of sub-threshold swing (SS) was found to be 64.7mV/dec with threshold voltage (V_TH) of 0.895V. The ideal height of the vertical DG-MOSFET pillar was found to be at 0.265 µm.

Keywords: DG-MOSFET, pillar, SCE, vertical

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Authors: Padmanabhan Balasubramanian, C. Ardil

Abstract:

An effective approach for realizing the binary tree structure, representing a combinational logic functionality with enhanced throughput, is discussed in this paper. The optimization in maximum operating frequency was achieved through delay minimization, which in turn was possible by means of reducing the depth of the binary network. The proposed synthesis methodology has been validated by experimentation with FPGA as the target technology. Though our proposal is technology independent, yet the heuristic enables better optimization in throughput even after technology mapping for such Boolean functionality; whose reduced CNF form is associated with a lesser literal cost than its reduced DNF form at the Boolean equation level. For cases otherwise, our method converges to similar results as that of [12]. The practical results obtained for a variety of case studies demonstrate an improvement in the maximum throughput rate for Spartan IIE (XC2S50E-7FT256) and Spartan 3 (XC3S50-4PQ144) FPGA logic families by 10.49% and 13.68% respectively. With respect to the LUTs and IOBUFs required for physical implementation of the requisite non-regenerative logic functionality, the proposed method enabled savings to the tune of 44.35% and 44.67% respectively, over the existing efficient method available in literature [12].

Keywords: Binary logic tree, FPGA based design, Boolean function, Throughput rate, CNF, DNF.

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Authors: R. Hanuma Naik, D. V. Ashok Kumar, K. S. R. Anjaneyulu

Abstract:

Several of the practical industrial control processes are multivariable processes. Due to the relation amid the variables (interaction), delay in the loops, it is very intricate to design a controller directly for these processes. So first, the interaction of the variables is analyzed using Relative Normalized Gain Array (RNGA), which considers the time constant, static gain and delay time of the processes. Based on the effect of RNGA, relative gain array (RGA) and NI, the pair (control configuration) of variables to be controlled by decentralized control is selected. The equivalent transfer function (ETF) of the process model is estimated as first order process with delay using the corresponding elements in the Relative gain array and Relative average residence time array (RARTA) of the processes. Secondly, a decentralized Proportional- Integral (PI) controller is designed for each ETF simply using frequency response specifications. Finally, the performance and robustness of the algorithm is comparing with existing related approaches to validate the effectiveness of the projected algorithm.

Keywords: Decentralized control, interaction, Multivariable processes, relative normalized gain array, relative average residence time array, steady state gain.

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Authors: Hung-Pei Hsu, Jyi-Tsong Lin, Po-Hsieh Lin, Cheng-Hsien Chang, Ming-Tsung Shih, Chan-Hsiang Chang, Shih-Chuan Tseng, Min-Yan Lin, Shih-Wen Hsu

Abstract:

In this paper, we propose a novel metal oxide semiconductor field effect transistor with L-shaped channel structure (LMOS), and several type of L-shaped structures are also designed, studied and compared with the conventional MOSFET device for the same average gate length (Lavg). The proposed device electrical characteristics are analyzed and evaluated by three dimension (3-D) ISE-TCAD simulator. It can be confirmed that the LMOS devices have higher on-state drain current and both lower drain-induced barrier lowering (DIBL) and subthreshold swing (S.S.) than its conventional counterpart has. In addition, the transconductance and voltage gain properties of the LMOS are also improved.

Keywords: Average gate length (Lavg), drain-induced barrier lowering (DIBL), L-shaped channel MOSFET (LMOS), subthreshold swing (S.S.).

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Authors: Shubhajit Roy Chowdhury, Aritra Banerjee, Aniruddha Roy, Hiranmay Saha

Abstract:

The paper proposes the novel design of a 3T XOR gate combining complementary CMOS with pass transistor logic. The design has been compared with earlier proposed 4T and 6T XOR gates and a significant improvement in silicon area and power-delay product has been obtained. An eight transistor full adder has been designed using the proposed three-transistor XOR gate and its performance has been investigated using 0.15um and 0.35um technologies. Compared to the earlier designed 10 transistor full adder, the proposed adder shows a significant improvement in silicon area and power delay product. The whole simulation has been carried out using HSPICE.

Keywords: XOR gate, full adder, improvement in speed, area minimization, transistor count minimization.

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Authors: Blesson Varghese, Gerard T. McKee

Abstract:

The work reported in this paper is motivated by the fact that there is a need to apply autonomic computing concepts to parallel computing systems. Advancing on prior work based on intelligent cores [36], a swarm-array computing approach, this paper focuses on 'Intelligent agents' another swarm-array computing approach in which the task to be executed on a parallel computing core is considered as a swarm of autonomous agents. A task is carried to a computing core by carrier agents and is seamlessly transferred between cores in the event of a predicted failure, thereby achieving self-ware objectives of autonomic computing. The feasibility of the proposed swarm-array computing approach is validated on a multi-agent simulator.

Keywords: Autonomic computing, intelligent agents, swarm-array computing.

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Authors: S.M. Lee, J.H. Koo, J.H. Park, S.C. Won

Abstract:

In this paper, we propose synchronization of an array of nonlinear systems with time delays. The array of systems is decomposed into isolated systems to establish appropriate Lyapunov¬Krasovskii functional. Using the Lyapunov-Krasovskii functional, a sufficient condition for the synchronization is derived in terms of LMIs(Linear Matrix Inequalities). Delayed feedback control gains are obtained by solving the sufficient condition. Numerical examples are given to show the validity the proposed method.

Keywords: Synchronization, Delay, Lyapunov method, LMI.

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Authors: Li Li, Li-Ru Xia, He-Ye Wang, Xiao-Dong Bi

Abstract:

In this paper, we presented a highly sensitive immune-affinity monolithic array for detection of α-fetoprotein (AFP) and carcinoembryonic antigen (CEA). Firstly, the epoxy functionalized monolith arrays were fabricated using UV initiated copolymerization method. Scanning electron microscopy (SEM) image showed that the poly(BABEA-co-GMA) monolith exhibited a well-controlled skeletal and well-distributed porous structure. Then, AFP and CEA immune-affinity monolithic arrays were prepared by immobilization of AFP and CEA antibodies on epoxy functionalized monolith arrays. With a non-competitive immune response format, the presented AFP and CEA immune-affinity arrays were demonstrated as an inexpensive, flexible, homogeneous and stable array for detection of AFP and CEA.

Keywords: Chemiluminescent detection, immune-affinity, monolithic copolymer array, UV-initiated copolymerization.

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Authors: Yngvar Berg, Mehdi Azadmehr

Abstract:

In this paper we present a linear autozeroing ultra lowvoltage amplifier. The autozeroing performed by all ULV circuits is important to reduce the impact of noise and especially avoid power supply noise in mixed signal low-voltage CMOS circuits. The simulated data presented is relevant for a 90nm TSMC CMOS process.

Keywords: Low-voltage, trans conductance amplifier, linearity, floating-gate.

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