Search results for: CMOS Inverter

Authors: Muhaned Zaidi, Ian Grout, Abu Khari bin A’ain

Abstract:

In this paper, a two-stage op-amp design is considered using both Miller and negative Miller compensation techniques. The first op-amp design uses Miller compensation around the second amplification stage, whilst the second op-amp design uses negative Miller compensation around the first stage and Miller compensation around the second amplification stage. The aims of this work were to compare the gain and phase margins obtained using the different compensation techniques and identify the ability to choose either compensation technique based on a particular set of design requirements. The two op-amp designs created are based on the same two-stage rail-to-rail output CMOS op-amp architecture where the first stage of the op-amp consists of differential input and cascode circuits, and the second stage is a class AB amplifier. The op-amps have been designed using a 0.35mm CMOS fabrication process.

Keywords: Op-amp, rail-to-rail output, Miller compensation, negative Miller capacitance.

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Authors: M. Tarafdar Haque, A. Taheri

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Application of neural networks in execution of programmed pulse width modulation (PPWM) of a voltage source inverter (VSI) is studied in this paper. Using the proposed method it is possible to cancel out the desired harmonics in output of VSI in addition to control the magnitude of fundamental harmonic, contineously. By checking the non-trained values and a performance index, the most appropriate neural network is proposed. It is shown that neural networks may solve the custom difficulties of practical utilization of PPWM such as large size of memory, complex digital circuits and controlling the magnitude of output voltage in a discrete manner.

Keywords: Neural Network, Inverter, PPWM.

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Authors: Hanifah Jambari, Naziha A. Azli, M. Afendi M. Piah

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This paper presents the generation of bipolar square wave pulses with characteristics that are suitable for liquid food sterilization using a Cascaded H-bridge Multilevel Inverter (CHMI). Bipolar square waves pulses have been reported as stable for a longer time during the sterilization process with minimum heat emission and increased efficiency. The CHMI allows the system to produce bipolar square wave pulses and yielding high output voltage without using a transformer while fulfilling the pulse requirements for effective liquid food sterilization. This in turn can reduce power consumption and cost of the overall liquid food sterilization system. The simulation results have shown that pulses with peak output voltage of 2.4 kV, pulse width of between 1 2s and 1 ms at frequencies of 50 Hz and 100 Hz can be generated by a 7-level CHMI. Results from the experimental set-up based on a 5-level CHMI has indicated the potential of the proposed circuit in producing bipolar square wave output pulses with peak values that depends on the DC source level supplied to the CHMI modules, pulse width of between 12.5 2s and 1 ms at frequencies of 50 Hz and 100 Hz.

Keywords: pulsed electric field, multilevel inverter, bipolarsquare wave, food sterilization

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Authors: Kuang-Hsiung Tan, Chih-Chan Hu, Chien-Wu Lan, Shih-Sung Lin, Te-Jen Chang

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An active islanding detection method using disturbance signal injection with intelligent controller is proposed in this study. First, a DC\AC power inverter is emulated in the distributed generator (DG) system to implement the tracking control of active power, reactive power outputs and the islanding detection. The proposed active islanding detection method is based on injecting a disturbance signal into the power inverter system through the d-axis current which leads to a frequency deviation at the terminal of the RLC load when the utility power is disconnected. Moreover, in order to improve the transient and steady-state responses of the active power and reactive power outputs of the power inverter, and to further improve the performance of the islanding detection method, two probabilistic fuzzy neural networks (PFNN) are adopted to replace the traditional proportional-integral (PI) controllers for the tracking control and the islanding detection. Furthermore, the network structure and the online learning algorithm of the PFNN are introduced in detail. Finally, the feasibility and effectiveness of the tracking control and the proposed active islanding detection method are verified with experimental results.

Keywords: Distributed generators, probabilistic fuzzy neural network, islanding detection, non-detection zone.

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Authors: Parag Nihawan, Ravinder Singh Bhatia, Dinesh Kumar Jain

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Industrial drives are source of serious power quality problems. In this, two typical industrial drives have been dealt with, namely, FOC induction motor drives and DTC induction motor drive. The Z-source inverter is an emerging topology of power electronic converters which is capable of buck boost characteristics. The performances of different control methods based Z-source inverters feeding these industrial drives have been investigated, in this work. The test systems have been modeled and simulated in MATLAB/SIMULINK. The results obtained after carrying out these simulations have been used to draw the conclusions.

Keywords: Z-Source Inverter, total harmonic distortion, direct torque control, field orientation control.

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Authors: Jae Hyung Noh, Hang Geun Jeong

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The charge-pump circuit is an important component in a phase-locked loop (PLL). The charge-pump converts Up and Down signals from the phase/frequency detector (PFD) into current. A conventional CMOS charge-pump circuit consists of two switched current sources that pump charge into or out of the loop filter according to two logical inputs. The mismatch between the charging current and the discharging current causes phase offset and reference spurs in a PLL. We propose a new charge-pump circuit to reduce the current mismatch by using a regulated cascode circuit. The proposed charge-pump circuit is designed and simulated by spectre with TSMC 0.18-μm 1.8-V CMOS technology.

Keywords: Phase-locked loop (PLL), charge-pump, phase/frequency detector (PFD), regulated cascode.

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Authors: D. Krishnaveni, M. Geetha Priya

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Applications of reversible logic gates in the design of complex integrated circuits provide power optimization.  This technique finds a great use in low power CMOS design, optical computing, quantum computing and nanotechnology. This paper proposes a reversible signed division circuit that can divide an n-bit signed dividend with an n-bit signed divisor using non-restoration division logic. The proposed design adequately addresses the ‘delay’ there by improving the efficiency of the circuit. An attempt is made to design a reversible signed division circuit. This paper provides a threshold to build more complex arithmetic systems using reversible logic, thus increasing the performance of computing systems.

Keywords: Low power CMOS, quantum computing, reversible logic gates, shift register, signed division.

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Authors: Syed Islam, Yiyun Huang, Sebastian Magierowski, Ebrahim Ghafar-Zadeh

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This paper presents system level CMOS solid-state nanopore techniques enhancement for speedup next generation molecular recording and high throughput channels. This discussion also considers optimum number of base-pair (bp) measurements through channel as an important role to enhance potential read accuracy. Effective power consumption estimation offered suitable range of multi-channel configuration. Nanopore bp extraction model in statistical method could contribute higher read accuracy with longer read-length (200 < read-length). Nanopore ionic current switching with Time Multiplexing (TM) based multichannel readout system contributed hardware savings.

Keywords: DNA, Nanopore, Amplifier, ADC, Multichannel.

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Authors: Nasser Erfani Majd, Mojtaba Lotfizad

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In this paper, an ultra low power and low jitter 12bit CMOS digitally controlled oscillator (DCO) design is presented. Based on a ring oscillator implemented with low power Schmitt trigger based inverters. Simulation of the proposed DCO using 32nm CMOS Predictive Transistor Model (PTM) achieves controllable frequency range of 550MHz~830MHz with a wide linearity and high resolution. Monte Carlo simulation demonstrates that the time-period jitter due to random power supply fluctuation is under 31ps and the power consumption is 0.5677mW at 750MHz with 1.2V power supply and 0.53-ps resolution. The proposed DCO has a good robustness to voltage and temperature variations and better linearity comparing to the conventional design.

Keywords: digitally controlled oscillator (DCO), low power, jitter; good linearity, robust

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Authors: Joshi Manohar. V., Sujatha. P., Anjaneyulu K. S. R

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The range of the output power is a very important and evident limitation of two-level inverters. In order to overcome this disadvantage, multilevel inverters are introduced. Recently, Cascade H-Bridge inverters have emerged as one of the popular converter topologies used in numerous industrial applications. The modulation switching strategies such as phase shifted carrier based Pulse Width Modulation (PWM) technique and Stair case modulation with Selective Harmonic Elimination (SHE) PWM technique are generally used. NR method is used to solve highly non linear transcendental equations which are formed by SHEPWM method. Generally NR method has a drawback of requiring good initial guess but in this paper a new approach is implemented for NR method with any random initial guess. A three phase CHB 11-level inverter is chosen for analysis. MATLAB/SIMULINK programming environment and harmonic profiles are compared. Finally this paper presents a method at fundamental switching frequency with least % THDV.

Keywords: Cascade H-bridge 11- level Inverter, NR method, Phase shifted carrier based pulse width modulation (PSCPWM), Selective Harmonic Elimination Pulse Width Modulation (SHEPWM), Total Harmonic Distortion (%THDv).

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Authors: Pejman Hosseiniun, Rose Shayeghi, Iman Rahbari, Mohamad Reza Kalhor

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CNFET has emerged as an alternative material to silicon for high performance, high stability and low power SRAM design in recent years. SRAM functions as cache memory in computers and many portable devices. In this paper, a new SRAM cell design based on CNFET technology is proposed. The proposed SRAM cell design for CNFET is compared with SRAM cell designs implemented with the conventional CMOS and FinFET in terms of speed, power consumption, stability, and leakage current. The HSPICE simulation and analysis show that the dynamic power consumption of the proposed 8T CNFET SRAM cell’s is reduced about 48% and the SNM is widened up to 56% compared to the conventional CMOS SRAM structure at the expense of 2% leakage power and 3% write delay increase.

Keywords: SRAM cell, CNFET, low power, HSPICE.

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Authors: M. S. Merzoug, F. Naceri

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This paper presents a comparative study on two most popular control strategies for Permanent Magnet Synchronous Motor (PMSM) drives: field-oriented control (FOC) and direct torque control (DTC). The comparison is based on various criteria including basic control characteristics, dynamic performance, and implementation complexity. The study is done by simulation using the Simulink Power System Blockset that allows a complete representation of the power section (inverter and PMSM) and the control system. The simulation and evaluation of both control strategies are performed using actual parameters of Permanent Magnet Synchronous Motor fed by an IGBT PWM inverter.

Keywords: PMSM, FOC, DTC, hysteresis, PWM.

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Authors: Zina Saheb, Ezz El-Masry, Jean-François Bousquet

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This paper presents an enhanced efficiency simultaneous dual band energy harvesting system for wireless body area network. A bulk biasing is used to enhance the efficiency of the adapted rectifier design to reduce V_th of MOSFET. The presented circuit harvests the radio frequency (RF) energy from two frequency bands: 1 GHz and 2.4 GHz. It is designed with TSMC 65-nm CMOS technology and high quality factor dual matching network to boost the input voltage. Full circuit analysis and modeling is demonstrated. The simulation results demonstrate a harvester with an efficiency of 23% at 1 GHz and 46% at 2.4 GHz at an input power as low as -30 dBm.

Keywords: Energy harvester, simultaneous, dual band, CMOS, differential rectifier, voltage boosting, TSMC 65nm.

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Authors: Kavala Kiran Kumar, R. Govardhana Rao

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Active power filter continues to be a powerful tool to control harmonics in power systems thereby enhancing the power quality. This paper presents a fuzzy tuned PID controller based shunt active filter to diminish the harmonics caused by non linear loads like thyristor bridge rectifiers and imbalanced loads. Here Fuzzy controller provides the tuning of PID, based on firing of thyristor bridge rectifiers and variations in input rms current. The shunt APF system is implemented with three phase current controlled Voltage Source Inverter (VSI) and is connected at the point of common coupling for compensating the current harmonics by injecting equal but opposite filter currents. These controllers are capable of controlling dc-side capacitor voltage and estimating reference currents. Hysteresis Current Controller (HCC) is used to generate switching signals for the voltage source inverter. Simulation studies are carried out with non linear loads like thyristor bridge rectifier along with unbalanced loads and the results proved that the APF along with fuzzy tuned PID controller work flawlessly for different firing angles of non linear load.

Keywords: Active power filters (APF), Fuzzy logic controller (FLC), Hysteresis current controller (HCC), PID, Total harmonic Distortion (THD), Voltage source inverter (VSI).

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Authors: A. K. Al-Othman, H. A. Al-Mekhaizim

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Multilevel inverters supplied from equal and constant dc sources almost don-t exist in practical applications. The variation of the dc sources affects the values of the switching angles required for each specific harmonic profile, as well as increases the difficulty of the harmonic elimination-s equations. This paper presents an extremely fast optimal solution of harmonic elimination of multilevel inverters with non-equal dc sources using Tanaka's fuzzy linear regression formulation. A set of mathematical equations describing the general output waveform of the multilevel inverter with nonequal dc sources is formulated. Fuzzy linear regression is then employed to compute the optimal solution set of switching angles.

Keywords: Multilevel converters, harmonics, pulse widthmodulation (PWM), optimal control.

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Authors: Hai-Qing Xie, Yun Zeng, Yong-Hong Yan, Jian-Ping Zeng, Tai-Hong Wang

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Photo-BJMOSFET (Bipolar Junction Metal-Oxide- Semiconductor Field Effect Transistor) fabricated on SOI film was proposed. ITO film is adopted in the device as gate electrode to reduce light absorption. Depletion region but not inversion region is formed in film by applying gate voltage (but low reverse voltage) to achieve high photo-to-dark-current ratio. Comparisons of photoelectriccharacteristics executed among VGK=0V, 0.3V, 0.6V, 0.9V and 1.0V (reverse voltage VAK is equal to 1.0V for total area of 10×10μm2). The results indicate that the greatest improvement in photo-to-dark-current ratio is achieved up to 2.38 at VGK=0.6V. In addition, photo-BJMOSFET is compatible with CMOS integration due to big input resistance

Keywords: Photo-BJMOSFET, Responsivity, Sensitivity, Spectral response.

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Authors: Kittipong Tripetch

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This paper proposes a study of input impedance of 2 types of CMOS active inductors. It derives 2 input impedance formulas. The first formula is the input impedance of the grounded active inductor. The second formula is the input impedance of the floating active inductor. After that, these formulas can be used to simulate magnitude and phase response of input impedance as a function of current consumption with MATLAB. Common mode rejection ratio (CMRR) of the fully differential bandpass amplifier is derived based on superposition principle. CMRR as a function of input frequency is plotted as a function of current consumption. 

Keywords: Grounded active inductor, floating active inductor, Fully differential bandpass amplifier.

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Authors: K. Derradji Belloum, A. Moussi

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Most high-performance ac drives utilize a current controller. The controller switches a voltage source inverter (VSI) such that the motor current follows a set of reference current waveforms. Fixed-band hysteresis (FBH) current control has been widely used for the PWM inverter. We want to apply the same controller for the PWM AC chopper. The aims of the controller is to optimize the harmonic content at both input and output sides, while maintaining acceptable losses in the ac chopper and to control in wide range the fundamental output voltage. Fixed band controller has been simulated and analyzed for a single-phase AC chopper and are easily extended to three-phase systems. Simulation confirmed the advantages and the excellent performance of the modulation method applied for the AC chopper.

Keywords: AC chopper, Current controller, Distortion factor, Hysteresis, Input Power Factor, PWM.

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Authors: N. Ould Cherchali, A. Tlemçani, M. S. Boucherit, A. Morsli

Abstract:

Nature-inspired metaheuristic algorithms, particularly those founded on swarm intelligence, have attracted much attention over the past decade. Firefly algorithm has appeared in approximately seven years ago, its literature has enlarged considerably with different applications. It is inspired by the behavior of fireflies. The aim of this paper is the application of firefly algorithm for solving a nonlinear algebraic system. This resolution is needed to study the Selective Harmonic Eliminated Pulse Width Modulation strategy (SHEPWM) to eliminate the low order harmonics; results have been applied on multilevel inverters. The final results from simulations indicate the elimination of the low order harmonics as desired. Finally, experimental results are presented to confirm the simulation results and validate the efficaciousness of the proposed approach.

Keywords: Firefly algorithm, metaheuristic algorithm, multilelvel inverter, SHEPWM.

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Authors: Arup K. George, Wai Pan Chan, Zhi Hui Kong, Minkyu Je

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This paper describes a low-power second-order filter for a continuous-time chopper stabilized capacitive sensor interface, integrated with a fully differential post-CMOS surface-micromachined MEMS pressure sensor. The circuit uses a single-ended folded-cascode operational amplifier and two GM-C filters connected in cascade. The circuit is realized in a 0.18 μm CMOS process and offers differential to single-ended conversion. The novelty of the scheme is the cascade of two GM-C filters to achieve a second-order filter while minimizing power dissipation. The simulated filter cutoff frequency is 1.14 kHz at common-mode voltage 1.65 V, operating from a 3.3 V supply while dissipating 172μW of power. The filter achieves an operating range of 1V for an output load of 1MOhm and 10pF.

Keywords: Chopper Stabilization, MEMS, Pressure Sensors, Low Pass Filter

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Authors: Md. Asif Jahangir Chowdhury, Md. Shahriar Rizwan, M. S. Islam

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In CMOS integrated circuit design there is a trade-off between static power consumption and technology scaling. Recently, the power density has increased due to combination of higher clock speeds, greater functional integration, and smaller process geometries. As a result static power consumption is becoming more dominant. This is a challenge for the circuit designers. However, the designers do have a few methods which they can use to reduce this static power consumption. But all of these methods have some drawbacks. In order to achieve lower static power consumption, one has to sacrifice design area and circuit performance. In this paper, we propose a new method to reduce static power in the CMOS VLSI circuit using Variable Body Biasing technique without being penalized in area requirement and circuit performance.

Keywords: variable body biasing, state saving technique, stack effect, dual V-th, static power reduction.

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Authors: Morteza Fathipour, Samira Omidbakhsh, Kimia Khodayari

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RF performance of SOI CMOS device has attracted significant amount of interest recently. In order to improve RF parameters, Strained Si/Relaxed Si0.8Ge0.2 investigated as a replacement for Si technology .Enhancement of carrier mobility associated with strain engineering makes Strained Si a promising candidate for improving RF performance of CMOS technology. From the simulation, the cut-off frequency is estimated to be 224 GHZ, whereas in SOI at similar bias is about 188 GHZ. Therefore, Strained Si exhibits 19% improvement in cut-off frequency over similar Si counterpart. In this paper, Ion/Ioff ratio is studied as one of the key parameters in logic and digital application. Strained Si/SiGe demonstrates better Ion/Ioff characteristic than SOI, in similar channel length of 100 nm.Another important key analog figures of merit such as Early Voltage (VEA) ,transconductance vs drain current (gm /Ids) are studied. They introduce the efficiency of the devices to convert dc power into ac frequency.

Keywords: cut-off frequency, RF application, Silicon oninsulator, Strained Si/SiGe on insulator.

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Authors: Devin Atkin, Orly Yadid-Pecht

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The continual demands for increasing resolution and dynamic range in complimentary metal-oxide semiconductor (CMOS) image sensors have resulted in exponential increases in the amount of data that need to be read out of an image sensor, and existing readouts cannot keep up with this demand. Interesting approaches such as sparse and burst readouts have been proposed and show promise, but at considerable trade-offs in other specifications. To this end, we have begun designing and evaluating various readout topologies centered around an attempt to parallelize the sensor readout. In this paper, we have designed, simulated, and started testing a light-controlled oscillator topology with dual column and row readouts. We expect the parallel readout structure to offer greater speed and alleviate the trade-off typical in this topology, where slow pixels present a major framerate bottleneck.

Keywords: CMOS image sensors, high-speed capture, wide dynamic range, light controlled oscillator.

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Authors: S. Douss, F. Touati, M. Loulou

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A design flow of multi-standard down-conversion CMOS mixers for three modern standards: Global System Mobile, Digital Enhanced Cordless Telephone and Universal Mobile Telecommunication Systems is presented. Three active mixer-s structures are studied. The first is based on the Gilbert cell which gives a tolerable noise figure and linearity with a low conversion gain. The second and third structures use the current bleeding and charge injection techniques in order to increase the conversion gain. An improvement of about 2 dB of the conversion gain is achieved without a considerable degradation of the other characteristics. The models used for noise figure, conversion gain and IIP3 used are studied. This study describes the nature of trade-offs inherent in such structures and gives insights that help in identifying which structure is better for given conditions.

Keywords: Active mixer, Radio-frequency transceiver, Multistandardfront end, Gilbert cell, current bleeding, charge injection.

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Authors: R. Prakash, B. Meenakshipriya, R. Kumaravelan

Abstract:

Fresh water is one of the resources which is getting depleted day by day. A wise method to address this issue is by the application of renewable energy-sun irradiation and by means of decentralized, cheap, energetically self-sufficient, robust and simple to operate plants, distillates can be obtained from sea, river or even sewage. Solar desalination is a technique used to desalinate water using solar energy. The present work deals with the comprehensive design and simulation of solar tracking system using LabVIEW, temperature and mass flow rate control of the solar desalination plant using LabVIEW and also analysis of single phase inverter circuit with LC filters for solar pumping system in MATLAB. The main objective of this work is to improve the performance of solar desalination system using automatic tracking system, output control using temperature and mass flow rate control system and also to reduce the harmonic distortion in the solar pumping system by means of LC filters. The simulation of single phase inverter was carried out using MATLAB and the output waveforms were analyzed. Simulations were performed for optimum output temperature control, which in turn controls the mass flow rate of water in the thermal collectors. Solar tracking system was accomplished using LABVIEW and was tested successfully. The thermal collectors are tracked in accordance with the sun’s irradiance levels, thereby increasing the efficiency of the thermal collectors.

Keywords: Desalination, Electro dialysis, LabVIEW, MATLAB, PWM inverter, Reverse osmosis.

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Authors: Hanny H. Tumbelaka, Masafumi Miyatake

Abstract:

This paper proposes a three-phase four-wire currentcontrolled Voltage Source Inverter (CC-VSI) for both power quality improvement and PV energy extraction. For power quality improvement, the CC-VSI works as a grid current-controlling shunt active power filter to compensate for harmonic and reactive power of loads. Then, the PV array is coupled to the DC bus of the CC-VSI and supplies active power to the grid. The MPPT controller employs the particle swarm optimization technique. The output of the MPPT controller is a DC voltage that determines the DC-bus voltage according to PV maximum power. The PSO method is simple and effective especially for a partially shaded PV array. From computer simulation results, it proves that grid currents are sinusoidal and inphase with grid voltages, while the PV maximum active power is delivered to loads.

Keywords: Active Power Filter, MPPT, PV Energy Conversion.

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Authors: Yeon-kug Moon, Kang-Yoon Lee, Yun-Jae Won, Seung-Ok Lim

Abstract:

This paper describes a low-voltage and low-power channel selection analog front end with continuous-time low pass filters and highly linear programmable gain amplifier (PGA). The filters were realized as balanced Gm-C biquadratic filters to achieve a low current consumption. High linearity and a constant wide bandwidth are achieved by using a new transconductance (Gm) cell. The PGA has a voltage gain varying from 0 to 65dB, while maintaining a constant bandwidth. A filter tuning circuit that requires an accurate time base but no external components is presented. With a 1-Vrms differential input and output, the filter achieves -85dB THD and a 78dB signal-to-noise ratio. Both the filter and PGA were implemented in a 0.18um 1P6M n-well CMOS process. They consume 3.2mW from a 1.8V power supply and occupy an area of 0.19mm2.

Keywords: component ; Channel selection filters, DC offset, programmable gain amplifier, tuning circuit

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Authors: Wilfred Fritz

Abstract:

Grid connected solar PV inverters need to be compliant to standard regulations regarding unwanted harmonic generation. This paper gives an introduction to harmonics, solar PV inverter voltage regulation and balancing through compensation and investigates the behaviour of harmonic generation at different power levels. Practical measurements of harmonics and power levels with a power quality data logger were made, on a test network at a university in Germany. The test setup and test results are discussed. The major finding was that between the morning and afternoon load peak windows when the PV inverters operate under low solar insolation and low power levels, more unwanted harmonics are generated. This has a huge impact on the power quality of the grid as well as capital and maintenance costs. The design of a single-tuned harmonic filter towards harmonic mitigation is presented.

Keywords: Harmonics, power quality, pulse width modulation, total harmonic distortion.

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Authors: V. Suresh Babu, Haseena P. S., Varun P. Gopi, M. R. Baiju

Abstract:

In this paper a scheme is proposed for generating a programmable current reference which can be implemented in the CMOS technology. The current can be varied over a wide range by changing an external voltage applied to one of the control gates of FGMOS (Floating Gate MOSFET). For a range of supply voltages and temperature, CMOS current reference is found to be dependent, this dependence is compensated by subtracting two current outputs with the same dependencies on the supply voltage and temperature. The system performance is found to improve with the use of FGMOS. Mathematical analysis of the proposed circuit is done to establish supply voltage and temperature independence. Simulation and performance evaluation of the proposed current reference circuit is done using TANNER EDA Tools. The current reference shows the supply and temperature dependencies of 520 ppm/V and 312 ppm/oC, respectively. The proposed current reference can operate down to 0.9 V supply.

Keywords: Floating Gate MOSFET, current reference, self bias scheme, temperature independency, supply voltage independency.

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Authors: Ahmed Hossam-Eldin, Ahmed Elserougi, Ahmed Massoud, Shehab Ahmed

Abstract:

The Inter feeder Power Flow Regulator (IFPFR) proposed in this paper consists of several voltage source inverters with common dc bus; each inverter is connected in series with one of different independent distribution feeders in the power system. This paper is concerned with how to transfer power between the feeders for load sharing purpose. The power controller of each inverter injects the power (for sending feeder) or absorbs the power (for receiving feeder) via injecting suitable voltage; this voltage injection is simulated by voltage drop across series virtual impedance, the impedance value is selected to achieve the concept of power exchange between the feeders without perturbing the load voltage magnitude of each feeder. In this paper a new control scheme for load sharing using IFPFR is proposed.

Keywords: IFPFR, Load sharing, Power transfer

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