Search results for: CMOS Inverter

Authors: Tianchai Suksri, Satean Tunyasrirut

Abstract:

This paper presents design and implements the T-DOF PI controller design for a speed control of induction motor. The voltage source inverter type space vector pulse width modulation technique is used the drive system. This scheme leads to be able to adjust the speed of the motor by control the frequency and amplitude of the input voltage. The ratio of input stator voltage to frequency should be kept constant. The T-DOF PI controller design by root locus technique is also introduced to the system for regulates and tracking speed response. The experimental results in testing the 120 watt induction motor from no-load condition to rated condition show the effectiveness of the proposed control scheme.

Keywords: PI controller, root locus technique, space vector pulse width modulation, induction motor.

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Authors: Satean Tunyasrirut, Tianchai Suksri, Sompong Srilad

Abstract:

This paper presents design and implements a voltage source inverter type space vector pulse width modulation (SVPWM) for control a speed of induction motor. This scheme leads to be able to adjust the speed of the motor by control the frequency and amplitude of the stator voltage, the ratio of stator voltage to frequency should be kept constant. The fuzzy logic controller is also introduced to the system for keeping the motor speed to be constant when the load varies. The experimental results in testing the 0.22 kW induction motor from no-load condition to rated condition show the effectiveness of the proposed control scheme.

Keywords: Fuzzy logic control, space vector pulse width modulation, induction motor.

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Authors: P.Ramanathan, P.T.Vanathi

Abstract:

Parallel Prefix addition is a technique for improving the speed of binary addition. Due to continuing integrating intensity and the growing needs of portable devices, low-power and highperformance designs are of prime importance. The classical parallel prefix adder structures presented in the literature over the years optimize for logic depth, area, fan-out and interconnect count of logic circuits. In this paper, a new architecture for performing 8-bit, 16-bit and 32-bit Parallel Prefix addition is proposed. The proposed prefix adder structures is compared with several classical adders of same bit width in terms of power, delay and number of computational nodes. The results reveal that the proposed structures have the least power delay product when compared with its peer existing Prefix adder structures. Tanner EDA tool was used for simulating the adder designs in the TSMC 180 nm and TSMC 130 nm technologies.

Keywords: Parallel Prefix Adder (PPA), Dot operator, Semi-Dotoperator, Complementary Metal Oxide Semiconductor (CMOS), Odd-dot operator, Even-dot operator, Odd-semi-dot operator andEven-semi-dot operator.

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Authors: Bilel Gassara, Mahmoud Abdellaoui, Nouri Masmoud

Abstract:

The 4G front-end transceiver needs a high performance which can be obtained mainly with an optimal architecture and a multi-band Local Oscillator. In this study, we proposed and presented a new architecture of multi-band frequency synthesizer based on an Inverse Sine Phase Detector Phase Locked Loop (ISPD PLL) without any filters and any controlled gain block and associated with adapted multi band LC tuned VCO using a several numeric controlled capacitive branches but not binary weighted. The proposed architecture, based on 0.35μm CMOS process technology, supporting Multi-band GSM/DCS/DECT/ UMTS/WiMax application and gives a good performances: a phase noise @1MHz -127dBc and a Factor Of Merit (FOM) @ 1MHz - 186dB and a wide band frequency range (from 0.83GHz to 3.5GHz), that make the proposed architecture amenable for monolithic integration and 4G multi-band application.

Keywords: GSM/DCS/DECT/UMTS/WiMax, ISPD PLL, keep and capture range, Multi-Band, Synthesizer, Wireless.

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Authors: Guo-Ming Sung, Naga Raju Naik R.

Abstract:

Paper presents a low power, high speed, sense-amplifier based flip-flop (SAFF). The flip-flop’s power con-sumption and delay are greatly reduced by employing a new conditionally precharge sense-amplifier stage and a single-ended latch stage. Glitch-free and contention-free latch operation is achieved by using a conditional cut-off strategy. The design uses fewer transistors, has a lower clock load, and has a simple structure, all of which contribute to a near-zero setup time. When compared to previous flip-flop structures proposed for similar input/output conditions, this design’s performance and overall PDP have improved. The post layout simulation of the circuit uses 2.91µW of power and has a delay of 65.82 ps. Overall, the power-delay product has seen some enhancements. Cadence Virtuoso Designing tool with CMOS 90nm technology are used for all designs.

Keywords: high-speed, low-power, flip-flop, sense-amplifier

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Authors: Mehdi Nafar, Mohammad Reza Mansouri

Abstract:

The present research presents a direct active and reactive power control (DPC) of a wind energy conversion system (WECS) for the maximum power point tracking (MPPT) based on a doubly fed induction generator (DFIG) connected to electric power grid. The control strategy of the Rotor Side Converter (RSC) is targeted in extracting a maximum of power under fluctuating wind speed. A fuzzy logic speed controller (FLC) has been used to ensure the MPPT. The Grid Side Converter is directed in a way to ensure sinusoidal current in the grid side and a smooth DC voltage. To reduce fluctuations, rotor torque and voltage use of multilevel inverters is a good way to remove the rotor harmony.

Keywords: DFIG, power quality improvement, wind energy conversion system, WECS, fuzzy logic, RSC, GSC, inverter.

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Authors: M. Fadlallah, G. Ghibaudo, C. G. Theodorou

Abstract:

The dynamic variation in memory devices such as the Static Random Access Memory can give errors in read or write operations. In this paper, the effect of low-frequency and random telegraph noise on the dynamic variation of one SRAM cell is detailed. The effect on circuit noise, speed, and length of time of processing is examined, using the Supply Read Retention Voltage and the Read Static Noise Margin. New test run methods are also developed. The obtained results simulation shows the importance of noise caused by dynamic variation, and the impact of Random Telegraph noise on SRAM variability is examined by evaluating the statistical distributions of Random Telegraph noise amplitude in the pull-up, pull-down. The threshold voltage mismatch between neighboring cell transistors due to intrinsic fluctuations typically contributes to larger reductions in static noise margin. Also the contribution of each of the SRAM transistor to total dynamic variation has been identified.

Keywords: Low-frequency noise, Random Telegraph Noise, Dynamic Variation, SRRV.

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Authors: Wei Yi Lim, M. Annamalai Arasu, M. Kumarasamy Raja, Minkyu Je

Abstract:

In this paper, the design of wide-swing constant transconductance (g_m) bias circuit that generates bias voltage for low-noise amplifier (LNA) circuit design by using an off-chip resistor is demonstrated. The overall transconductance (G_m) generated by the constant g_m bias circuit is important to maintain the overall gain and noise figure of the LNA circuit. Therefore, investigation is performed to study the variation in G_m with process, temperature and supply voltage (PVT).  Temperature and supply voltage are swept from -10 °C to 85 °C and 1.425 V to 1.575 V respectively, while the process conditions are also varied to the extreme and the g_m variation is eventually concluded at between -3 % to 7 %. With the slight variation in the g_m value, through simulation, at worst condition of state SS, we are able to attain a conversion gain (S₂₁) variation of -3.10 % and a noise figure (NF) variation of 18.71 %. The whole constant g_m circuit draws approximately 100 µA from a 1.5V supply and is designed based on 0.13 µm CMOS process. 

Keywords: Transconductance, LNA, temperature, process.

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Authors: Jun Sung Go, Jong Kang Park, Jong Tae Kim

Abstract:

As semi-conductor manufacturing technology evolves; the single event transient problem becomes more significant issue. Single event transient has a critical impact on both combinational and sequential logic circuits, so it is important to evaluate the soft error tolerance of the circuits at the design stage. In this paper, we present a soft error detecting simulation using scan chain. The simulation model generates a single event transient randomly in the circuit, and detects the soft error during the execution of the test patterns. We verified this model by inserting a scan chain in an 8051 microprocessor using 65 nm CMOS technology. While the test patterns generated by ATPG program are passing through the scan chain, we insert a single event transient and detect the number of soft errors per sub-module. The experiments show that the soft error rates per cell area of the SFR module is 277% larger than other modules.

Keywords: Scan chain, single event transient, soft error, 8051 processor.

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Authors: Naima Ikken, Abdelhadi Bouknadel, Nour-eddine Tariba Ahmed Haddou, Hafsa El Omari

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The operation of grid-connected inverters necessity a single-phase phase locked loop (PLL) is proposed in this article to accurately and quickly estimate and detect the grid phase angle. This article presents the improvement of a method of phase-locked loop. The novelty is to generate a method (PLL) of synchronizing the grid with a Notch filter based on adaptive fuzzy logic for inverter systems connected to the grid. The performance of the proposed method was tested under normal and abnormal operating conditions (amplitude, frequency and phase shift variations). In addition, simulation results with ISPM software are developed to verify the effectiveness of the proposed method strategy. Finally, the experimental test will be used to extract the result and discuss the validity of the proposed algorithm.

Keywords: Phase locked loop, PLL, notch filter, fuzzy logic control.

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Authors: Hidir S. Nogay

Abstract:

In this study, two systems were created to predict interior temperature in induction motor. One of them consisted of a simple ANN model which has two layers, ten input parameters and one output parameter. The other one consisted of eight ANN models connected each other as cascaded. Cascaded ANN system has 17 inputs. Main reason of cascaded system being used in this study is to accomplish more accurate estimation by increasing inputs in the ANN system. Cascaded ANN system is compared with simple conventional ANN model to prove mentioned advantages. Dataset was obtained from experimental applications. Small part of the dataset was used to obtain more understandable graphs. Number of data is 329. 30% of the data was used for testing and validation. Test data and validation data were determined for each ANN model separately and reliability of each model was tested. As a result of this study, it has been understood that the cascaded ANN system produced more accurate estimates than conventional ANN model.

Keywords: Cascaded neural network, internal temperature, three-phase induction motor, inverter.

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Authors: Kittipong Tripetch, Nobuhiko Nakano

Abstract:

Two types of floating active resistors based on a complementary regulated cascode topology with cross-coupled regulated transistors are presented in this paper. The first topology is a high swing complementary regulated cascode active resistor. The second topology is a complementary common gate with a regulated cross coupled transistor. The small-signal input resistances of the floating resistors are derived. Three graphs of the input current versus the input voltage for different aspect ratios are designed and plotted using the Cadence Spectre 0.18-µm Rohm Semiconductor process. The total harmonic distortion graphs are plotted for three different aspect ratios with different input-voltage amplitudes and different input frequencies. From the simulation results, it is observed that a resistance of approximately 8.52 MΩ can be obtained from supply voltage at  ±0.9 V.

Keywords: Complementary common gate, complementary regulated cascode, current mirror, floating active resistors.

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Authors: D. Shobha Rani, M. Muralidhar

Abstract:

Solar photovoltaic (SPV) power systems can be employed as electrical power sources to meet the daily residential energy needs of rural areas that have no access to grid systems. In view of this, a standalone SPV powered air cooling system is proposed in this paper, which constitutes a dc-dc boost converter, two voltage source inverters (VSI) connected to two brushless dc (BLDC) motors which are coupled to a centrifugal water pump and a fan blower. A simple and efficient Maximum Power Point Tracking (MPPT) technique based on Silver Mean Method (SMM) is utilized in this paper. The air cooling system is developed and simulated using the MATLAB / Simulink environment considering the dynamic and steady state variation in the solar irradiance.

Keywords: Boost converter, solar photovoltaic array, voltage source inverter, brushless DC motor, solar irradiance, Maximum Power Point Tracking, Silver Mean Method.

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Authors: İres İskender, Ahmet Karaarslan

Abstract:

In this study, the performance of a high-frequency arc welding machine including a two-switch inverter is analyzed. The control of the system is achieved using two different control techniques i- fuzzy logic control (FLC) ii- state space averaging based sliding control. Fuzzy logic control does not need accurate mathematical model of a plant and can be used in nonlinear applications. The second method needs the mathematical model of the system. In this method the state space equations of the system are derived for two different “on" and “off" states of the switches. The derived state equations are combined with the sliding control rule considering the duty-cycle of the converter. The performance of the system is analyzed by simulating the system using SIMULINK tool box of MATLAB. The simulation results show that fuzzy logic controller is more robust and less sensitive to parameter variations.

Keywords: Fuzzy logic, arc welding, sliding state space control, PWM, current control.

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Authors: Chang Soo Kang, In Ho Im, Sergey Churayev, Timour Paltashev

Abstract:

This paper describes the design of new method of propagation delay measurement in micro and nanostructures during characterization of ASIC standard library cell. Providing more accuracy timing information about library cell to the design team we can improve a quality of timing analysis inside of ASIC design flow process. Also, this information could be very useful for semiconductor foundry team to make correction in technology process. By comparison of the propagation delay in the CMOS element and result of analog SPICE simulation. It was implemented as digital IP core for semiconductor manufacturing process. Specialized method helps to observe the propagation time delay in one element of the standard-cell library with up-to picoseconds accuracy and less. Thus, the special useful solutions for VLSI schematic to parameters extraction, basic cell layout verification, design simulation and verification are announced.

Keywords: phase error accumulation methodology, gatepropagation delay, Processor Testing, MEMS Testing

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Authors: Somaye Abdollahi Pour, Mohsen Saneei

Abstract:

This paper describes a novel monitoring scheme to minimize total active power in digital circuits depend on the demand frequency, by adjusting automatically both supply voltage and threshold voltages based on circuit operating conditions such as temperature, process variations, and desirable frequency. The delay monitoring results, will be control and apply so as to be maintained at the minimum value at which the chip is able to operate for a given clock frequency. Design details of power monitor are examined using simulation framework in 32nm BTPM model CMOS process. Experimental results show the overhead of proposed circuit in terms of its power consumption is about 40 μW for 32nm technology; moreover the results show that our proposed circuit design is not far sensitive to the temperature variations and also process variations. Besides, uses the simple blocks which offer good sensitivity, high speed, the continuously feedback loop. This design provides up to 40% reduction in power consumption in active mode.

Keywords: active mode, delay monitor, body biasing, VDD scaling, low power.

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Authors: E. E. El-Kholy, Ahamed Kalas, Mahmoud Fauzy, M. El-Shahat Dessouki, Abdou. M. El-Refay, Mohammed El-Zefery

Abstract:

Direct Torque Control (DTC) is an AC drive control method especially designed to provide fast and robust responses. In this paper a progressive algorithm for direct torque control of threephase induction drive system supplied by photovoltaic arrays using voltage source inverter to control motor torque and flux with maximum power point tracking at different level of insolation is presented. Experimental results of the new DTC method obtained by an experimental rapid prototype system for drives are presented. Simulation and experimental results confirm that the proposed system gives quick, robust torque and speed responses at constant switching frequencies.

Keywords: Photovoltaic (PV) array, direct torque control (DTC), constant switching frequency, induction motor, maximum power point tracking (MPPT).

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Authors: Jae-Kyung Lee, Joon-Young Park, Ki-Yong Oh, Jun-Shin Park

Abstract:

Wind turbine should be controlled to capture maximum wind energy and to prevent the turbine from being stalled. To achieve those two goals, wind turbine controller controls torque on generator and limits input torque from wind by pitching blade. Usually, torque on generator is controlled using inverter torque set point. However, verifying a control algorithm in actual wind turbine needs a lot of efforts to test and the actual wind turbine could be broken while testing a control algorithm. So, several software have developed and commercialized by Garrad Hassan, GH Bladed, and NREL, FAST. Even though, those programs can simulate control system modeling with subroutines or DLLs. However, those simulation programs are not able to emulate detailed generator or PMSG. In this paper, a small size wind turbine simulator is developed with induction motor and small size drive train. The developed system can simulate wind turbine control algorithm in the region before rated power.

Keywords: Wind turbine, simulator, wind turbine control, wind turbine torque control

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Authors: P.Tripura, Y.Srinivasa Kishore Babu

Abstract:

This paper presents an intelligent speed control system based on fuzzy logic for a voltage source PWM inverter-fed indirect vector controlled induction motor drive. Traditional indirect vector control system of induction motor introduces conventional PI regulator in outer speed loop; it is proved that the low precision of the speed regulator debases the performance of the whole system. To overcome this problem, replacement of PI controller by an intelligent controller based on fuzzy set theory is proposed. The performance of the intelligent controller has been investigated through digital simulation using MATLAB-SIMULINK package for different operating conditions such as sudden change in reference speed and load torque. The simulation results demonstrate that the performance of the proposed controller is better than that of the conventional PI controller.

Keywords: Fuzzy Logic, Intelligent controllers, Conventional PI controller, Induction motor drives, indirect vector control, Speed control

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Authors: J. Chelladurai, G. Saravana Ilango, C. Nagamani, S. Senthil Kumar

Abstract:

Pulse width modulation (PWM) techniques have been the subject of intensive research for different industrial and power sector applications. A large variety of methods, different in concept and performance, have been newly developed and described. This paper analyzes the comparative merits of Sinusoidal Pulse Width Modulation (SPWM) and Space Vector Pulse Width Modulation (SVPWM) techniques and the suitability of these techniques in a Shunt Active Filter (SAF). The objective is to select the scheme that offers effective utilization of DC bus voltage and also harmonic reduction at the input side. The effectiveness of the PWM techniques is tested in the SAF configuration with a non linear load. The performance of the SAF with the SPWM and (SVPWM) techniques are compared with respect to the THD in source current. The study reveals that in the context of closed loop SAF control with the SVPWM technique there is only a minor improvement in THD. The utilization of the DC bus with SVPWM is also not significant compared to that with SPWM because of the non sinusoidal modulating signal from the controller in SAF configuration.

Keywords: Voltage source inverter, Shunt active filter, SPWM, SVPWM, Matlab/SIMULINK.

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Authors: Aziza Benaboud, Alfred Rufer

Abstract:

In this paper the authors propose a flexible electronic solution, to improve the energetic efficiency of a thermo plant. This is achieved by replacing the mechanical gear box, placed traditionally between a gas turbine and a synchronous generator; by a power electronic converter. After reminding problematic of gear boxes and interest of a proposed electronic solution in high power plants, the authors describe a new control strategy for an indirect frequency converter, which is characterized by its high efficiency due to the use of SWM: Square Wave Modulation. The main advantage of this mode is the quasi absence of switching losses. A control method is also proposed to resolve some problems incurred by using square wave modulation, in particular to reduce the harmonics distortion of the output inverter voltage and current. Simulation examples as well as experimental results are included.

Keywords: Angle shift, high efficiency, indirect converter, gas turbine, NPC three level converter, square wave modulation SWM, switching angle.

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Authors: Jingjing Lan, Jun Yu, Muthukumaraswamy Annamalai Arasu

Abstract:

This paper presents a digital non-linear pulse-width modulation (PWM) controller in a high-voltage (HV) buck-boost DC-DC converter for the piezoelectric transducer of the down-hole acoustic telemetry system. The proposed design controls the generation of output signal with voltage higher than the supply voltage and is targeted to work under high temperature. To minimize the power consumption and silicon area, a simple and efficient design scheme is employed to develop the PWM controller. The proposed PWM controller consists of serial to parallel (S2P) converter, data assign block, a mode and duty cycle controller (MDC), linearly PWM (LPWM) and noise shaper, pulse generator and clock generator. To improve the reliability of circuit operation at higher temperature, this design is fabricated with the 1.0-μm silicon-on-insulator (SOI) CMOS process. The implementation results validated that the proposed design has the advantages of smaller size, lower power consumption and robust thermal stability.

Keywords: DC-DC power conversion, digital control, high temperatures, pulse-width modulation.

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Authors: Abdolreza Roozbeh, Reza Sedaghati, Ali Asghar Baziar, Mohammad Reza Tabatabaei

Abstract:

This paper presents dynamic models of distributed generators (DG) and investigates dynamic behavior of the DG units in the micro grid system. The DG units include photovoltaic and fuel cell sources. The voltage source inverter is adopted since the electronic interface which can be equipped with its controller to keep stability of the micro grid during small signal dynamics. This paper also introduces power management strategies and implements the DG load sharing concept to keep the micro grid operation in gridconnected and islanding modes of operation. The results demonstrate the operation and performance of the photovoltaic and fuel cell as distributed generators in a micro grid. The entire control system in the micro grid is developed by combining the benefits of the power control and the voltage control strategies. Simulation results are all reported, confirming the validity of the proposed control technique.

Keywords: Stability, Distributed Generation, Dynamic, Micro Grid.

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Authors: Vijay Kumar Sharma, Manisha Pattanaik, Balwinder Raj

Abstract:

Minimizations of power dissipation, chip area with higher circuit performance are the necessary and key parameters in deep submicron regime. The leakage current increases sharply in deep submicron regime and directly affected the power dissipation of the logic circuits. In deep submicron region the power dissipation as well as high performance is the crucial concern since increasing importance of portable systems. Number of leakage reduction techniques employed to reduce the leakage current in deep submicron region but they have some trade-off to control the leakage current. ONOFIC approach gives an excellent agreement between power dissipation and propagation delay for designing the efficient CMOS logic circuits. In this article ONOFIC approach is compared with LECTOR technique and output results show that ONOFIC approach significantly reduces the power dissipation and enhance the speed of the logic circuits. The lower power delay product is the big outcome of this approach and makes it an influential leakage reduction technique.

Keywords: Deep submicron, Leakage Current, LECTOR, ONOFIC, Power Delay Product

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Authors: Shreyash Sinai Kunde, Siddhang Tendulkar, Shiv Prakash Gupta, Gaurav Kumar, Suresh Mikkili

Abstract:

One of the major power quality concerns in modern times is the problem of current harmonics. The current harmonics is caused due to the increase in non-linear loads which is largely dominated by power electronics devices. The Shunt active filtering is one of the best solutions for mitigating current harmonics. This paper describes a fuzzy logic controller based (FLC) based three Phase Shunt active Filter to achieve low current harmonic distortion (THD) and Reactive power compensation. The performance of fuzzy logic controller is analysed under both balanced sinusoidal and unbalanced sinusoidal source condition. The above controller serves the purpose of maintaining DC Capacitor Voltage constant. The proposed shunt active filter uses hysteresis current controller for current control of IGBT based PWM inverter. The simulation results of model in Simulink MATLAB reveals satisfying results.

Keywords: Shunt active filter, Current harmonics, Fuzzy logic controller, Hysteresis current controller.

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Authors: Arash Azizi Mazreah, Mohammad T. Manzuri Shalmani, Hamid Barati, Ali Barati, Ali Sarchami

Abstract:

This paper proposes a low power SRAM based on five transistor SRAM cell. Proposed SRAM uses novel word-line decoding such that, during read/write operation, only selected cell connected to bit-line whereas, in conventional SRAM (CV-SRAM), all cells in selected row connected to their bit-lines, which in turn develops differential voltages across all bit-lines, and this makes energy consumption on unselected bit-lines. In proposed SRAM memory array divided into two halves and this causes data-line capacitance to reduce. Also proposed SRAM uses one bit-line and thus has lower bit-line leakage compared to CV-SRAM. Furthermore, the proposed SRAM incurs no area overhead, and has comparable read/write performance versus the CV-SRAM. Simulation results in standard 0.25μm CMOS technology shows in worst case proposed SRAM has 80% smaller dynamic energy consumption in each cycle compared to CV-SRAM. Besides, energy consumption in each cycle of proposed SRAM and CV-SRAM investigated analytically, the results of which are in good agreement with the simulation results.

Keywords: SRAM, write Operation, read Operation, capacitances, dynamic energy consumption.

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Authors: P. Santiprapan, K-L. Areerak, K-N. Areerak

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This paper presents the mathematical model and control strategy on DQ frame of shunt active power filter. The structure of the shunt active power filter is the voltage source inverter (VSI). The pulse width modulation (PWM) with PI controller is used in the paper. The concept of DQ frame to apply with the shunt active power filter is described. Moreover, the detail of the PI controller design for two current loops and one voltage loop are fully explained. The DQ axis with Fourier (DQF) method is applied to calculate the reference currents on DQ frame. The simulation results show that the control strategy and the design method presented in the paper can provide the good performance of the shunt active power filter. Moreover, the %THD of the source currents after compensation can follow the IEEE Std.519-1992.

Keywords: shunt active power filter, mathematical model, DQ control strategy, DQ axis with Fourier, pulse width modulation control.

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Authors: N. Janjamraj, A. Oonsivilai

Abstract:

This paper present the harmonic elimination of hybrid multilevel inverters (HMI) which could be increase the number of output voltage level. Total Harmonic Distortion (THD) is one of the most important requirements concerning performance indices. Because of many numbers output levels of HMI, it had numerous unknown variables of eliminate undesired individual harmonic and THD nonlinear equations set. Optimized harmonic stepped waveform (OHSW) is solving switching angles conventional method, but most complicated for solving as added level. The artificial intelligent techniques are deliberation to solve this problem. This paper presents the Particle Swarm Optimization (PSO) technique for solving switching angles to get minimum THD and eliminate undesired individual harmonics of 15-levels hybrid multilevel inverters. Consequently it had many variables and could eliminate numerous harmonics. Both advantages including high level of inverter and Particle Swarm Optimization (PSO) are used as powerful tools for harmonics elimination.

Keywords: Multilevel Inverters, Particle Swarms Optimization, Harmonic Elimination.

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Authors: Jie Jin

Abstract:

In this paper, a new CMOS current-mode single input and multi-outputs (SIMO) universal filter and quadrature oscillator with a similar circuit are proposed. The circuits only consist of three Current differencing transconductance amplifiers (CDTA) and two grounded capacitors, which are resistorless, and they are suitable for monolithic integration. The universal filter uses minimum CDTAs and passive elements to realize SIMO type low-pass (LP), high-pass (HP), band-pass (BP) band-stop (BS) and all-pass (AP) filter functions simultaneously without any component matching conditions. The angular frequency (ω0) and the quality factor (Q) of the proposed filter can be electronically controlled and tuned orthogonal. By some modifications of the filter, a new current-mode four-phase quadrature oscillator (QO) can be obtained easily. The condition of oscillation (CO) and frequency of oscillation (FO) of the QO can be controlled electronically and independently through the bias current of the CDTAs, and it is suitable for variable frequency oscillator. Moreover, all the passive and active sensitivities of the circuits are low. SPICE simulation results are included to confirm the theory.

Keywords: Universal Filter, Quadrature Oscillator, Current mode, Current differencing transconductance amplifiers.

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Authors: T. Patrice Nna Nna, S. Ndjakomo Essiane, S. Pérabi Ngoffé, F. Amigue Fissou

Abstract:

This paper deals with the harmonic decontamination of current in an electrical grid by an active shunt filter in order to improve power quality. The contribution of this paper is mainly based on the proposal of a control strategy for an active filter based on Duty Cycle Modulation (DCM). First, three-monophase method is applied for the identification of disturbing currents. A Simulink model of this method is given for one phase of the grid. Secondly, two orders were designed: the first one is the Hysteresis Control and the second one is the DCM Control. Finally, a comparative study of the two controls was performed. The results obtained show a significant improvement in the rate of harmonic distortion for both controls. The harmonic distortion for the Hysteresis control is limited by the non-controllability of the switching frequencies of the inverter's switches and reduces the harmonic distortion rate (THD) to 3.12% as opposed to the DCM control which limits the THD to 2.82% which makes it better.

Keywords: Harmonic pollution, shunt active filter, hysteresis, Duty Cycle Modulation.

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