@article{(Open Science Index):https://publications.waset.org/pdf/15803,
	  title     = {Phase Error Accumulation Methodology for On-Chip Cell Characterization},
	  author    = {Chang Soo Kang and  In Ho Im and  Sergey Churayev and  Timour Paltashev},
	  country	= {},
	  institution	= {},
	  abstract     = {This paper describes the design of new method of
propagation delay measurement in micro and nanostructures during
characterization of ASIC standard library cell. Providing more
accuracy timing information about library cell to the design team we
can improve a quality of timing analysis inside of ASIC design flow
process. Also, this information could be very useful for semiconductor
foundry team to make correction in technology process. By
comparison of the propagation delay in the CMOS element and result
of analog SPICE simulation. It was implemented as digital IP core for
semiconductor manufacturing process. Specialized method helps to
observe the propagation time delay in one element of the standard-cell
library with up-to picoseconds accuracy and less. Thus, the special
useful solutions for VLSI schematic to parameters extraction, basic
cell layout verification, design simulation and verification are
	    journal   = {International Journal of Electronics and Communication Engineering},
	  volume    = {5},
	  number    = {7},
	  year      = {2011},
	  pages     = {797 - 800},
	  ee        = {https://publications.waset.org/pdf/15803},
	  url   	= {https://publications.waset.org/vol/55},
	  bibsource = {https://publications.waset.org/},
	  issn  	= {eISSN: 1307-6892},
	  publisher = {World Academy of Science, Engineering and Technology},
	  index 	= {Open Science Index 55, 2011},