Search results for: Analog circuits
Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 333

Search results for: Analog circuits

183 Low Power Low Voltage Current Mode Pipelined A/D Converters

Authors: Krzysztof Wawryn, Robert Suszyński, Bogdan Strzeszewski

Abstract:

This paper presents two prototypes of low power low voltage current mode 9 bit pipelined a/d converters. The first and the second converters are configured of 1.5 bit and 2.5 bit stages, respectively. The a/d converter structures are composed of current mode building blocks and final comparator block which converts the analog current signal into digital voltage signal. All building blocks have been designed in CMOS AMS 0.35μm technology, then simulated to verify proposed concept. The performances of both converters are compared to performances of known current mode and voltage mode switched capacitance converter structures. Low power consumption and small chip area are advantages of the proposed converters.

Keywords: Pipelined converter, a/d converter, low power, lowvoltage, current mode.

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182 Development of Autonomous Line-Following Soccer Robots

Authors: A. A. Shafie, M. F. Alias, M. H. Ali

Abstract:

The main objective of this project is to build an autonomous microcontroller-based mobile robot for a local robot soccer competition. The black competition field is equipped with white lines to serve as the guidance path for competing robots. Two prototypes of soccer robot embedded with the Basic Stamp II microcontroller have been developed. Two servo motors are used as the drive train for the first prototype whereas the second prototype uses two DC motors as its drive train. To sense the lines, lightdependent resistors (LDRs) supply the analog inputs for the microcontroller. The performances of both prototypes are evaluated. The DC motor-driven robot has produced better trajectory control over the one using servo motors and has brought the team into the final round.

Keywords: Soccer robot, Obstacle detection, Differential drive, Line following.

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181 A ±0.5V BiCMOS Class-A Current Conveyor

Authors: Subodh Thankachan, Manisha Pattanaik, S. S. Rajput

Abstract:

In this paper, a new BiCMOS CCII and CCCII, capable of operate at ±0.5V and having wide dynamic range with achieved bandwidth of 480MHz and 430MHz respectively have been proposed. The structures have been found to be insensitive to the threshold voltage variations. The proposed circuits are suitable for implementation using 0.25μm BiCMOS technology. Pspice simulations confirm the performance of the proposed structures.

Keywords: BiCMOS, Current conveyor, Compound current conveyor, Low supply voltage, Threshold voltage variation.

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180 Memristor: The Missing Circuit Element and its Application

Authors: Vishnu Pratap Singh Kirar

Abstract:

Memristor is also known as the fourth fundamental passive circuit element. When current flows in one direction through the device, the electrical resistance increases and when current flows in the opposite direction, the resistance decreases. When the current is stopped, the component retains the last resistance that it had, and when the flow of charge starts again, the resistance of the circuit will be what it was when it was last active. It behaves as a nonlinear resistor with memory. Recently memristors have generated wide research interest and have found many applications. In this paper we survey the various applications of memristors which include non volatile memory, nanoelectronic memories, computer logic, neuromorphic computer architectures low power remote sensing applications, crossbar latches as transistor replacements, analog computations and switches.

Keywords: Memristor, non-volatile memory, arithmatic operation, programmable resistor.

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179 Practical Simulation Model of Floating-Gate MOS Transistor in Sub 100nm Technologies

Authors: Zina Saheb, Ezz El-Masry

Abstract:

As the Silicon oxide scaled down in MOSFET technology to few nanometers, gate Direct Tunneling (DT) in Floating gate (FGMOSFET) devices has become a major concern for analog designers. FGMOSFET has been used in many low-voltage and low-power applications, however, there is no accurate model that account for DT gate leakage in nano-scale. This paper studied and analyzed different simulation models for FGMOSFET using TSMC 90-nm technology. The simulation results for FGMOSFET cascade current mirror shows the impact of DT on circuit performance in terms of current and voltage without the need for fabrication. This works shows the significance of using an accurate model for FGMOSFET in nan-scale technologies.

Keywords: CMOS transistor, direct-tunneling current, floatinggate, gate-leakage current, simulation model.

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178 Development of a Real Time Axial Force Measurement System and IoT-Based Monitoring for Smart Bearing

Authors: Hassam Ahmed, Yuanzhi Liu, Yassine Selami, Wei Tao, Hui Zhao

Abstract:

The purpose of this research is to develop a real time axial force measurement system for a smart bearing through the use of strain-gauges, whereby the data acquisition is performed by an Arduino microcontroller due to its easy manipulation and low-cost. The measured signal is acquired and then discretized using a Wheatstone Bridge and an Analog-Digital Converter (ADC) respectively. For bearing monitoring, a real time monitoring system based on Internet of things (IoT) and Bluetooth were developed. Experimental tests were performed on a bearing within a force range up to 600 kN. The experimental results show that there is a proportional linear relationship between the applied force and the output voltage, and the error R squared is within 0.9878 based on the regression analysis.

Keywords: Bearing, force measurement, IoT, strain gauge.

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177 Impairments Correction of Six-Port Based Millimeter-Wave Radar

Authors: Dan Ohev Zion, Alon Cohen

Abstract:

In recent years, the presence of short-range millimeter-wave radar in civil application has increased significantly. Autonomous driving, security, 3D imaging and high data rate communication systems are a few examples. The next challenge is the integration inside small form-factor devices, such as smartphones (e.g. gesture recognition). The main challenge is implementation of a truly low-power, low-complexity high-resolution radar. The most popular approach is the Frequency Modulated Continuous Wave (FMCW) radar, with an analog multiplication front-end. In this paper, we present an approach for adaptive estimation and correction of impairments of such front-end, specifically implemented using the Six-Port Device (SPD) as the multiplier element. The proposed algorithm was simulated and implemented on a 60 GHz radar lab prototype.

Keywords: Radar, millimeter-wave, six-port, FMCW Radar, IQ mismatch.

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176 An Area-Efficient and Low-Power Digital Pulse-Width Modulation Controller for DC-DC Switching Power Converter

Authors: Jingjing Lan, Jun Zhou, Xin Liu

Abstract:

In this paper, a low-power digital controller for DC-DC power conversion was presented. The controller generates the pulse-width modulated (PWM) signal from digital inputs provided by analog-to-digital converter (ADC). An efficient and simple design scheme to develop the control unit was discussed. This method allows minimization of the consumed resources of the chip and it is based on direct digital design approach. In this application, with the proposed scheme, nearly half area and two-third of the power consumption was saved compared to the conventional schemes. This work illustrates the possibility of implementing low-power and area-efficient power management circuit using direct digital design based approach. 

Keywords: Buck converter, DC-DC power conversion, digital control, proportional-integral (PI) controller.

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175 A Design of Electronically Tunable Voltagemode Universal Filter with High Input Impedance

Authors: Surapong Siripongdee, Witthaya Mekhum

Abstract:

This article presents a voltage-mode universal biquadratic filter performing simultaneous 3 standard functions: lowpass, high-pass and band-pass functions, employing differential different current conveyor (DDCC) and current controlled current conveyor (CCCII) as active element. The features of the circuit are that: the quality factor and pole frequency can be tuned independently via the input bias currents: the circuit description is very simple, consisting of 1 DDCC, 2 CCCIIs, 2 electronic resistors and 2 grounded capacitors. Without requiring component matching conditions, the proposed circuit is very appropriate to further develop into an integrated circuit. The PSPICE simulation results are depicted. The given results agree well with the theoretical anticipation.

Keywords: Filter, DDCC, CCCII, Analog circuit, Voltagemode, PSPICE

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174 Pulse Generator with Constant Pulse Width

Authors: Hanif Che Lah, Wee Leong Son, Rozita Borhan

Abstract:

This paper is about method to produce a stable and accurate constant output pulse width regardless of the amplitude, period and pulse width variation of the input signal source. The pulse generated is usually being used in numerous applications as the reference input source to other circuits in the system. Therefore, it is crucial to produce a clean and constant pulse width to make sure the system is working accurately as expected.

Keywords: Amplitude, Constant Pulse Width, Frequency Divider, Pulse Generator.

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173 A Hyper-Domain Image Watermarking Method based on Macro Edge Block and Wavelet Transform for Digital Signal Processor

Authors: Yi-Pin Hsu, Shin-Yu Lin

Abstract:

In order to protect original data, watermarking is first consideration direction for digital information copyright. In addition, to achieve high quality image, the algorithm maybe can not run on embedded system because the computation is very complexity. However, almost nowadays algorithms need to build on consumer production because integrator circuit has a huge progress and cheap price. In this paper, we propose a novel algorithm which efficient inserts watermarking on digital image and very easy to implement on digital signal processor. In further, we select a general and cheap digital signal processor which is made by analog device company to fit consumer application. The experimental results show that the image quality by watermarking insertion can achieve 46 dB can be accepted in human vision and can real-time execute on digital signal processor.

Keywords: watermarking, digital signal processor, embedded system

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172 Matrix Based Synthesis of EXOR dominated Combinational Logic for Low Power

Authors: Padmanabhan Balasubramanian, C. Hari Narayanan

Abstract:

This paper discusses a new, systematic approach to the synthesis of a NP-hard class of non-regenerative Boolean networks, described by FON[FOFF]={mi}[{Mi}], where for every mj[Mj]∈{mi}[{Mi}], there exists another mk[Mk]∈{mi}[{Mi}], such that their Hamming distance HD(mj, mk)=HD(Mj, Mk)=O(n), (where 'n' represents the number of distinct primary inputs). The method automatically ensures exact minimization for certain important selfdual functions with 2n-1 points in its one-set. The elements meant for grouping are determined from a newly proposed weighted incidence matrix. Then the binary value corresponding to the candidate pair is correlated with the proposed binary value matrix to enable direct synthesis. We recommend algebraic factorization operations as a post processing step to enable reduction in literal count. The algorithm can be implemented in any high level language and achieves best cost optimization for the problem dealt with, irrespective of the number of inputs. For other cases, the method is iterated to subsequently reduce it to a problem of O(n-1), O(n-2),.... and then solved. In addition, it leads to optimal results for problems exhibiting higher degree of adjacency, with a different interpretation of the heuristic, and the results are comparable with other methods. In terms of literal cost, at the technology independent stage, the circuits synthesized using our algorithm enabled net savings over AOI (AND-OR-Invert) logic, AND-EXOR logic (EXOR Sum-of- Products or ESOP forms) and AND-OR-EXOR logic by 45.57%, 41.78% and 41.78% respectively for the various problems. Circuit level simulations were performed for a wide variety of case studies at 3.3V and 2.5V supply to validate the performance of the proposed method and the quality of the resulting synthesized circuits at two different voltage corners. Power estimation was carried out for a 0.35micron TSMC CMOS process technology. In comparison with AOI logic, the proposed method enabled mean savings in power by 42.46%. With respect to AND-EXOR logic, the proposed method yielded power savings to the tune of 31.88%, while in comparison with AND-OR-EXOR level networks; average power savings of 33.23% was obtained.

Keywords: AOI logic, ESOP, AND-OR-EXOR, Incidencematrix, Hamming distance.

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171 Automatic Deactivation in Phased Array Probe for Human Prostate Magnetic Resonance Imaging at 1.5T

Authors: Fotios N. Vlachos, Anastasios D. Garetsos, Nikolaos K. Uzunoglu, Efstathios D. Gotsis

Abstract:

A four element prototype phased array surface probe has been designed and constructed to improve clinical human prostate spectroscopic data. The probe consists of two pairs of adjacent rectangular coils with an optimum overlap to reduce the mutual inductance. The two pairs are positioned on the anterior and the posterior pelvic region and two couples of varactors at the input of each coil undertake the procedures of tuning and matching. The probe switches off and on automatically during the consecutive phases of the MR experiment with the use of an analog switch that is triggered by a microcontroller. Experimental tests that were carried out resulted in high levels of tuning accuracy. Also, the switching mechanism functions properly for various applied loads and pulse sequence characteristics, producing only 10 μs of latency.

Keywords: Automatic tuning, prostate imaging, phased array, spectroscopy.

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170 A Novel Interpolation Scheme and Apparatus to Extend DAC Usable Spectrum over Nyquist Frequency

Authors: Wang liguo, Wang zongmin, Kong ying

Abstract:

A novel interpolation scheme to extend usable spectrum and upconvert in high performance D/A converters is addressed in this paper. By adjusting the pulse width of cycle and the production circuit of code, the expansion code is a null code or complementary code that is interpolation process. What the times and codes of interpolation decide DAC works in one of a normal mode or multi-mixer mode so that convert the input digital data signal into normal signal or a mixed analog signal having a mixer frequency that is higher than the data frequency. Simulation results show that the novel scheme and apparatus most extend the usable frequency spectrum into fifth to sixth Nyquist zone beyond conventional DACs.

Keywords: interpolation, upconversion, modulation, switching function, duty cycle.

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169 Computation of Natural Logarithm Using Abstract Chemical Reaction Networks

Authors: Iuliia Zarubiieva, Joyun Tseng, Vishwesh Kulkarni

Abstract:

Recent researches has focused on nucleic acids as a substrate for designing biomolecular circuits for in situ monitoring and control. A common approach is to express them by a set of idealised abstract chemical reaction networks (ACRNs). Here, we present new results on how abstract chemical reactions, viz., catalysis, annihilation and degradation, can be used to implement circuit that accurately computes logarithm function using the method of Arithmetic-Geometric Mean (AGM), which has not been previously used in conjunction with ACRNs.

Keywords: Abstract chemical reaction network, DNA strand displacement, natural logarithm.

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168 Classification Based on Deep Neural Cellular Automata Model

Authors: Yasser F. Hassan

Abstract:

Deep learning structure is a branch of machine learning science and greet achievement in research and applications. Cellular neural networks are regarded as array of nonlinear analog processors called cells connected in a way allowing parallel computations. The paper discusses how to use deep learning structure for representing neural cellular automata model. The proposed learning technique in cellular automata model will be examined from structure of deep learning. A deep automata neural cellular system modifies each neuron based on the behavior of the individual and its decision as a result of multi-level deep structure learning. The paper will present the architecture of the model and the results of simulation of approach are given. Results from the implementation enrich deep neural cellular automata system and shed a light on concept formulation of the model and the learning in it.

Keywords: Cellular automata, neural cellular automata, deep learning, classification.

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167 Design of a Novel Fractal Multiband Planar Antenna with a CPW-Feed

Authors: T. Benyetho, L. El Abdellaoui, J. Terhzaz, H. Bennis, N. Ababssi, A. Tajmouati, A. Tribak, M. Latrach

Abstract:

This work presents a new planar multiband antenna based on fractal geometry. This structure is optimized and validated into simulation by using CST-MW Studio. To feed this antenna we have used a CPW line which makes it easy to be incorporated with integrated circuits. The simulation results presents a good matching input impedance and radiation pattern in the GSM band at 900 MHz and ISM band at 2.4 GHz. The final structure is a dual band fractal antenna with 70 x 70 mm² as a total area by using an FR4 substrate.

Keywords: Antenna, CPW, Fractal, GSM, Multiband.

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166 High-Speed Pipeline Implementation of Radix-2 DIF Algorithm

Authors: Christos Meletis, Paul Bougas, George Economakos , Paraskevas Kalivas, Kiamal Pekmestzi

Abstract:

In this paper, we propose a new architecture for the implementation of the N-point Fast Fourier Transform (FFT), based on the Radix-2 Decimation in Frequency algorithm. This architecture is based on a pipeline circuit that can process a stream of samples and produce two FFT transform samples every clock cycle. Compared to existing implementations the architecture proposed achieves double processing speed using the same circuit complexity.

Keywords: Digital signal processing, systolic circuits, FFTalgorithm.

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165 An Investigation of Direct and Indirect Geo-Referencing Techniques on the Accuracy of Points in Photogrammetry

Authors: F. Yildiz, S. Y. Oturanc

Abstract:

Advances technology in the field of photogrammetry replaces analog cameras with reflection on aircraft GPS/IMU system with a digital aerial camera. In this system, when determining the position of the camera with the GPS, camera rotations are also determined by the IMU systems. All around the world, digital aerial cameras have been used for the photogrammetry applications in the last ten years. In this way, in terms of the work done in photogrammetry it is possible to use time effectively, costs to be reduced to a minimum level, the opportunity to make fast and accurate. Geo-referencing techniques that are the cornerstone of the GPS / INS systems, photogrammetric triangulation of images required for balancing (interior and exterior orientation) brings flexibility to the process. Also geo-referencing process; needed in the application of photogrammetry targets to help to reduce the number of ground control points. In this study, the use of direct and indirect georeferencing techniques on the accuracy of the points was investigated in the production of photogrammetric mapping.

Keywords: Photogrammetry, GPS/IMU Systems, Geo- Referencing.

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164 Wireless Communicated Smart Wind Sensor

Authors: Zdenek Bohuslavek

Abstract:

Development of microprocessor controlled sensor for measurement of wind speed and direction is the aim of this study. Electrical circuits and software were developed to the existing electromechanical part of the sensor TM-W2 becoming the properties of so-called smart sensor. The measured data about wind speed (sensitivity 0.01 m/s) and direction (0-360° by step 10°) are transmitted as 16-bit information. The connection between sensor and control unit is realized by radio communication (FM 433 MHz). Transition range is 220 m if used Quad type antenna. This concept provides substitution of actual cable systems by wireless ones.

Keywords: smart wind sensor, anemometer, wind speed, wireless communication

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163 Formulation, Analysis and Validation of Takagi-Sugeno Fuzzy Modeling For Robotic Monipulators

Authors: Rafael Jorge Menezes Santos, Ginalber Luiz de Oliveira Serra, Carlos César Teixeira Ferreira

Abstract:

This paper proposes a methodology for analysis of the dynamic behavior of a robotic manipulator in continuous time. Initially this system (nonlinear system) will be decomposed into linear submodels and analyzed in the context of the Linear and Parameter Varying (LPV) Systems. The obtained linear submodels, which represent the local dynamic behavior of the robotic manipulator in some operating points were grouped in a Takagi-Sugeno fuzzy structure. The obtained fuzzy model was analyzed and validated through analog simulation, as universal approximator of the robotic manipulator.

Keywords: modeling of nonlinear dynamic systems, Takagi- Sugeno fuzzy model, Linear and Parameter Varying (LPV) System.

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162 Maximizing Sum-Rate for Multi-User Two-Way Relaying Networks with ANC Protocol

Authors: Muhammad Abrar, Xiang Gui, Amal Punchihewa

Abstract:

In this paper we study the resource allocation problem for an OFDMA based cooperative two-way relaying (TWR) network. We focus on amplify and forward (AF) analog network coding (ANC) protocol. An optimization problem for two basic resources namely, sub-carrier and power is formulated for multi-user TWR networks. A joint optimal optimization problem is investigated and two-step low complexity sub-optimal resource allocation algorithm is proposed for multi-user TWR networks with ANC protocol. The proposed algorithm has been evaluated in term of total achievable system sum-rate and achievable individual sum-rate for each userpair. The good tradeoff between system sum-rate and fairness is observed in the two-step proportional resource allocation scheme.

Keywords: Relay Network, Relay Protocols, Resource Allocation, Two –way relaying.

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161 Comparison of the DC/DC-Converters for Fuel Cell Applications

Authors: Oleksandr Krykunov

Abstract:

The source voltage of high-power fuel cell shows strong load dependence at comparatively low voltage levels. In order to provide the voltage of 750V on the DC-link for feeding electrical energy into the mains via a three phase inverter a step-up converter with a large step-up ratio is required. The output voltage of this DC/DC-converter must be stabile during variations of the load current and the voltage of the fuel cell. This paper presents the methods and results of the calculation of the efficiency and the expense for the realization for the circuits of the DC/DC-converter that meet these requirements.

Keywords: DC/DC-converter, calculation, efficiency, fuel cell.

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160 Optimal Criteria for Non-Minimal Phase Plants

Authors: Z. Nemec, R. Matousek

Abstract:

The paper describes the evaluation of quality of control for cases of controlled non-minimal phase plants. Control circuits containing non-minimal phase plants have different properties, they manifest reversed reaction at the beginning of unit step response. For these types of plants are developed special criterion of quality of control, which considers the difference and can be helpful for synthesis of optimal controller tuning. All results are clearly presented using Matlab/Simulink models.

Keywords: control design, non-minimal phase system, optimalcriteria, power plant, heating plant, water turbine, Matlab, Simulink.

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159 Highly Linear and Low Noise AMR Sensor Using Closed Loop and Signal-Chopped Architecture

Authors: N. Hadjigeorgiou, A. C. Tsalikidou, E. Hristoforou, P. P. Sotiriadis

Abstract:

During the last few decades, the continuously increasing demand for accurate and reliable magnetic measurements has paved the way for the development of different types of magnetic sensing systems as well as different measurement techniques. Sensor sensitivity and linearity, signal-to-noise ratio, measurement range, cross-talk between sensors in multi-sensor applications are only some of the aspects that have been examined in the past. In this paper, a fully analog closed loop system in order to optimize the performance of AMR sensors has been developed. The operation of the proposed system has been tested using a Helmholtz coil calibration setup in order to control both the amplitude and direction of magnetic field in the vicinity of the AMR sensor. Experimental testing indicated that improved linearity of sensor response, as well as low noise levels can be achieved, when the system is employed.

Keywords: AMR sensor, closed loop, memory effects, chopper, linearity improvement, sensitivity improvement, magnetic noise, electronic noise.

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158 Simulation of Voltage Controlled Tunable All Pass Filter Using LM13700 OTA

Authors: Bhaba Priyo Das, Neville Watson, Yonghe Liu

Abstract:

In recent years Operational Transconductance Amplifier based high frequency integrated circuits, filters and systems have been widely investigated. The usefulness of OTAs over conventional OP-Amps in the design of both first order and second order active filters are well documented. This paper discusses some of the tunability issues using the Matlab/Simulink® software which are previously unreported for any commercial OTA. Using the simulation results two first order voltage controlled all pass filters with phase tuning capability are proposed.

Keywords: All pass filter, Operational Transconductance Amplifier, Simulation.

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157 A Processor with Dynamically Reconfigurable Circuit for Floating-Point Arithmetic

Authors: Yukinari Minagi , Akinori Kanasugi

Abstract:

This paper describes about dynamic reconfiguration to miniaturize arithmetic circuits in general-purpose processor. Dynamic reconfiguration is a technique to realize required functions by changing hardware construction during operation. The proposed arithmetic circuit performs floating-point arithmetic which is frequently used in science and technology. The data format is floating-point based on IEEE754. The proposed circuit is designed using VHDL, and verified the correct operation by simulations and experiments.

Keywords: dynamic reconfiguration, floating-point arithmetic, double precision, FPGA

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156 Non-Isolated Direct AC-DC Converter Design with BCM-PFC Circuit

Authors: Y. Kobori, L. Xing, H. Gao, N.Onozawa, S. Wu, S. N. Mohyar, Z. Nosker, H. Kobayashi, N. Takai, K. Niitsu

Abstract:

This paper proposes two types of non-isolated direct AC-DC converters. First, it shows a buck-boost converter with an H-bridge, which requires few components (three switches, two diodes, one inductor and one capacitor) to convert AC input to DC output directly. This circuit can handle a wide range of output voltage. Second, a direct AC-DC buck converter is proposed for lower output voltage applications. This circuit is analyzed with output voltage of 12V. We describe circuit topologies, operation principles and simulation results for both circuits.

Keywords: AC-DC converter, Buck-boost converter, Buck converter, PFC, BCM PFC circuit.

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155 Frequency Transformation with Pascal Matrix Equations

Authors: Phuoc Si Nguyen

Abstract:

Frequency transformation with Pascal matrix equations is a method for transforming an electronic filter (analogue or digital) into another filter. The technique is based on frequency transformation in the s-domain, bilinear z-transform with pre-warping frequency, inverse bilinear transformation and a very useful application of the Pascal’s triangle that simplifies computing and enables calculation by hand when transforming from one filter to another. This paper will introduce two methods to transform a filter into a digital filter: frequency transformation from the s-domain into the z-domain; and frequency transformation in the z-domain. Further, two Pascal matrix equations are derived: an analogue to digital filter Pascal matrix equation and a digital to digital filter Pascal matrix equation. These are used to design a desired digital filter from a given filter.

Keywords: Frequency transformation, Bilinear z-transformation, Pre-warping frequency, Digital filters, Analog filters, Pascal’s triangle.

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154 Designing of Full Adder Using Low Power Techniques

Authors: Shashank Gautam

Abstract:

This paper proposes techniques like MT CMOS, POWER GATING, DUAL STACK, GALEOR and LECTOR to reduce the leakage power. A Full Adder has been designed using these techniques and power dissipation is calculated and is compared with general CMOS logic of Full Adder. Simulation results show the validity of the proposed techniques is effective to save power dissipation and to increase the speed of operation of the circuits to a large extent.

Keywords: Low Power, MT CMOS, Galeor, Lector, Power Gating, Dual Stack, Full Adder.

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