Search results for: 0.18μm CMOS technology.

Authors: Seongykyoon Jeong, Sungki Lee, Jaeyun Kim, Seunghun Oh, Kiho Kwak

Abstract:

The purpose of study is to demonstrate how the characteristics of technology and the process required for development of technology affect technology transfer from public organisations to industry on the technology level. In addition, using the advantage of the analytic level and the novel means of measuring technology convergence, we examine the characteristics of converging technologies as compared to non-converging technologies in technology transfer process. In sum, our study finds that a technology from the public sector is likely to be transferred when its readiness level is closer to generation of profit, when its stage of life cycle is early and when its economic values is high. Our findings also show that converging technologies are less likely to be transferred.

Keywords: Interdisciplinary, Technology transfer, Technology convergence.

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Authors: Hasmayadi Abdul Majid, Rohana Musa

Abstract:

This paper presents the development of a 38.5 kS/s 10-bit low power SAR ADC which is realized in MIMOS’s 0.35 µm CMOS process. The design uses a resistive DAC, a dynamic comparator with pre-amplifier and SAR digital logic to create 10 effective bits while consuming less than 7.8 mW with a 3.3 V power supply.

Keywords: Successive Approximation Register Analog-to- Digital Converter, SAR ADC, Resistive DAC.

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Authors: S. Kumaravel, B. Venkataramani

Abstract:

In the literature, Improved Recycling Folded Cascode (IRFC) Operational Transconductance Amplifier (OTA) is proposed for enhancing the DC gain and the Unity Gain Bandwidth (UGB) of the Recycling Folded Cascode (RFC) OTA. In this paper, an enhanced IRFC (EIRFC) OTA which uses positive feedback at the cascode node is proposed for enhancing the differential mode (DM) gain without changing the unity gain bandwidth (UGB) and lowering the Common mode (CM) gain. For the purpose of comparison, IRFC and EIRFC OTAs are implemented using UMC 90nm CMOS technology and studied through simulation. From the simulation, it is found that the DM gain and CM gain of EIRFC OTA is higher by 6dB and lower by 38dB respectively, compared to that of IRFC OTA for the same power and area. The slew rate of EIRFC OTA is also higher by a factor of 1.5.

Keywords: Cascode Amplifier, CMRR, gm/ID Methodology, Recycling, Slew Rate.

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Authors: Kah-Hyong Chang, Xin Liu, Jia Hao Cheong, Saisundar Sankaranarayanan, Dexing Pang, Hongzhao Zheng

Abstract:

A digital baseband Application-Specific Integrated Circuit (ASIC) (yclic Redundancy Checkis developed for a microchip transponder to transmit signals and temperature levels from biomedical monitoring devices. The transmission protocol is adapted from the ISO/IEC 11784/85 standard. The module has a decimation filter that employs only a single adder-subtractor in its datapath. The filtered output is coded with cyclic redundancy check and transmitted through backscattering Load Shift Keying (LSK) modulation to a reader. Fabricated using the 0.18-μm CMOS technology, the module occupies 0.116 mm² in chip area (digital baseband: 0.060 mm², decimation filter: 0.056 mm²), and consumes a total of less than 0.9 μW of power (digital baseband: 0.75 μW, decimation filter: 0.14 μW).

Keywords: Biomedical sensor, decimation filter, Radio Frequency Integrated Circuit (RFIC) baseband, temperature sensor.

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Authors: P.K. Sharma, B. Bhargava, S. Akashe

Abstract:

Power dissipation due to leakage current in the digital circuits is a biggest factor which is considered specially while designing nanoscale circuits. This paper is exploring the ideas of reducing leakage current in static CMOS circuits by stacking the transistors in increasing numbers. Clearly it means that the stacking of OFF transistors in large numbers result a significant reduction in power dissipation. Increase in source voltage of NMOS transistor minimizes the leakage current. Thus stacking technique makes circuit with minimum power dissipation losses due to leakage current. Also some of digital circuits such as full adder, D flip flop and 6T SRAM have been simulated in this paper, with the application of reduction technique on ‘cadence virtuoso tool’ using specter at 45nm technology with supply voltage 0.7V.

Keywords: Stack, 6T SRAM cell, low power, threshold voltage

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Authors: Seongykyoon Jeong, Sungki Lee, Jaeyun Kim, Seunghun Oh, Kiho Kwak

Abstract:

The purpose of this article is to identify the practical strategies of R&D (research and development) entities for developing converging technology in organizational context. Based on the multi-assignation technological domains of patents derived from entire government-supported R&D projects for 13 years, we find that technology convergence is likely to occur when a university solely develops technology or when university develops technology as one of the collaborators. These results reflect the important role of universities in developing converging technology

Keywords: Interdisciplinary, Research and development strategy, Technology convergence

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Authors: Saad Mutashar Abbas, M. A. Hannan, S. A. Samad, A. Hussain

Abstract:

This paper presented a proposed design for transcutaneous inductive powering links. The design used to transfer power and data to the implanted devices such as implanted Microsystems to stimulate and monitoring the nerves and muscles. The system operated with low band frequency 13.56 MHZ according to industrial- scientific – medical (ISM) band to avoid the tissue heating. For external part, the modulation index is 13 % and the modulation rate 7.3% with data rate 1 Mbit/s assuming Tbit=1us. The system has been designed using 0.35-μm fabricated CMOS technology. The mathematical model is given and the design is simulated using OrCAD P Spice 16.2 software tool and for real-time simulation the electronic workbench MULISIM 11 has been used. The novel circular plane (pancake) coils was simulated using ANSOFT- HFss software.

Keywords: Implanted devices, ASK techniques, Class-E power amplifier, Inductive powering and low-frequency ISM band.

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Authors: P. P. S. Sifolo, M. J. Maimela M. P. Tladi

Abstract:

This article investigates technology used by Tshwane residents intended for tourism purposes. The aim is to contribute information for planning and management concerning technology within the tourism sector in the city of Tshwane, South Africa. This study identified the types of tourist related technologies used by the Tshwane residents, be it for business purposes or personal use. The study connected the exploitation of technology for tourism purposes through unpacking the tourism sector as it utilizes technology. Quantitative research methodology was used whereby self-completed questionnaires were chosen as research instruments. The research study carried out a search for knowledge on technology for tourism and the Tshwane residents; however the study revealed that technology has certainly imprinted tourism massively because of its effectiveness and efficiency. Technology has assisted tourism businesses stay abreast of competition with integrated communication technology (ICT) and because of that, SA is on the map as one of the economically performing countries in Africa. Moreover, technology and tourism make a meaningful impact on job creation and Gross Domestic Product (GDP).

Keywords: Information and Communication Technology, Technology for tourism, Tshwane residents.

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Authors: L.Tahmooresnejad, M.A.Shafia, R.Salami

Abstract:

Technology transfer is a common method for companies to acquire new technology and presents both challenges and substantial benefits. In some cases especially in developing countries, the mere possession of technology does not guarantee a competitive advantage if the appropriate infrastructure is not in place. In this paper, we identify the localization factors needed to provide a better understanding of the conditions necessary for localization in order to benefit from future technology developments. Our theoretical and empirical analyses allow us to identify several factors in the technology transfer process that affect localization and provide leverage in enhancing capabilities and absorptive capacity.The impact factors are categorized within different groups of government, firms, institutes and market, and are verified through the empirical survey of a technology transfer experience. Moreover, statistical analysis has allowed a deeper understanding of the importance of each factor and has enabled each group to prioritize their organizational policies to effectively localize their technology.

Keywords: Absorption Capacity, Adaptation, Technology Transfer, Technology Localization

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Authors: Daekook Kang, Wooseok Jang, Hyeonjeong Lee, Hyun Joung No

Abstract:

Technology changes have been acknowledged as a critical factor in determining competitiveness of organization. Under such environment, the right anticipation of technology change has been of huge importance in strategic planning. To monitor technology change, technology forecasting (TF) is frequently utilized. In academic perspective, TF has received great attention for a long time. However, few researches have been conducted to provide overview of the TF literature. Even though some studies deals with review of TF research, they generally focused on type and characteristics of various TF, so hardly provides information about patterns of TF research and which TF method is used in certain technology industry. Accordingly, this study profile developments in and patterns of scholarly research in TF over time. Also, this study investigates which technology industries have used certain TF method and identifies their relationships. This study will help in understanding TF research trend and their application area.

Keywords: Technology forecasting, technology industry, TF trend, technology trajectory.

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Authors: S. M. Abbas, M. A. Hannan, S. A. Samad, A. Hussain

Abstract:

This paper presented a modified efficient inductive powering link based on ASK modulator and proposed efficient class- E power amplifier. The design presents the external part which is located outside the body to transfer power and data to the implanted devices such as implanted Microsystems to stimulate and monitoring the nerves and muscles. The system operated with low band frequency 10MHZ according to industrial- scientific – medical (ISM) band to avoid the tissue heating. For external part, the modulation index is 11.1% and the modulation rate 7.2% with data rate 1 Mbit/s assuming Tbit = 1us. The system has been designed using 0.35-μm fabricated CMOS technology. The mathematical model is given and the design is simulated using OrCAD P Spice 16.2 software tool and for real-time simulation, the electronic workbench MULISIM 11 has been used.

Keywords: Implanted devices, ASK techniques, Class-E power amplifier, Inductive powering and low-frequency ISM band.

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Authors: Néjib Hassen, Thouraya Ettaghzouti, Kamel Besbes

Abstract:

In this paper, a modified CCCII is presented. We have used a current mirror with low supply voltage. This circuit is operated at low supply voltage of ±1V. Tspice simulations for TSMC 0.18μm CMOS Technology has shown that the current and voltage bandwidth are respectively 3.34GHz and 4.37GHz, and parasitic resistance at port X has a value of 169.320 for a control current of 120μA. In order to realize this circuit, we have implemented in this first step a universal current mode filter where the frequency can reach the 134.58MHz. In the second step, we have implemented two simulated inductors: one floating and the other grounded. These two inductors are operated in high frequency and variable depending on bias current I0. Finally, we have used the two last inductors respectively to implement two sinusoidal oscillators domains of frequencies respectively: [470MHz, 692MHz], and [358MHz, 572MHz] for bias currents I0 [80μA, 350μA].

Keywords: Current controlled current conveyor CCCII, floating inductor, grounded inductor, oscillator, universal filter.

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Authors: B. Kiyani, R. H. Amiri, S. H. Hosseini, A. Bourouni, A. Karimi

Abstract:

Nowadays, offshore's complicated facilities need their own communications requirements. Nevertheless, developing and real-world applications of new communications technology are faced with tremendous problems for new technology users, developers and implementers. Traditional systems engineering cannot be capable to develop a new technology effectively because it does not consider the dynamics of the process. This paper focuses on the design of a holistic model that represents the dynamics of new communication technology development within offshore industry. The model shows the behavior of technology development efforts. Furthermore, implementing this model, results in new and useful insights about the policy option analysis for developing a new communications technology in offshore industry.

Keywords: Technology development, Offshore industry, Systemdynamics, Voice Over IP.

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Authors: Shilpi Lavania

Abstract:

As the frequency of operation has attained a range of GHz and signal rise time continues to increase interconnect technology is suffering due to various high frequency effects as well as ground bounce problem. In some recent studies a high frequency effect i.e. skin effect has been modeled and its drawbacks have been discussed. This paper strives to make an impression on the advantage side of modeling skin effect for interconnect line. The proposed method has considered a CMOS with RC interconnect. Delay and noise considering ground bounce problem and with skin effect are discussed. The simulation results reveal an advantage of considering skin effect for minimization of ground bounce problem during the working of the model. Noise and delay variations with temperature are also presented.

Keywords: Interconnect, Skin effect, Ground Bounce, Delay, Noise.

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Authors: Jeeeun Kim, Sungjoo Lee

Abstract:

This research proposes a methodology for patent-citation-based technology input-output analysis by applying the patent information to input-output analysis developed for the dependencies among different industries. For this analysis, a technology relationship matrix and its components, as well as input and technology inducement coefficients, are constructed using patent information. Then, a technology inducement coefficient is calculated by normalizing the degree of citation from certain IPCs to the different IPCs (International patent classification) or to the same IPCs. Finally, we construct a Dependency Structure Matrix (DSM) based on the technology inducement coefficient to suggest a useful application for this methodology.

Keywords: Technology spillover effect, technology relationship, IO table, technology inducement coefficients, patent analysis, patent citation.

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Authors: Khalil Monfaredi, Hassan Faraji Baghtash, Majid Abbasi

Abstract:

In this paper a novel high output impedance, low input impedance, wide bandwidth, very simple current mirror with input and output voltage requirements less than that of a simple current mirror is presented. These features are achieved with very simple structure avoiding extra large node impedances to ensure high bandwidth operation. The circuit's principle of operation is discussed and compared to simple and low voltage cascode (LVC) current mirrors. Such outstanding features of this current mirror as high output impedance ~384K, low input impedance~6.4, wide bandwidth~178MHz, low input voltage ~ 362mV, low output voltage ~ 38mV and low current transfer error ~4% (all at 50μA) makes it an outstanding choice for high performance applications. Simulation results in BSIM 0.35μm CMOS technology with HSPICE are given in comparison with simple, and LVC current mirrors to verify and validate the performance of the proposed current mirror.

Keywords: Analog circuits, Current mirror, high frequency, Low power, Low voltage.

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Authors: E. V. Veraszto, J. T. F. Camargo, D. Silva, N. A. Miranda, F. O. Simon, S. F. Amaral, L. V. Freitas

Abstract:

The concept of technology as well as itself has evolved continuously over time, such that, nowadays, this concept is still marked by myths and realities. Even the concept of science is frequently misunderstood as technology. In this way, this paper presents different forms of interpretation of the concept of technology in the course of history, as well as the social and cultural aspects associated with it, through an analysis made by means of insights from sociological studies of science and technology and its multiple relations with society. Through the analysis of contents, the paper presents a classification of how technology is interpreted in the social sphere and search channel efforts to show how a broader understanding can contribute to better interpretations of how scientific and technological development influences the environment in which we operate. The text also presents a particular point of view for the interpretation of the concept from the analysis throughout the whole work.

Keywords: Technology, conceptions of technology, technological myths, definition of technology.

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Authors: José Carlos Rodríguez, Mario Gómez

Abstract:

The aim of this paper is to get insight on the nature of university-industry technology transfer (UITT) and technology transfer offices (TTOs) activity at universities in the case of emerging economies. In relation to the process of transferring knowledge/technology in the case of emerging economies, knowledge/technology transfer in these economies are more reactive than in developed economies due to differences in maturity of technologies. It is assumed in this paper that knowledge/technology transfer is a complex phenomenon, and thus the paper contributes to get insight on the nature of UITT and TTOs creation in the case of emerging economies by using a system dynamics model of knowledge/technology transfer in these countries. The paper recognizes the differences between industrialized countries and emerging economies on these phenomena.

Keywords: University-industry technology transfer, technology transfer offices, technology transfer models, emerging economies.

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Authors: Bilel Gassara, Mahmoud Abdellaoui, Nouri Masmoud

Abstract:

The 4G front-end transceiver needs a high performance which can be obtained mainly with an optimal architecture and a multi-band Local Oscillator. In this study, we proposed and presented a new architecture of multi-band frequency synthesizer based on an Inverse Sine Phase Detector Phase Locked Loop (ISPD PLL) without any filters and any controlled gain block and associated with adapted multi band LC tuned VCO using a several numeric controlled capacitive branches but not binary weighted. The proposed architecture, based on 0.35μm CMOS process technology, supporting Multi-band GSM/DCS/DECT/ UMTS/WiMax application and gives a good performances: a phase noise @1MHz -127dBc and a Factor Of Merit (FOM) @ 1MHz - 186dB and a wide band frequency range (from 0.83GHz to 3.5GHz), that make the proposed architecture amenable for monolithic integration and 4G multi-band application.

Keywords: GSM/DCS/DECT/UMTS/WiMax, ISPD PLL, keep and capture range, Multi-Band, Synthesizer, Wireless.

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Authors: Guo-Ming Sung, Naga Raju Naik R.

Abstract:

Paper presents a low power, high speed, sense-amplifier based flip-flop (SAFF). The flip-flop’s power con-sumption and delay are greatly reduced by employing a new conditionally precharge sense-amplifier stage and a single-ended latch stage. Glitch-free and contention-free latch operation is achieved by using a conditional cut-off strategy. The design uses fewer transistors, has a lower clock load, and has a simple structure, all of which contribute to a near-zero setup time. When compared to previous flip-flop structures proposed for similar input/output conditions, this design’s performance and overall PDP have improved. The post layout simulation of the circuit uses 2.91µW of power and has a delay of 65.82 ps. Overall, the power-delay product has seen some enhancements. Cadence Virtuoso Designing tool with CMOS 90nm technology are used for all designs.

Keywords: high-speed, low-power, flip-flop, sense-amplifier

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Authors: Gizem Intepe, Tufan Koc

Abstract:

S-Curves are commonly used in technology forecasting. They show the paths of product performance in relation to time or investment in R&D. It is a useful tool to describe the inflection points and the limit of improvement of a technology. Companies use this information to base their innovation strategies. However inadequate use and some limitations of this technique lead to problems in decision making. In this paper first technology forecasting and its importance for company level strategies will be discussed. Secondly the S-Curve and its place among other forecasting techniques will be introduced. Thirdly its use in technology forecasting will be discussed based on its advantages, disadvantages and limitations. Finally an application of S-curve on 3D TV technology using patent data will also be presented and the results will be discussed.

Keywords: Patent analysis, Technological forecasting. S curves, 3D TV

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Authors: N. Shen, Z. X. Chen, K.D. Buddharaju, H. M. Chua, X. Li, N. Singh, G.Q Lo, D.-L. Kwong

Abstract:

In this paper, we present a vertical wire NMOS device fabricated using CMOS compatible processes. The impact of temperature on various device parameters is investigated in view of usual increase in surrounding temperature with device density.

Keywords: Gate-all-around, temperature dependence, silicon nanowire

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Authors: G. Schuh, S. Aghassi

Abstract:

In order to bridge the gap between research and industry, promoting technology and knowledge transfer becomes increasingly important. Especially small- and medium-sized enterprises, having only little R&D resources themselves, depend on external technology development activities for remaining innovative. Academia research on the other hand needs potential industrial partners, who are capable and willing to commercialize their technologies as most public funding programs require some sort of technology transfer or dissemination activities. Modern web technologies offer more and more “social” functionalities and open up new ways of user interaction. In the past years several technology transfer platforms were developed, making use of modern web technologies in order to enable and support technology transfer. In this paper we report on the results of a state-of-the art analyses of existing technology transfer platforms, point out their advantages and deficits and give a perspective to the development of an improved technology transfer platform.

Keywords: Knowledge transfer, social software, technology management, technology transfer.

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Authors: G. Reinhart, S. Schindler

Abstract:

Due to dynamic evolution, the ability of a manufacturing technology to produce a special product is changing. Therefore, it is essential to monitor the established techniques and processes to detect whether a company-s production will fit future circumstances. Concerning the manufacturing technology planning process, companies must decide when to change to a new technology for maintaining and increasing competitive advantages. In this context, the maturity assessment of the focused technologies is crucial. This article presents an approach for defining the maturity of a manufacturing technology from a strategic point of view. The concept is based on the approach of technology readiness level (TRL) according to NASA (National Aeronautics and Space Administration), but also includes dynamic changes. Therefore, the model takes into account the concept of the technology life cycle. Furthermore, it enables a company to estimate the ideal date for implementation of a new manufacturing technology.

Keywords: Maturity Assessment, Manufacturing Technology Planning, Technology Life Cycle, Technology Readiness Level.

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Authors: M. Kaggwa

Abstract:

Technology or lack of it will play an important role in Africa-s effort to achieve inclusive development. Although a key determinant of competitiveness, new technology can exacerbate exclusion of the majority from the mainstream economic activities. To minimise potential technology exclusion while leveraging its critical role in African-s development, requires insight into technology diffusion process. Using system dynamics approach, a technology diffusion model is presented. The frequency of interaction of people exposed to and those not exposed to technology, and the technology adoption rate - the fraction of people who embrace new technologies once they are exposed, are identified as the broad factors critical to technology diffusion to wider society enabling more people to be part of the economic growth process. Based on simulation results, it is recommends that these two broad factors should form part of national policy aimed at achieving inclusive and sustainable development in Africa.

Keywords: Inclusive Development, System Dynamics, Technology, Technology diffusion.

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Authors: M. Yousefi, N. Nasirzadeh

Abstract:

In this paper, dynamic comparator structure employing two methods for power consumption reduction with applications in low-power high-speed analog-to-digital converters have been presented. The proposed comparator has low consumption thanks to power reduction methods. They have the ability for offset adjustment. The comparator consumes 14.3 μW at 100 MHz which is equal to 11.8 fJ. The comparator has been designed and simulated in 180 nm CMOS. Layouts occupy 210 μm².

Keywords: Comparator, low, power, efficiency.

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Authors: Chang Soo Kang, In Ho Im, Sergey Churayev, Timour Paltashev

Abstract:

This paper describes the design of new method of propagation delay measurement in micro and nanostructures during characterization of ASIC standard library cell. Providing more accuracy timing information about library cell to the design team we can improve a quality of timing analysis inside of ASIC design flow process. Also, this information could be very useful for semiconductor foundry team to make correction in technology process. By comparison of the propagation delay in the CMOS element and result of analog SPICE simulation. It was implemented as digital IP core for semiconductor manufacturing process. Specialized method helps to observe the propagation time delay in one element of the standard-cell library with up-to picoseconds accuracy and less. Thus, the special useful solutions for VLSI schematic to parameters extraction, basic cell layout verification, design simulation and verification are announced.

Keywords: phase error accumulation methodology, gatepropagation delay, Processor Testing, MEMS Testing

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Authors: Somaye Abdollahi Pour, Mohsen Saneei

Abstract:

This paper describes a novel monitoring scheme to minimize total active power in digital circuits depend on the demand frequency, by adjusting automatically both supply voltage and threshold voltages based on circuit operating conditions such as temperature, process variations, and desirable frequency. The delay monitoring results, will be control and apply so as to be maintained at the minimum value at which the chip is able to operate for a given clock frequency. Design details of power monitor are examined using simulation framework in 32nm BTPM model CMOS process. Experimental results show the overhead of proposed circuit in terms of its power consumption is about 40 μW for 32nm technology; moreover the results show that our proposed circuit design is not far sensitive to the temperature variations and also process variations. Besides, uses the simple blocks which offer good sensitivity, high speed, the continuously feedback loop. This design provides up to 40% reduction in power consumption in active mode.

Keywords: active mode, delay monitor, body biasing, VDD scaling, low power.

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Authors: Geoffrey Sinha

Abstract:

This paper is primarily addressed to teachers who stand on the threshold of bringing technology and new media into their classrooms. Technology and new media, such as smart phones and tablets have changed the face of communication in general and of language teaching more specifically. New media has widespread appeal among young people in particular, so it is in the teacher’s best interests to bring new media into their lessons. It is the author’s firm belief that technology will never replace the teacher, but it is without question that the twenty-first century teacher must employ technology and new media in some form, or run the risk of failure. The level that one chooses to incorporate new media within their class is entirely in their hands.

Keywords: New media, social media, technology, education.

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Authors: Padmanabhan Balasubramanian, Ryuta Arisaka

Abstract:

Factoring Boolean functions is one of the basic operations in algorithmic logic synthesis. A novel algebraic factorization heuristic for single-output combinatorial logic functions is presented in this paper and is developed based on the set theory paradigm. The impact of factoring is analyzed mainly from a low power design perspective for standard cell based digital designs in this paper. The physical implementation of a number of MCNC/IWLS combinational benchmark functions and sub-functions are compared before and after factoring, based on a simple technology mapping procedure utilizing only standard gate primitives (readily available as standard cells in a technology library) and not cells corresponding to optimized complex logic. The power results were obtained at the gate-level by means of an industry-standard power analysis tool from Synopsys, targeting a 130nm (0.13μm) UMC CMOS library, for the typical case. The wire-loads were inserted automatically and the simulations were performed with maximum input activity. The gate-level simulations demonstrate the advantage of the proposed factoring technique in comparison with other existing methods from a low power perspective, for arbitrary examples. Though the benchmarks experimentation reports mixed results, the mean savings in total power and dynamic power for the factored solution over a non-factored solution were 6.11% and 5.85% respectively. In terms of leakage power, the average savings for the factored forms was significant to the tune of 23.48%. The factored solution is expected to better its non-factored counterpart in terms of the power-delay product as it is well-known that factoring, in general, yields a delay-efficient multi-level solution.

Keywords: Factorization, Set theory, Logic function, Standardcell based design, Low power.

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