Search results for: Time delay

Authors: E. V. Larkin, T. A. Akimenko, A. V. Bogomolov, A. N. Privalov

Abstract:

The digital control system of mobile robots (MR) control is considered. It is shown that sequential interpretation of control algorithm operators, unfolding in physical time, suggests the occurrence of time delays between inputting data from sensors and outputting data to actuators. Another destabilizing control factor is presence of backlash in the joints of an actuator with an executive unit. Complex model of control system, which takes into account the dynamics of the MR, the dynamics of the digital controller and backlash in actuators, is worked out. The digital controller model is divided into two parts: the first part describes the control law embedded in the controller in the form of a control program that realizes a polling procedure when organizing transactions to sensors and actuators. The second part of the model describes the time delays that occur in the Von Neumann-type controller when processing data. To estimate time intervals, the algorithm is represented in the form of an ergodic semi-Markov process. For an ergodic semi-Markov process of common form, a method is proposed for estimation a wandering time from one arbitrary state to another arbitrary state. Example shows how the backlash and time delays affect the quality characteristics of the MR control system functioning.

Keywords: Mobile robot, backlash, control algorithm, Von Neumann controller, semi-Markov process, time delay.

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Authors: Yavar Safaei Mehrabani, Mehdi Hosseinzadeh

Abstract:

As embedded and portable systems were emerged power consumption of circuits had been major challenge. On the other hand latency as determines frequency of circuits is also vital task. Therefore, trade off between both of them will be desirable. Modulo 2n+1 adders are important part of the residue number system (RNS) based arithmetic units with the interesting moduli set (2n-1,2n, 2n+1). In this manuscript we have introduced novel binary representation to the design of modulo 2n+1 adder. VLSI realization of proposed architecture under 180 nm full static CMOS technology reveals its superiority in terms of area, power consumption and power-delay product (PDP) against several peer existing structures.

Keywords: Computer arithmetic, modulo 2n+1 adders, Residue Number System (RNS), VLSI.

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Authors: Dong-Jae Kang, Nam-Woo Kim, Duk-Joo Son, Sung-In Jung

Abstract:

According to dramatic growth of internet services, an easy and prompt service deployment has been important for internet service providers to successfully maintain time-to-market. Before global service deployment, they have to pay the big cost for service evaluation to make a decision of the proper system location, system scale, service delay and so on. But, intra-Lab evaluation tends to have big gaps in the measured data compared with the realistic situation, because it is very difficult to accurately expect the local service environment, network congestion, service delay, network bandwidth and other factors. Therefore, to resolve or ease the upper problems, we propose multiple cloud based GPES Broker system and use case that helps internet service providers to alleviate the above problems in beta release phase and to make a prompt decision for their service launching. By supporting more realistic and reliable evaluation information, the proposed GPES Broker system saves the service release cost and enables internet service provider to make a prompt decision about their service launching to various remote regions.

Keywords: GPES Broker system, Cloud Service Broker, Multiple Cloud, Global performance evaluation service (GPES), Service provisioning

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Authors: Daiming Wang

Abstract:

In this paper, by using Mawhin-s continuation theorem of coincidence degree and a method based on delay differential inequality, some sufficient conditions are obtained for the existence and global exponential stability of periodic solutions of cellular neural networks with distributed delays and impulses on time scales. The results of this paper generalized previously known results.

Keywords: Periodic solutions, global exponential stability, coincidence degree, M-matrix.

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Authors: Ching-Tsan Chiang, Sheng-Jie Yang, Jing-Kai Huang

Abstract:

The purpose of this research is to develop and apply the RSCMAC to enhance the dynamic accuracy of Global Positioning System (GPS). GPS devices provide services of accurate positioning, speed detection and highly precise time standard for over 98% area on the earth. The overall operation of Global Positioning System includes 24 GPS satellites in space; signal transmission that includes 2 frequency carrier waves (Link 1 and Link 2) and 2 sets random telegraphic codes (C/A code and P code), on-earth monitoring stations or client GPS receivers. Only 4 satellites utilization, the client position and its elevation can be detected rapidly. The more receivable satellites, the more accurate position can be decoded. Currently, the standard positioning accuracy of the simplified GPS receiver is greatly increased, but due to affected by the error of satellite clock, the troposphere delay and the ionosphere delay, current measurement accuracy is in the level of 5~15m. In increasing the dynamic GPS positioning accuracy, most researchers mainly use inertial navigation system (INS) and installation of other sensors or maps for the assistance. This research utilizes the RSCMAC advantages of fast learning, learning convergence assurance, solving capability of time-related dynamic system problems with the static positioning calibration structure to improve and increase the GPS dynamic accuracy. The increasing of GPS dynamic positioning accuracy can be achieved by using RSCMAC system with GPS receivers collecting dynamic error data for the error prediction and follows by using the predicted error to correct the GPS dynamic positioning data. The ultimate purpose of this research is to improve the dynamic positioning error of cheap GPS receivers and the economic benefits will be enhanced while the accuracy is increased.

Keywords: Dynamic Error, GPS, Prediction, RSCMAC.

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Authors: H. El-Madbouly

Abstract:

For future Broad band ISDN, Asynchronous Transfer Mode (ATM) is designed not only to support a wide range of traffic classes with diverse flow characteristics, but also to guarantee the different quality of service QOS requirements. The QOS may be measured in terms of cell loss probability and maximum cell delay. In this paper, ATM networks in which the virtual path (VP) concept is implemented are considered. By applying the Markov Deterministic process method, an efficient algorithm to compute the minimum capacity required to satisfy the QOS requirements when multiple classes of on-off are multiplexed on to a single VP. Using the result, we then proposed a simple algorithm to determine different combinations of VP to achieve the optimum of the total capacity required for satisfying the individual QOS requirements (loss- delay).

Keywords: Bandwidth allocation, Quality of services, ATMNetwork, virtual path.

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Authors: Yasunori Sugita, Toshinori Yoshikawa, Naoyuki Aikawa

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Variable digital filters are useful for various signal processing and communication applications where the frequency characteristics, such as fractional delays and cutoff frequencies, can be varied. In this paper, we propose a design method of variable FIR digital filters with an approximate linear phase characteristic in the passband. The proposed variable FIR filters have some large attenuation in stopband and their large attenuation can be varied by spectrum parameters. In the proposed design method, a quasi-equiripple characteristic can be obtained by using an iterative weighted least square method. The usefulness of the proposed design method is verified through some examples.

Keywords: Weighted Least Squares Approximation, Variable FIR Filters, Low-Delay, Quasi-Equiripple

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Authors: Sami Mutair, Yasuyuki Ikegami

Abstract:

This paper reports on the results of experimental investigations of flash evaporation from superheated jet issues vertically upward from a round straight nozzle of 81.3 mm diameter. For the investigated range of jet superheat degree and velocity, it was shown that flash evaporation enhances with initial temperature increase. Due to the increase of jet inertia and subsequently the delay of jet shattering, increase of jet velocity was found to result in increase of evaporation "delay period". An empirical equation predicts the jet evaporation completion height was developed, this equation is thought to be useful in designing the flash evaporation chamber. In attempts for enhancement of flash evaporation, use of steel wire mesh located at short distance downstream was found effective with no consequent pressure drop.

Keywords: Enhancement; Flash Evaporation; OTEC; superheated jet

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Authors: Changjin Xu

Abstract:

In this paper, applying frequency domain approach, a delayed predator-prey fishery model with prey reserve is investigated. By choosing the delay τ as a bifurcation parameter, It is found that Hopf bifurcation occurs as the bifurcation parameter τ passes a sequence of critical values. That is, a family of periodic solutions bifurcate from the equilibrium when the bifurcation parameter exceeds a critical value. The length of delay which preserves the stability of the positive equilibrium is calculated. Some numerical simulations are included to justify the theoretical analysis results. Finally, main conclusions are given.

Keywords: Predator-prey model, stability, Hopf bifurcation, frequency domain, Nyquist criterion.

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Authors: R. Abdul Wahab, R. Mohd Fuad Tengku Aziz, N. Othman, S. Saleh, N. Razali, M. Al Baqir Zinal Abidin, M. Hanif Md Nasir

Abstract:

This paper will discuss how we optimize our physical verification flow in our IC Design Department having various rule decks from multiple foundries. Our ultimate goal is to achieve faster time to tape-out and avoid schedule delay. Currently the physical verification runtimes and memory usage have drastically increased with the increasing number of design rules, design complexity, and the size of the chips to be verified. To manage design violations, we use a number of solutions to reduce the amount of violations needed to be checked by physical verification engineers. The most important functions in physical verifications are DRC (design rule check), LVS (layout vs. schematic), and XRC (extraction). Since we have a multiple number of foundries for our design tape-outs, we need a flow that improve the overall turnaround time and ease of use of the physical verification process. The demand for fast turnaround time is even more critical since the physical design is the last stage before sending the layout to the foundries.

Keywords: Physical verification, DRC, LVS, XRC, flow, foundry, runset.

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Authors: Marwan Ihsan Shukur, Lee Sheng Chyan, Vooi Voon Yap

Abstract:

Wireless sensor networks is an emerging technology that serves as environment monitors in many applications. Yet these miniatures suffer from constrained resources in terms of computation capabilities and energy resources. Limited energy resource in these nodes demands an efficient consumption of that resource either by developing the modules itself or by providing an efficient communication protocols. This paper presents a comprehensive summarization and a comparative study of the available MAC protocols proposed for Wireless Sensor Networks showing their capabilities and efficiency in terms of energy consumption and delay guarantee.

Keywords: MAC (Medium Access Control), SEA (Simple EnergyAware), WSNs (Wireless Sensor Nodes or Networks) RTS (RequestTo Send), CTS (Clear To Send), SYNCH (Synchronize), NS2(Network Simulator 2).

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Authors: Changchun Shen, Shouming Zhong

Abstract:

This paper investigates the problem of absolute stability and robust stability of a class of Lur-e systems with neutral type and time-varying delays. By using Lyapunov direct method and linear matrix inequality technique, new delay-dependent stability criteria are obtained and formulated in terms of linear matrix inequalities (LMIs) which are easy to check the stability of the considered systems. To obtain less conservative stability conditions, an operator is defined to construct the Lyapunov functional. Also, the free weighting matrices approach combining a matrix inequality technique is used to reduce the entailed conservativeness. Numerical examples are given to indicate significant improvements over some existing results.

Keywords: Lur'e system, linear matrix inequalities, Lyapunov, stability.

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Authors: Antoni Wibowo, Harry Pujianto, Dewi Retno Sari Saputro

Abstract:

The stock market can provide huge profits in a relatively short time in financial sector; however, it also has a high risk for investors and traders if they are not careful to look the factors that affect the stock market. Therefore, they should give attention to the dynamic fluctuations and movements of the stock market to optimize profits from their investment. In this paper, we present a nonlinear autoregressive exogenous model (NARX) to predict the movements of stock market; especially, the movements of the closing price index. As case study, we consider to predict the movement of the closing price in Indonesia composite index (IHSG) and choose the best structures of NARX for IHSG’s prediction.

Keywords: NARX, prediction, stock market, time series.

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Authors: Zhenguo Vincent Chia, Sheung Yan Simon Ng, Minkyu Je

Abstract:

This paper presents CMOS Current Mode Logic (CML) circuits for a high speed Digital to Analog Converter (DAC) using standard CMOS 65nm process. The CML circuits have the propagation delay advantage over its conventional CMOS counterparts due to smaller output voltage swing and tunable bias current. The CML circuits proposed in this paper can achieve a maximum propagation delay of only 9.3ps, which can satisfy the stringent requirement for the 5 GHz high speed DAC application. Another advantage for CML circuits is its dynamic symmetry characteristic resulting in a reduction of an additional inverter. Simulation results show that the proposed CML circuits can operate from 1.08V to 1.3V with temperature ranging from -40 to +120°C.

Keywords: Conventional, Current Mode Logic, DAC, Decoder

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Authors: Zixin Liu, Huawei Yang, Fangwei Chen

Abstract:

This paper studies the mean square exponential synchronization problem of a class of stochastic neutral type chaotic neural networks with mixed delay. On the Basis of Lyapunov stability theory, some sufficient conditions ensuring the mean square exponential synchronization of two identical chaotic neural networks are obtained by using stochastic analysis and inequality technique. These conditions are expressed in the form of linear matrix inequalities (LMIs), whose feasibility can be easily checked by using Matlab LMI Toolbox. The feedback controller used in this paper is more general than those used in previous literatures. One simulation example is presented to demonstrate the effectiveness of the derived results.

Keywords: Exponential synchronization, stochastic analysis, chaotic neural networks, neutral type system.

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Authors: Mingyang Sun, Guozheng Yan, Dasheng Liu, Lei Yang

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Driven by the demand of intelligent monitoring in rehabilitation centers or hospitals, a high accuracy real-time location system based on UWB (ultra-wideband) technology was proposed. The system measures precise location of a specific person, traces his movement and visualizes his trajectory on the screen for doctors or administrators. Therefore, doctors could view the position of the patient at any time and find them immediately and exactly when something emergent happens. In our design process, different algorithms were discussed, and their errors were analyzed. In addition, we discussed about a , simple but effective way of correcting the antenna delay error, which turned out to be effective. By choosing the best algorithm and correcting errors with corresponding methods, the system attained a good accuracy. Experiments indicated that the ranging error of the system is lower than 7 cm, the locating error is lower than 20 cm, and the refresh rate exceeds 5 times per second. In future works, by embedding the system in wearable IoT (Internet of Things) devices, it could provide not only physical parameters, but also the activity status of the patient, which would help doctors a lot in performing healthcare.

Keywords: Intelligent monitoring, IoT devices, real-time location, smart healthcare, ultra-wideband technology.

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Authors: S. Gherbi, F. Bouchareb

Abstract:

This paper deals with the novel intelligent bio-inspired control strategies, it presents a novel approach based on an optimal fuzzy immune PID parameters tuning, it is a combination of a PID controller, inspired by the human immune mechanism with fuzzy logic. Such controller offers more possibilities to deal with the delayed systems control difficulties due to the delay term. Indeed, we use an optimization approach to tune the four parameters of the controller in addition to the fuzzy function; the obtained controller is implemented in a modified Smith predictor structure, which is well known that it is the most efficient to the control of delayed systems. The application of the presented approach to control a three tank delay system shows good performances and proves the efficiency of the method.

Keywords: Delayed systems, Fuzzy Immune PID, Optimization, Smith predictor.

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Authors: Zheni S. Stefanova, Kandethody M. Ramachandran

Abstract:

With the increasing dependency on our computer devices, we face the necessity of adequate, efficient and effective mechanisms, for protecting our network. There are two main problems that Intrusion Detection Systems (IDS) attempt to solve. 1) To detect the attack, by analyzing the incoming traffic and inspect the network (intrusion detection). 2) To produce a prompt response when the attack occurs (intrusion prevention). It is critical creating an Intrusion detection model that will detect a breach in the system on time and also challenging making it provide an automatic and with an acceptable delay response at every single stage of the monitoring process. We cannot afford to adopt security measures with a high exploiting computational power, and we are not able to accept a mechanism that will react with a delay. In this paper, we will propose an intrusion response mechanism that is based on artificial intelligence, and more precisely, reinforcement learning techniques (RLT). The RLT will help us to create a decision agent, who will control the process of interacting with the undetermined environment. The goal is to find an optimal policy, which will represent the intrusion response, therefore, to solve the Reinforcement learning problem, using a Q-learning approach. Our agent will produce an optimal immediate response, in the process of evaluating the network traffic.This Q-learning approach will establish the balance between exploration and exploitation and provide a unique, self-learning and strategic artificial intelligence response mechanism for IDS.

Keywords: Intrusion prevention, network security, optimal policy, Q-learning.

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Authors: Padmanabhan Balasubramanian, Bashetty Raghavendra

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In this paper, an analysis is presented, which demonstrates the effect pre-logic factoring could have on an automated combinational logic synthesis process succeeding it. The impact of pre-logic factoring for some arbitrary combinatorial circuits synthesized within a FPGA based logic design environment has been analyzed previously. This paper explores a similar effect, but with the non-regenerative logic synthesized using elements of a commercial standard cell library. On an overall basis, the results obtained pertaining to the analysis on a variety of MCNC/IWLS combinational logic benchmark circuits indicate that pre-logic factoring has the potential to facilitate simultaneous power, delay and area optimized synthesis solutions in many cases.

Keywords: Algebraic factoring, Combinational logic synthesis, Standard cells, Low power, Delay optimization, Area reduction.

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Authors: Kyoungjin Kim

Abstract:

Nanoscale thermites such as the composite mixture of nano-sized aluminum and molybdenum trioxide powders possess several technical advantages such as much higher reaction rate and shorter ignition delay, when compared to the conventional energetic formulations made of micron-sized metal and oxidizer particles. In this study, the self-propagation of combustion wave in compacted pellets of nanoscale thermite composites is modeled and computationally investigated by utilizing the activation energy reduction of aluminum particles due to nanoscale particle sizes. The present computational model predicts the speed of combustion wave propagation which is good agreement with the corresponding experiments of thermite reaction. Also, several characteristics of thermite reaction in nanoscale composites are discussed including the ignition delay and combustion wave structures.

Keywords: Nanoparticles, Thermite reaction, Combustion wave, Numerical modeling.

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Authors: In Su Na, Gunwon Lee, Seiyong Kim

Abstract:

This study analyzed the effect of area variables and economic variables on the length of each period of the project in order to analyze the effect of agreement rate on project implementation in housing renewal projects. In conclusion, as can be seen from these results, a low agreement rate may not translate into project promotion, and a higher agreement rate may not translate into project delay. The expectation of the policy is that the lower the agreement rate, the more projects would be promoted, but that is not the actual effect. From a policy consistency viewpoint, changing the agreement rate frequently, depending on the decision of the public, is not reasonable. The policy of using agreement rate as a necessary condition for project implementation should be reconsidered.

Keywords: Area and Economic Variables, Elapsed time, Housing Renewal Project.

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Authors: Reza Faghih Mirzaee, Mohammad Hossein Moaiyeri, Keivan Navi

Abstract:

In this paper we present two novel 1-bit full adder cells in dynamic logic style. NP-CMOS (Zipper) and Multi-Output structures are used to design the adder blocks. Characteristic of dynamic logic leads to higher speeds than the other standard static full adder cells. Using HSpice and 0.18┬Ám CMOS technology exhibits a significant decrease in the cell delay which can result in a considerable reduction in the power-delay product (PDP). The PDP of Multi-Output design at 1.8v power supply is around 0.15 femto joule that is 5% lower than conventional dynamic full adder cell and at least 21% lower than other static full adders.

Keywords: Bridge Style, Dynamic Logic, Full Adder, HighSpeed, Multi Output, NP-CMOS, Zipper.

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Authors: Sourabh Jain, Sukhvir Singh Jain, Gaurav V. Jain

Abstract:

Intelligent Transportation System is an integrated application of communication, control and monitoring and display process technologies for developing a user–friendly transportation system for urban areas in developing countries. In fact, the development of a country and the progress of its transportation system are complementary to each other. Urban traffic has been growing vigorously due to population growth as well as escalation of vehicle ownership causing congestion, delays, pollution, accidents, high-energy consumption and low productivity of resources. The development and management of urban transport in developing countries like India however, is at tryout stage with very few accumulations. Under the umbrella of ITS, urban corridor management strategy have proven to be one of the most successful system in accomplishing these objectives. The present study interprets and figures out the performance of the 27.4 km long Urban Bus route having six intersections, five flyovers and 29 bus stops that covers significant area of the city by causality analysis. Performance interpretations incorporate Passenger Boarding and Alighting, Dwell time, Distance between Bus Stops and Total trip time taken by bus on selected urban route.

Keywords: Congestion, Dwell time, delay, passengers boarding alighting, travel time.

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Authors: Shubhajit Roy Chowdhury, Aritra Banerjee, Aniruddha Roy, Hiranmay Saha

Abstract:

The paper proposes the novel design of a 3T XOR gate combining complementary CMOS with pass transistor logic. The design has been compared with earlier proposed 4T and 6T XOR gates and a significant improvement in silicon area and power-delay product has been obtained. An eight transistor full adder has been designed using the proposed three-transistor XOR gate and its performance has been investigated using 0.15um and 0.35um technologies. Compared to the earlier designed 10 transistor full adder, the proposed adder shows a significant improvement in silicon area and power delay product. The whole simulation has been carried out using HSPICE.

Keywords: XOR gate, full adder, improvement in speed, area minimization, transistor count minimization.

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Authors: H. Y. Jung, Ju H. Park, S. M. Lee

Abstract:

Sampled-data controller is presented for solid oxide fuel cell systems which is expressed by a sector bounded nonlinear model. The proposed control law is obtained by solving a convex problem satisfying several linear matrix inequalities. Simulation results are given to show the effectiveness of the proposed design method.

Keywords: Sampled-data control, Sector bound, Solid oxide fuel cell, Time-delay.

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Authors: Jun Wang, Tingcun Wei

Abstract:

The digital pulse width modulator (DPWM) is the crucial building block for digitally-controlled DC-DC switching converter, which converts the digital duty ratio signal into its analog counterpart to control the power MOSFET transistors on or off. With the increase of switching frequency of digitally-controlled DC-DC converter, the DPWM with higher time resolution is required. In this paper, a 15-bits DPWM with three-level hybrid structure is presented; the first level is composed of a7-bits counter and a comparator, the second one is a 5-bits delay line, and the third one is a 3-bits digital dither. The presented DPWM is designed and implemented using the PLL megafunction of FPGA (Field Programmable Gate Arrays), and the required frequency of clock signal is 128 times of switching frequency. The simulation results show that, for the switching frequency of 2 MHz, a DPWM which has the time resolution of 15 ps is achieved using a maximum clock frequency of 256MHz. The designed DPWM in this paper is especially useful for high-frequency digitally-controlled DC-DC switching converters.

Keywords: DPWM, PLL megafunction, FPGA, time resolution, digitally-controlled DC-DC switching converter.

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Authors: Bhavana Prakash Shrivastava, Kavita Khare

Abstract:

This paper presents a synthesis and simulation of proposed enhanced buffer. The design provides advantages of both buffer and bufferless network for that two cross bar switches are used. The concept of virtual channel (VC) is eliminated from the previous design by using an efficient flow-control scheme that uses the storage already present in pipelined channels in place of explicit input VCBs. This can be addressed by providing enhanced buffers on the bufferless link and creating two virtual networks. With this approach, VCBs act as distributed FIFO buffers. Without VCBs or VCs, deadlock prevention is achieved by duplicating physical channels. An enhanced buffer provides a function of hand shaking by providing a ready valid handshake signal and two bit storage. Through this design the power is reduced to 15.65% and delay is reduced to 97.88% with respect to virtual channel router.

Keywords: Enhanced buffer, Gate delay, NOC, VCs, VCB.

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Authors: Arash Moradkhani Roshandeh, Othman Che Puan

Abstract:

Access Management is the proactive management of vehicular access points to land parcels adjacent to all manner of roadways. Good access management promotes safe and efficient use of the transportation network. This study attempts to utilize archived data from the University Technology of Malaysia on-campus area to assess the accuracy with which access management display some benefits. Results show that usage of access management reduces delay and fewer crashes. Clustered development can improve walking, cycling and transit travel, reduce parking requirements and improve emergency responses. Effective Access Management planning can also reduce total roadway facility costs by reducing the number of driveways and intersections. At the end after presenting recommendations some of the travel impact, and benefits that can be derived if these suggestions are implemented have been summarized with the related comments.

Keywords: Access Management, Delay, Density, Traffic Flow

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Authors: Yi Zhang, Quan Zhou, Jun Li, Yanlang Hu

Abstract:

Scheduling algorithm is a key technology in satellite switching system with input-buffer. In this paper, a new scheduling algorithm and its realization are proposed. Based on Crossbar switching fabric, the algorithm adopts serial scheduling strategy and adjusts the output port arbitrating strategy for the better equity of every port. Consequently, it increases the matching probability. The algorithm can greatly reduce the scheduling delay and cell loss rate. The analysis and simulation results by OPNET show that the proposed algorithm has the better performance than others in average delay and cell loss rate, and has the equivalent complexity. On the basis of these results, the hardware realization and simulation based on FPGA are completed, which validate the feasibility of the new scheduling algorithm.

Keywords: Scheduling algorithm, input-buffer, serial scheduling, hardware design.

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Authors: Ankit Mitra

Abstract:

An adder is one of the most integral component of a digital system like a digital signal processor or a microprocessor. Being an extremely computationally intensive part of a system, the optimization for speed and power consumption of the adder is of prime importance. In this paper we have designed a 1 bit full adder cell based on dynamic TSPC logic to achieve high speed operation. A high threshold voltage sleep transistor is used to reduce the static power dissipation in standby mode. The circuit is designed and simulated in TSPICE using TSMC 180nm CMOS process. Average power consumption, delay and power-delay product is measured which showed considerable improvement in performance over the existing full adder designs.

Keywords: CMOS, TSPC, MTCMOS, ALU, Clock gating, power gating, pipelining.

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