TY - JFULL AU - Bhavana Prakash Shrivastava and Kavita Khare PY - 2013/3/ TI - Synthesis and Simulation of Enhanced Buffer Router vs. Virtual Channel Router in NOC ON Cadence T2 - International Journal of Electrical and Computer Engineering SP - 284 EP - 293 VL - 7 SN - 1307-6892 UR - https://publications.waset.org/pdf/9996915 PU - World Academy of Science, Engineering and Technology NX - Open Science Index 74, 2013 N2 - This paper presents a synthesis and simulation of proposed enhanced buffer. The design provides advantages of both buffer and bufferless network for that two cross bar switches are used. The concept of virtual channel (VC) is eliminated from the previous design by using an efficient flow-control scheme that uses the storage already present in pipelined channels in place of explicit input VCBs. This can be addressed by providing enhanced buffers on the bufferless link and creating two virtual networks. With this approach, VCBs act as distributed FIFO buffers. Without VCBs or VCs, deadlock prevention is achieved by duplicating physical channels. An enhanced buffer provides a function of hand shaking by providing a ready valid handshake signal and two bit storage. Through this design the power is reduced to 15.65% and delay is reduced to 97.88% with respect to virtual channel router. ER -