Search results for: Time-varying delay
Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 582

Search results for: Time-varying delay

402 Bandwidth and Delay Aware Routing Protocol with Scheduling Algorithm for Multi Hop Mobile Ad Hoc Networks

Authors: Y. Harold Robinson, E. Golden Julie, S. Balaji

Abstract:

The scheduling based routing scheme is presented in this paper to avoid link failure. The main objective of this system is to introduce a cross-layer protocol framework that integrates routing with priority-based traffic management and distributed transmission scheduling. The reservation scheme is based on ID. The presented scheme guarantees that bandwidth reserved time slot is used by another packet in which end-to-end reservation is achieved. The Bandwidth and Delay Aware Routing Protocol with Scheduling Algorithm is presented to allocate channels efficiently. The experimental results show that the presented schemes performed well in various parameters compared to existing methods.

Keywords: Integrated routing, scheduling, MAC layer, IEEE 802.11.

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401 Bandwidth allocation in ATM Network for different QOS Requirements

Authors: H. El-Madbouly

Abstract:

For future Broad band ISDN, Asynchronous Transfer Mode (ATM) is designed not only to support a wide range of traffic classes with diverse flow characteristics, but also to guarantee the different quality of service QOS requirements. The QOS may be measured in terms of cell loss probability and maximum cell delay. In this paper, ATM networks in which the virtual path (VP) concept is implemented are considered. By applying the Markov Deterministic process method, an efficient algorithm to compute the minimum capacity required to satisfy the QOS requirements when multiple classes of on-off are multiplexed on to a single VP. Using the result, we then proposed a simple algorithm to determine different combinations of VP to achieve the optimum of the total capacity required for satisfying the individual QOS requirements (loss- delay).

Keywords: Bandwidth allocation, Quality of services, ATMNetwork, virtual path.

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400 A Weighted Least Square Algorithm for Low-Delay FIR Filters with Piecewise Variable Stopbands

Authors: Yasunori Sugita, Toshinori Yoshikawa, Naoyuki Aikawa

Abstract:

Variable digital filters are useful for various signal processing and communication applications where the frequency characteristics, such as fractional delays and cutoff frequencies, can be varied. In this paper, we propose a design method of variable FIR digital filters with an approximate linear phase characteristic in the passband. The proposed variable FIR filters have some large attenuation in stopband and their large attenuation can be varied by spectrum parameters. In the proposed design method, a quasi-equiripple characteristic can be obtained by using an iterative weighted least square method. The usefulness of the proposed design method is verified through some examples.

Keywords: Weighted Least Squares Approximation, Variable FIR Filters, Low-Delay, Quasi-Equiripple

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399 New Approaches on Exponential Stability Analysis for Neural Networks with Time-Varying Delays

Authors: Qingqing Wang, Baocheng Chen, Shouming Zhong

Abstract:

In this paper, utilizing the Lyapunov functional method and combining linear matrix inequality (LMI) techniques and integral inequality approach (IIA) to study the exponential stability problem for neural networks with discrete and distributed time-varying delays.By constructing new Lyapunov-Krasovskii functional and dividing the discrete delay interval into multiple segments,some new delay-dependent exponential stability criteria are established in terms of LMIs and can be easily checked.In order to show the stability condition in this paper gives much less conservative results than those in the literature,numerical examples are considered.

Keywords: Neural networks, Exponential stability, LMI approach, Time-varying delays.

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398 Study and Enhancement of Flash Evaporation Desalination Utilizing the Ocean Thermocline and Discharged heat

Authors: Sami Mutair, Yasuyuki Ikegami

Abstract:

This paper reports on the results of experimental investigations of flash evaporation from superheated jet issues vertically upward from a round straight nozzle of 81.3 mm diameter. For the investigated range of jet superheat degree and velocity, it was shown that flash evaporation enhances with initial temperature increase. Due to the increase of jet inertia and subsequently the delay of jet shattering, increase of jet velocity was found to result in increase of evaporation "delay period". An empirical equation predicts the jet evaporation completion height was developed, this equation is thought to be useful in designing the flash evaporation chamber. In attempts for enhancement of flash evaporation, use of steel wire mesh located at short distance downstream was found effective with no consequent pressure drop.

Keywords: Enhancement; Flash Evaporation; OTEC; superheated jet

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397 Bifurcation Analysis of a Delayed Predator-prey Fishery Model with Prey Reserve in Frequency Domain

Authors: Changjin Xu

Abstract:

In this paper, applying frequency domain approach, a delayed predator-prey fishery model with prey reserve is investigated. By choosing the delay τ as a bifurcation parameter, It is found that Hopf bifurcation occurs as the bifurcation parameter τ passes a sequence of critical values. That is, a family of periodic solutions bifurcate from the equilibrium when the bifurcation parameter exceeds a critical value. The length of delay which preserves the stability of the positive equilibrium is calculated. Some numerical simulations are included to justify the theoretical analysis results. Finally, main conclusions are given.

Keywords: Predator-prey model, stability, Hopf bifurcation, frequency domain, Nyquist criterion.

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396 Modeling and Stability Analysis of Delayed Game Network

Authors: Zixin Liu, Jian Yu, Daoyun Xu

Abstract:

This paper aims to establish a delayed dynamical relationship between payoffs of players in a zero-sum game. By introducing Markovian chain and time delay in the network model, a delayed game network model with sector bounds and slope bounds restriction nonlinear function is first proposed. As a result, a direct dynamical relationship between payoffs of players in a zero-sum game can be illustrated through a delayed singular system. Combined with Finsler-s Lemma and Lyapunov stable theory, a sufficient condition guaranteeing the unique existence and stability of zero-sum game-s Nash equilibrium is derived. One numerical example is presented to illustrate the validity of the main result.

Keywords: Game networks, zero-sum game, delayed singular system, nonlinear perturbation, time delay.

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395 Noise Source Identification on Urban Construction Sites Using Signal Time Delay Analysis

Authors: Balgaisha G. Mukanova, Yelbek B. Utepov, Aida G. Nazarova, Alisher Z. Imanov

Abstract:

The problem of identifying local noise sources on a construction site using a sensor system is considered. Mathematical modeling of detected signals on sensors was carried out, considering signal decay and signal delay time between the source and detector. Recordings of noises produced by construction tools were used as a dependence of noise on time. Synthetic sensor data was constructed based on these data, and a model of the propagation of acoustic waves from a point source in the three-dimensional space was applied. All sensors and sources are assumed to be located in the same plane. A source localization method is checked based on the signal time delay between two adjacent detectors and plotting the direction of the source. Based on the two direct lines' crossline, the noise source's position is determined. Cases of one dominant source and the case of two sources in the presence of several other sources of lower intensity are considered. The number of detectors varies from three to eight detectors. The intensity of the noise field in the assessed area is plotted. The signal of a two-second duration is considered. The source is located for subsequent parts of the signal with a duration above 0.04 sec; the final result is obtained by computing the average value.

Keywords: Acoustic model, direction of arrival, inverse source problem, sound localization, urban noises.

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394 Wireless Sensor Networks:Delay Guarentee and Energy Efficient MAC Protocols

Authors: Marwan Ihsan Shukur, Lee Sheng Chyan, Vooi Voon Yap

Abstract:

Wireless sensor networks is an emerging technology that serves as environment monitors in many applications. Yet these miniatures suffer from constrained resources in terms of computation capabilities and energy resources. Limited energy resource in these nodes demands an efficient consumption of that resource either by developing the modules itself or by providing an efficient communication protocols. This paper presents a comprehensive summarization and a comparative study of the available MAC protocols proposed for Wireless Sensor Networks showing their capabilities and efficiency in terms of energy consumption and delay guarantee.

Keywords: MAC (Medium Access Control), SEA (Simple EnergyAware), WSNs (Wireless Sensor Nodes or Networks) RTS (RequestTo Send), CTS (Clear To Send), SYNCH (Synchronize), NS2(Network Simulator 2).

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393 Current Mode Logic Circuits for 10-bit 5GHz High Speed Digital to Analog Converter

Authors: Zhenguo Vincent Chia, Sheung Yan Simon Ng, Minkyu Je

Abstract:

This paper presents CMOS Current Mode Logic (CML) circuits for a high speed Digital to Analog Converter (DAC) using standard CMOS 65nm process. The CML circuits have the propagation delay advantage over its conventional CMOS counterparts due to smaller output voltage swing and tunable bias current. The CML circuits proposed in this paper can achieve a maximum propagation delay of only 9.3ps, which can satisfy the stringent requirement for the 5 GHz high speed DAC application. Another advantage for CML circuits is its dynamic symmetry characteristic resulting in a reduction of an additional inverter. Simulation results show that the proposed CML circuits can operate from 1.08V to 1.3V with temperature ranging from -40 to +120°C.

Keywords: Conventional, Current Mode Logic, DAC, Decoder

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392 Detecting the Nonlinearity in Time Series from Continuous Dynamic Systems Based on Delay Vector Variance Method

Authors: Shumin Hou, Yourong Li, Sanxing Zhao

Abstract:

Much time series data is generally from continuous dynamic system. Firstly, this paper studies the detection of the nonlinearity of time series from continuous dynamics systems by applying the Phase-randomized surrogate algorithm. Then, the Delay Vector Variance (DVV) method is introduced into nonlinearity test. The results show that under the different sampling conditions, the opposite detection of nonlinearity is obtained via using traditional test statistics methods, which include the third-order autocovariance and the asymmetry due to time reversal. Whereas the DVV method can perform well on determining nonlinear of Lorenz signal. It indicates that the proposed method can describe the continuous dynamics signal effectively.

Keywords: Nonlinearity, Time series, continuous dynamics system, DVV method

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391 Comparative Performance Analysis of Fiber Delay Line Based Buffer Architectures for Contention Resolution in Optical WDM Networks

Authors: Manoj Kumar Dutta

Abstract:

Wavelength Division Multiplexing (WDM) technology is the most promising technology for the proper utilization of huge raw bandwidth provided by an optical fiber. One of the key problems in implementing the all-optical WDM network is the packet contention. This problem can be solved by several different techniques. In time domain approach the packet contention can be reduced by incorporating Fiber Delay Lines (FDLs) as optical buffer in the switch architecture. Different types of buffering architectures are reported in literatures. In the present paper a comparative performance analysis of three most popular FDL architectures are presented in order to obtain the best contention resolution performance. The analysis is further extended to consider the effect of different fiber non-linearities on the network performance.

Keywords: WDM network, contention resolution, optical buffering, non-linearity, throughput.

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390 Mean Square Exponential Synchronization of Stochastic Neutral Type Chaotic Neural Networks with Mixed Delay

Authors: Zixin Liu, Huawei Yang, Fangwei Chen

Abstract:

This paper studies the mean square exponential synchronization problem of a class of stochastic neutral type chaotic neural networks with mixed delay. On the Basis of Lyapunov stability theory, some sufficient conditions ensuring the mean square exponential synchronization of two identical chaotic neural networks are obtained by using stochastic analysis and inequality technique. These conditions are expressed in the form of linear matrix inequalities (LMIs), whose feasibility can be easily checked by using Matlab LMI Toolbox. The feedback controller used in this paper is more general than those used in previous literatures. One simulation example is presented to demonstrate the effectiveness of the derived results.

Keywords: Exponential synchronization, stochastic analysis, chaotic neural networks, neutral type system.

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389 Transmission Model for Plasmodium Vivax Malaria: Conditions for Bifurcation

Authors: P. Pongsumpun, I.M. Tang

Abstract:

Plasmodium vivax malaria differs from P. falciparum malaria in that a person suffering from P. vivax infection can suffer relapses of the disease. This is due the parasite being able to remain dormant in the liver of the patients where it is able to re-infect the patient after a passage of time. During this stage, the patient is classified as being in the dormant class. The model to describe the transmission of P. vivax malaria consists of a human population divided into four classes, the susceptible, the infected, the dormant and the recovered. The effect of a time delay on the transmission of this disease is studied. The time delay is the period in which the P. vivax parasite develops inside the mosquito (vector) before the vector becomes infectious (i.e., pass on the infection). We analyze our model by using standard dynamic modeling method. Two stable equilibrium states, a disease free state E0 and an endemic state E1, are found to be possible. It is found that the E0 state is stable when a newly defined basic reproduction number G is less than one. If G is greater than one the endemic state E1 is stable. The conditions for the endemic equilibrium state E1 to be a stable spiral node are established. For realistic values of the parameters in the model, it is found that solutions in phase space are trajectories spiraling into the endemic state. It is shown that the limit cycle and chaotic behaviors can only be achieved with unrealistic parameter values.

Keywords: Equilibrium states, Hopf bifurcation, limit cyclebehavior, local stability, Plasmodium Vivax, time delay.

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388 Optimal Tuning of a Fuzzy Immune PID Parameters to Control a Delayed System

Authors: S. Gherbi, F. Bouchareb

Abstract:

This paper deals with the novel intelligent bio-inspired control strategies, it presents a novel approach based on an optimal fuzzy immune PID parameters tuning, it is a combination of a PID controller, inspired by the human immune mechanism with fuzzy logic. Such controller offers more possibilities to deal with the delayed systems control difficulties due to the delay term. Indeed, we use an optimization approach to tune the four parameters of the controller in addition to the fuzzy function; the obtained controller is implemented in a modified Smith predictor structure, which is well known that it is the most efficient to the control of delayed systems. The application of the presented approach to control a three tank delay system shows good performances and proves the efficiency of the method.

Keywords: Delayed systems, Fuzzy Immune PID, Optimization, Smith predictor.

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387 Analysis of Effect of Pre-Logic Factoring on Cell Based Combinatorial Logic Synthesis

Authors: Padmanabhan Balasubramanian, Bashetty Raghavendra

Abstract:

In this paper, an analysis is presented, which demonstrates the effect pre-logic factoring could have on an automated combinational logic synthesis process succeeding it. The impact of pre-logic factoring for some arbitrary combinatorial circuits synthesized within a FPGA based logic design environment has been analyzed previously. This paper explores a similar effect, but with the non-regenerative logic synthesized using elements of a commercial standard cell library. On an overall basis, the results obtained pertaining to the analysis on a variety of MCNC/IWLS combinational logic benchmark circuits indicate that pre-logic factoring has the potential to facilitate simultaneous power, delay and area optimized synthesis solutions in many cases.

Keywords: Algebraic factoring, Combinational logic synthesis, Standard cells, Low power, Delay optimization, Area reduction.

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386 Computational Modeling of Combustion Wave in Nanoscale Thermite Reaction

Authors: Kyoungjin Kim

Abstract:

Nanoscale thermites such as the composite mixture of nano-sized aluminum and molybdenum trioxide powders possess several technical advantages such as much higher reaction rate and shorter ignition delay, when compared to the conventional energetic formulations made of micron-sized metal and oxidizer particles. In this study, the self-propagation of combustion wave in compacted pellets of nanoscale thermite composites is modeled and computationally investigated by utilizing the activation energy reduction of aluminum particles due to nanoscale particle sizes. The present computational model predicts the speed of combustion wave propagation which is good agreement with the corresponding experiments of thermite reaction. Also, several characteristics of thermite reaction in nanoscale composites are discussed including the ignition delay and combustion wave structures.

Keywords: Nanoparticles, Thermite reaction, Combustion wave, Numerical modeling.

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385 Improving Quality of Business Networks for Information Systems

Authors: Hazem M. El-Bakry, Ahmed Atwan

Abstract:

Computer networks are essential part in computerbased information systems. The performance of these networks has a great influence on the whole information system. Measuring the usability criteria and customers satisfaction on small computer network is very important. In this article, an effective approach for measuring the usability of business network in an information system is introduced. The usability process for networking provides us with a flexible and a cost-effective way to assess the usability of a network and its products. In addition, the proposed approach can be used to certify network product usability late in the development cycle. Furthermore, it can be used to help in developing usable interfaces very early in the cycle and to give a way to measure, track, and improve usability. Moreover, a new approach for fast information processing over computer networks is presented. The entire data are collected together in a long vector and then tested as a one input pattern. Proposed fast time delay neural networks (FTDNNs) use cross correlation in the frequency domain between the tested data and the input weights of neural networks. It is proved mathematically and practically that the number of computation steps required for the presented time delay neural networks is less than that needed by conventional time delay neural networks (CTDNNs). Simulation results using MATLAB confirm the theoretical computations.

Keywords: Usability Criteria, Computer Networks, Fast Information Processing, Cross Correlation, Frequency Domain.

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384 Bandwidth Allocation for ABR Service in Cellular Networks

Authors: Khaja Kamaluddin, Muhammed Yousoof

Abstract:

Available Bit Rate Service (ABR) is the lower priority service and the better service for the transmission of data. On wireline ATM networks ABR source is always getting the feedback from switches about increase or decrease of bandwidth according to the changing network conditions and minimum bandwidth is guaranteed. In wireless networks guaranteeing the minimum bandwidth is really a challenging task as the source is always in mobile and traveling from one cell to another cell. Re establishment of virtual circuits from start to end every time causes the delay in transmission. In our proposed solution we proposed the mechanism to provide more available bandwidth to the ABR source by re-usage of part of old Virtual Channels and establishing the new ones. We want the ABR source to transmit the data continuously (non-stop) inorderto avoid the delay. In worst case scenario at least minimum bandwidth is to be allocated. In order to keep the data flow continuously, priority is given to the handoff ABR call against new ABR call.

Keywords: Bandwidth allocation, Virtual Channel (VC), CBR, ABR, MCR and QOS.

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383 High Speed NP-CMOS and Multi-Output Dynamic Full Adder Cells

Authors: Reza Faghih Mirzaee, Mohammad Hossein Moaiyeri, Keivan Navi

Abstract:

In this paper we present two novel 1-bit full adder cells in dynamic logic style. NP-CMOS (Zipper) and Multi-Output structures are used to design the adder blocks. Characteristic of dynamic logic leads to higher speeds than the other standard static full adder cells. Using HSpice and 0.18┬Ám CMOS technology exhibits a significant decrease in the cell delay which can result in a considerable reduction in the power-delay product (PDP). The PDP of Multi-Output design at 1.8v power supply is around 0.15 femto joule that is 5% lower than conventional dynamic full adder cell and at least 21% lower than other static full adders.

Keywords: Bridge Style, Dynamic Logic, Full Adder, HighSpeed, Multi Output, NP-CMOS, Zipper.

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382 A high Speed 8 Transistor Full Adder Design Using Novel 3 Transistor XOR Gates

Authors: Shubhajit Roy Chowdhury, Aritra Banerjee, Aniruddha Roy, Hiranmay Saha

Abstract:

The paper proposes the novel design of a 3T XOR gate combining complementary CMOS with pass transistor logic. The design has been compared with earlier proposed 4T and 6T XOR gates and a significant improvement in silicon area and power-delay product has been obtained. An eight transistor full adder has been designed using the proposed three-transistor XOR gate and its performance has been investigated using 0.15um and 0.35um technologies. Compared to the earlier designed 10 transistor full adder, the proposed adder shows a significant improvement in silicon area and power delay product. The whole simulation has been carried out using HSPICE.

Keywords: XOR gate, full adder, improvement in speed, area minimization, transistor count minimization.

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381 A New Cut–Through Mechanism in IEEE 802.16 Mesh Networks

Authors: Yi-Ting Mai, Chun-Chuan Yang, Cheng-Jung Wen

Abstract:

IEEE 802.16 is a new wireless technology standard, it has some advantages, including wider coverage, higher bandwidth, and QoS support. As the new wireless technology for last mile solution, there are designed two models in IEEE 802.16 standard. One is PMP (point to multipoint) and the other is Mesh. In this paper we only focus on IEEE 802.16 Mesh model. According to the IEEE 802.16 standard description, Mesh model has two scheduling modes, centralized and distributed. Considering the pros and cons of the two scheduling, we present the combined scheduling QoS framework that the BS (Base Station) controls time frame scheduling and selects the shortest path from source to destination directly. On the other hand, we propose the Expedited Queue mechanism to cut down the transmission time. The EQ mechanism can reduce a lot of end-to-end delay in our QoS framework. Simulation study has shown that the average delay is smaller than contrasts. Furthermore, our proposed scheme can also achieve higher performance.

Keywords: IEEE 802.16 Mesh, Scheduling, Expedited Queue, QoS.

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380 Robust Stability Criteria for Uncertain Genetic Regulatory Networks with Time-Varying Delays

Authors: Wenqin Wang, Shouming Zhong

Abstract:

This paper presents the robust stability criteria for uncertain genetic regulatory networks with time-varying delays. One key point of the criterion is that the decomposition of the matrix ˜D into ˜D = ˜D1 + ˜D2. This decomposition corresponds to a decomposition of the delayed terms into two groups: the stabilizing ones and the destabilizing ones. This technique enables one to take the stabilizing effect of part of the delayed terms into account. Meanwhile, by choosing an appropriate new Lyapunov functional, a new delay-dependent stability criteria is obtained and formulated in terms of linear matrix inequalities (LMIs). Finally, numerical examples are presented to illustrate the effectiveness of the theoretical results.

Keywords: Genetic regulatory network, Time-varying delay, Uncertain system, Lyapunov-Krasovskii functional

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379 Providing On-Demand Path and Arrival Time Information Considering Realtime Delays of Buses

Authors: Yoshifumi Ishizaki, Naoki Kanatani, Masaki Ito, Toshihiko Sasama, Takao Kawamura, Kazunori Sugahara

Abstract:

This paper demonstrates the bus location system for the route bus through the experiment in the real environment. A bus location system is a system that provides information such as the bus delay and positions. This system uses actual services and positions data of buses, and those information should match data on the database. The system has two possible problems. One, the system could cost high in preparing devices to get bus positions. Two, it could be difficult to match services data of buses. To avoid these problems, we have developed this system at low cost and short time by using the smart phone with GPS and the bus route system. This system realizes the path planning considering bus delay and displaying position of buses on the map. The bus location system was demonstrated on route buses with smart phones for two months.

Keywords: Route Bus, Path Planning System, GPS, Smart Phone.

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378 Synthesis and Simulation of Enhanced Buffer Router vs. Virtual Channel Router in NOC ON Cadence

Authors: Bhavana Prakash Shrivastava, Kavita Khare

Abstract:

This paper presents a synthesis and simulation of proposed enhanced buffer. The design provides advantages of both buffer and bufferless network for that two cross bar switches are used. The concept of virtual channel (VC) is eliminated from the previous design by using an efficient flow-control scheme that uses the storage already present in pipelined channels in place of explicit input VCBs. This can be addressed by providing enhanced buffers on the bufferless link and creating two virtual networks. With this approach, VCBs act as distributed FIFO buffers. Without VCBs or VCs, deadlock prevention is achieved by duplicating physical channels. An enhanced buffer provides a function of hand shaking by providing a ready valid handshake signal and two bit storage. Through this design the power is reduced to 15.65% and delay is reduced to 97.88% with respect to virtual channel router.

Keywords: Enhanced buffer, Gate delay, NOC, VCs, VCB.

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377 The System Identification and PID Lead-lag Control for Two Poles Unstable SOPDT Process by Improved Relay Method

Authors: V. K. Singh, P. K. Padhy

Abstract:

This paper describes identification of the two poles unstable SOPDT process, especially with large time delay. A new modified relay feedback identification method for two poles unstable SOPDT process is proposed. Furthermore, for the two poles unstable SOPDT process, an additional Derivative controller is incorporated parallel with relay to relax the constraint on the ratio of delay to the unstable time constant, so that the exact model parameters of unstable processes can be identified. To cope with measurement noise in practice, a low pass filter is suggested to get denoised output signal toimprove the exactness of model parameter of unstable process. PID Lead-lag tuning formulas are derived for two poles unstable (SOPDT) processes based on IMC principle. Simulation example illustrates the effectiveness and the simplicity of the proposed identification and control method.

Keywords: IMC structure, PID Lead-lag controller, Relayfeedback, SOPDT

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376 Evaluation of University Technology Malaysia on Campus Transport Access Management

Authors: Arash Moradkhani Roshandeh, Othman Che Puan

Abstract:

Access Management is the proactive management of vehicular access points to land parcels adjacent to all manner of roadways. Good access management promotes safe and efficient use of the transportation network. This study attempts to utilize archived data from the University Technology of Malaysia on-campus area to assess the accuracy with which access management display some benefits. Results show that usage of access management reduces delay and fewer crashes. Clustered development can improve walking, cycling and transit travel, reduce parking requirements and improve emergency responses. Effective Access Management planning can also reduce total roadway facility costs by reducing the number of driveways and intersections. At the end after presenting recommendations some of the travel impact, and benefits that can be derived if these suggestions are implemented have been summarized with the related comments.

Keywords: Access Management, Delay, Density, Traffic Flow

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375 The Simulation and Realization of Input-Buffer Scheduling Algorithm in Satellite Switching System

Authors: Yi Zhang, Quan Zhou, Jun Li, Yanlang Hu

Abstract:

Scheduling algorithm is a key technology in satellite switching system with input-buffer. In this paper, a new scheduling algorithm and its realization are proposed. Based on Crossbar switching fabric, the algorithm adopts serial scheduling strategy and adjusts the output port arbitrating strategy for the better equity of every port. Consequently, it increases the matching probability. The algorithm can greatly reduce the scheduling delay and cell loss rate. The analysis and simulation results by OPNET show that the proposed algorithm has the better performance than others in average delay and cell loss rate, and has the equivalent complexity. On the basis of these results, the hardware realization and simulation based on FPGA are completed, which validate the feasibility of the new scheduling algorithm.

Keywords: Scheduling algorithm, input-buffer, serial scheduling, hardware design.

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374 Design and Analysis of a Low Power High Speed 1 Bit Full Adder Cell Based On TSPC Logic with Multi-Threshold CMOS

Authors: Ankit Mitra

Abstract:

An adder is one of the most integral component of a digital system like a digital signal processor or a microprocessor. Being an extremely computationally intensive part of a system, the optimization for speed and power consumption of the adder is of prime importance. In this paper we have designed a 1 bit full adder cell based on dynamic TSPC logic to achieve high speed operation. A high threshold voltage sleep transistor is used to reduce the static power dissipation in standby mode. The circuit is designed and simulated in TSPICE using TSMC 180nm CMOS process. Average power consumption, delay and power-delay product is measured which showed considerable improvement in performance over the existing full adder designs.

Keywords: CMOS, TSPC, MTCMOS, ALU, Clock gating, power gating, pipelining.

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373 A New Protocol for Concealed Data Aggregation in Wireless Sensor Networks

Authors: M. Abbasi Dezfouli, S. Mazraeh, M. H. Yektaie

Abstract:

Wireless sensor networks (WSN) consists of many sensor nodes that are placed on unattended environments such as military sites in order to collect important information. Implementing a secure protocol that can prevent forwarding forged data and modifying content of aggregated data and has low delay and overhead of communication, computing and storage is very important. This paper presents a new protocol for concealed data aggregation (CDA). In this protocol, the network is divided to virtual cells, nodes within each cell produce a shared key to send and receive of concealed data with each other. Considering to data aggregation in each cell is locally and implementing a secure authentication mechanism, data aggregation delay is very low and producing false data in the network by malicious nodes is not possible. To evaluate the performance of our proposed protocol, we have presented computational models that show the performance and low overhead in our protocol.

Keywords: Wireless Sensor Networks, Security, Concealed Data Aggregation.

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