Search results for: DC Voltage Regulator
Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 961

Search results for: DC Voltage Regulator

361 A Current-mode Continuous-time Sigma-delta Modulator based on Translinear Loop Principle

Authors: P. Jelodarian , E. Farshidi

Abstract:

In this paper, a new approach for design of a fully differential second order current mode continuous-time sigma-delta modulator is presented. For circuit implementation, square root domain (SRD) translinear loop based on floating-gate MOS transistors that operate in saturation region is employed. The modulator features, low supply voltage, low power consumption (8mW) and high dynamic range (55dB). Simulation results confirm that this design is suitable for data converters.

Keywords: Sigma-delta, current-mode, translinear loop, geometric mean, squarer/divider.

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360 Numerical Simulation of Electric and Hydrodynamic Fields Distribution in a Dielectric Liquids Electrofilter Cell

Authors: Narcis C. Ostahie, Tudor Sajin

Abstract:

In this paper a numerical simulation of electric and hydrodynamic fields distribution in an electrofilter for dielectric liquids cell is made. The simulation is made with the purpose to determine the trajectory of particles that moves under the action of external force in an electric and hydrodynamic field created inside of an electrofilter for dielectric liquids. Particle trajectory is analyzed for a dielectric liquid-solid particles suspension.

Keywords: Dielectric liquids, electrohydrodynamics, energy, high voltage, particles

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359 Optimal Assessment of Faulted Area around an Industrial Customer for Critical Sag Magnitudes

Authors: Marios N. Moschakis

Abstract:

This paper deals with the assessment of faulted area around an industrial customer connected to a particular electric grid that will cause a certain sag magnitude on this customer. The faulted (critical or exposed) area’s length is calculated by adding all line lengths in the neighborhood of the critical node (customer). The applied method is the so-called Method of Critical Distances. By using advanced short-circuit analysis, the Critical Area can be accurately calculated for radial and meshed power networks due to all symmetrical and asymmetrical faults. For the demonstration of the effectiveness of the proposed methodology, a study case is used.

Keywords: Critical area, fault-induced voltage sags, industrial customers, power quality.

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358 Comparison of Full Graph Methods of Switched Circuits Solution

Authors: Zdeňka Dostálová, David Matoušek, Bohumil Brtnik

Abstract:

As there are also graph methods of circuit analysis in addition to algebraic methods, it is, in theory, clearly possible to carry out an analysis of a whole switched circuit in two-phase switching exclusively by the graph method as well. This article deals with two methods of full-graph solving of switched circuits: by transformation graphs and by two-graphs. It deals with the circuit switched capacitors and the switched current, too. All methods are presented in an equally detailed steps to be able to compare.

Keywords: Switched capacitors of two phases, switched currents of two phases, transformation graph, two-graph, Mason's formula, voltage transfer, summary graph.

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357 Design of Novel SCR-based ESD Protection Device for I/O Clamp in BCD Process

Authors: Yong-Seo Koo, Jin-Woo Jung, Byung-Seok Lee, Dong-Su Kim, Yil-Suk Yang

Abstract:

In this paper, a novel LVTSCR-based device for electrostatic discharge (ESD) protection of integrated circuits (ICs) is designed, fabricated and characterized. The proposed device is similar to the conventional LVTSCR but it has an embedded PMOSFET in the anode n-well to enhance the turn on speed, the clamping capability and the robustness. This is possible because the embedded PMOSFET provides the sub-path of ESD discharge current. The TLP, HBM and MM testing are carried out to verify the ESD performance of the proposed devices, which are fabricated in 0.35um (Bipolar-CMOS-DMOS) BCDMOS process. The device has the robustness of 70mA/um that is higher about 60mA/um than the LVTSCR, approximately.

Keywords: ESD Protection, grounded gate NMOS (GGNMOS), low trigger voltage SCR (LVTSCR)

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356 Triboelectric Separation of Binary Plastic Mixture

Authors: M. Saeki

Abstract:

This paper presents the results of an experimental study on the performance of a triboelectric separator of plastic mixtures used for recycling. The separator consists of four cylindrical electrodes. The principle behind the separation technique is based on the difference in the Coulomb force acting on the plastic particles after triboelectric charging. The separation of mixtures of acrylonitrile butadiene styrene (ABS) and polystyrene (PS) using this method was studied. The effects of the triboelectric charging time and applied voltage on the separation efficiency were investigated. The experimental results confirm that it is possible to obtain a high purity and recovery rate for the initial compositions considered in this study.

Keywords: Coulomb force, recycling, triboelectric separator, waste plastics.

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355 An Induction Motor Drive System with Intelligent Supervisory Control for Water Networks Including Storage Tank

Authors: O. S. Ebrahim, K. O. Shawky, M. A. Badr, P. K. Jain

Abstract:

This paper describes an efficient; low-cost; high-availability; induction motor (IM) drive system with intelligent supervisory control for water distribution networks including storage tank. To increase the operational efficiency and reduce cost, the IM drive system includes main pumping unit and an auxiliary voltage source inverter (VSI) fed unit. The main unit comprises smart star/delta starter, regenerative fluid clutch, switched VAR compensator, and hysteresis liquid-level controller. Three-state energy saving mode (ESM) is defined at no-load and a logic algorithm is developed for best energetic cost reduction. To reduce voltage sag, the supervisory controller operates the switched VAR compensator upon motor starting. To provide smart star/delta starter at low cost, a method based on current sensing is developed for interlocking, malfunction detection, and life–cycles counting and used to synthesize an improved fuzzy logic (FL) based availability assessment scheme. Furthermore, a recurrent neural network (RNN) full state estimator is proposed to provide sensor fault-tolerant algorithm for the feedback control. The auxiliary unit is working at low flow rates and improves the system efficiency and flexibility for distributed generation during islanding mode. Compared with doubly-fed IM, the proposed one ensures 30% working throughput under main motor/pump fault conditions, higher efficiency, and marginal cost difference. This is critically important in case of water networks. Theoretical analysis, computer simulations, cost study, as well as efficiency evaluation, using timely cascaded energy-conservative systems, are performed on IM experimental setup to demonstrate the validity and effectiveness of the proposed drive and control.

Keywords: Artificial Neural Network, ANN, Availability Assessment, Cloud Computing, Energy Saving, Induction Machine, IM, Supervisory Control, Fuzzy Logic, FL, Pumped Storage.

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354 Transient Energy and its Impact on Transmission Line Faults

Authors: Mamta Patel, R. N. Patel

Abstract:

Transmission and distribution lines are vital links between the generating unit and consumers. They are exposed to atmosphere, hence chances of occurrence of fault in transmission line is very high which has to be immediately taken care of in order to minimize damage caused by it. In this paper Discrete wavelet transform of voltage signals at the two ends of transmission lines have been analyzed. The transient energy of the detail information of level five is calculated for different fault conditions. It is observed that the variation of transient energy of healthy and faulted line can give important information which can be very useful in classifying and locating the fault.

Keywords: Wavelet, Discrete wavelet transform, Multiresolution analysis, Transient energy

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353 Analysis of a Novel Strained Silicon RF LDMOS

Authors: V.Fathipour, M. A. Malakootian, S. Fathipour, M. Fathipour

Abstract:

In this paper we propose a novel RF LDMOS structure which employs a thin strained silicon layer at the top of the channel and the N-Drift region. The strain is induced by a relaxed Si0.8 Ge0.2 layer which is on top of a compositionally graded SiGe buffer. We explain the underlying physics of the device and compare the proposed device with a conventional LDMOS in terms of energy band diagram and carrier concentration. Numerical simulations of the proposed strained silicon laterally diffused MOS using a 2 dimensional device simulator indicate improvements in saturation and linear transconductance, current drivability, cut off frequency and on resistance. These improvements are however accompanied with a suppression in the break down voltage.

Keywords: High Frequency MOSFET, Design of RF LDMOS, Strained-Silicon, LDMOS.

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352 General Purpose Pulse Width Modulation Based Sliding Mode Controller for Buck DC-DC

Authors: M.Bensaada , A.Boudghene Stambouli , M.Bekhti, A. Bellar, L. Boukhris

Abstract:

This paper is a simple and systematic approaches to the design and analysis a pulse width modulation (PWM) based sliding mode controller for buck DC-DC Converters. Various aspects of the design, including the practical problems and the proposed solutions, are detailed. However, these control strategies can't compensate for large load current and input voltage variations. In this paper, a new control strategy by compromising both schemes advantages and avoiding their drawbacks is proposed, analyzed and simulated.

Keywords: Buck, DC/DC converters, sliding mode control, pulse width modulation.

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351 New Design Methodologies for High Speed Low Power XOR-XNOR Circuits

Authors: Shiv Shankar Mishra, S. Wairya, R. K. Nagaria, S. Tiwari

Abstract:

New methodologies for XOR-XNOR circuits are proposed to improve the speed and power as these circuits are basic building blocks of many arithmetic circuits. This paper evaluates and compares the performance of various XOR-XNOR circuits. The performance of the XOR-XNOR circuits based on TSMC 0.18μm process models at all range of the supply voltage starting from 0.6V to 3.3V is evaluated by the comparison of the simulation results obtained from HSPICE. Simulation results reveal that the proposed circuit exhibit lower PDP and EDP, more power efficient and faster when compared with best available XOR-XNOR circuits in the literature.

Keywords: Exclusive-OR (XOR), Exclusive-NOR (XNOR), High speed, Low power, Arithmetic Circuits.

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350 Harmonic Reduction In Three-Phase Parallel Connected Inverter

Authors: M.A.A. Younis, N. A. Rahim, S. Mekhilef

Abstract:

This paper presents the design and analysis of a parallel connected inverter configuration of. The configuration consists of parallel connected three-phase dc/ac inverter. Series resistors added to the inverter output to maintain same current in each inverter of the two parallel inverters, and to reduce the circulating current in the parallel inverters to the minimum. High frequency third harmonic injection PWM (THIPWM) employed to reduce the total harmonic distortion and to make maximum use of the voltage source. DSP was used to generate the THIPWM and the control algorithm for the converter. Selected experimental results have been shown to validate the proposed system.

Keywords: Three-phase inverter, Third harmonic injection PWM, inverters parallel connection.

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349 Bifurcation and Chaos of the Memristor Circuit

Authors: Wang Zhulin, Min Fuhong, Peng Guangya, Wang Yaoda, Cao Yi

Abstract:

In this paper, a magnetron memristor model based on hyperbolic sine function is presented and the correctness proved by studying the trajectory of its voltage and current phase, and then a memristor chaotic system with the memristor model is presented. The phase trajectories and the bifurcation diagrams and Lyapunov exponent spectrum of the magnetron memristor system are plotted by numerical simulation, and the chaotic evolution with changing the parameters of the system is also given. The paper includes numerical simulations and mathematical model, which confirming that the system, has a wealth of dynamic behavior.

Keywords: Memristor, chaotic circuit, dynamical behavior, chaotic system.

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348 GA based Optimal Sizing and Placement of Distributed Generation for Loss Minimization

Authors: Deependra Singh, Devender Singh, K. S. Verma

Abstract:

This paper addresses a novel technique for placement of distributed generation (DG) in electric power systems. A GA based approach for sizing and placement of DG keeping in view of system power loss minimization in different loading conditions is explained. Minimal system power loss is obtained under voltage and line loading constraints. Proposed strategy is applied to power distribution systems and its effectiveness is verified through simulation results on 16, 37-bus and 75-bus test systems.

Keywords: Distributed generation (DG), Genetic algorithms (GA), optimal sizing and placement, Power loss.

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347 Effect of Field Dielectric Material on Performance of InGaAs Power LDMOSFET

Authors: Yashvir Singh, Swati Chamoli

Abstract:

In this paper, a power laterally-diffused metal-oxide-semiconductor field-effect transistor (LDMOSFET) on In0.53Ga0.47As is presented. The device utilizes a thicker field-oxide with low dielectric constant under the field-plate in order to achieve possible reduction in device capacitances and reduced-surface-field effect. Using 2D numerical simulations, performance of the proposed device is analyzed and compared with that of the conventional LDMOSFET. The proposed structure provides 50% increase in the breakdown voltage, 21% increase in transit frequency, and 72% improvement in figure-of-merit over the conventional device for same cell pitch.

Keywords: InGaAs, dielectric, lateral, power MOSFET.

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346 Emotions Triggered by Children’s Literature Images

Authors: A. Breda, C. Cruz

Abstract:

The role of images/illustrations in communicating meanings and triggering emotions assumes an increasingly relevant role in contemporary texts, regardless of the age group for which they are intended or the nature of the texts that host them. It is no coincidence that children's books are full of illustrations and that the image/text ratio decreases as the age group grows. The vast majority of children's books can be considered as multimodal texts containing text and images/illustrations, interacting with each other, to provide the young reader with a broader and more creative understanding of the book's narrative. This interaction is very diverse, ranging from images/illustrations that are not essential for understanding the storytelling to those that contribute significantly to the meaning of the story. Usually, these books are also read by adults, namely by parents, educators, and teachers who act as mediators between the book and the children, explaining aspects that are or seem to be too complex for the child's context. It should be noted that there are books labeled as children's books, that are clearly intended for both children and adults. In this work, following a qualitative and interpretative methodology based on written productions, participant observation, and field notes, we will describe the perceptions of future teachers of the 1st cycle of basic education, attending a master’s degree at a Portuguese university, about the role of the image in literary and non-literary texts, namely in mathematical texts, and how these can constitute precious resources for emotional regulation and for the design of creative didactic situations. The analysis of the collected data allowed us to obtain evidence regarding the evolution of the participants' perception regarding the crucial role of images in children's literature, not only as an emotional regulator for young readers but also as a creative source for the design of meaningful didactical situations, crossing other scientific areas, other than the mother tongue, namely mathematics.

Keywords: Children’s literature, emotions, multimodal texts, soft skills.

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345 Complementary Energy Path Adiabatic Logic based Full Adder Circuit

Authors: Shipra Upadhyay , R. K. Nagaria, R. A. Mishra

Abstract:

In this paper, we present the design and experimental evaluation of complementary energy path adiabatic logic (CEPAL) based 1 bit full adder circuit. A simulative investigation on the proposed full adder has been done using VIRTUOSO SPECTRE simulator of cadence in 0.18μm UMC technology and its performance has been compared with the conventional CMOS full adder circuit. The CEPAL based full adder circuit exhibits the energy saving of 70% to the conventional CMOS full adder circuit, at 100 MHz frequency and 1.8V operating voltage.

Keywords: Adiabatic, CEPAL, full adder, power clock

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344 Loss Analysis by Loading Conditions of Distribution Transformers

Authors: A. Bozkurt, C. Kocatepe, R. Yumurtaci, İ. C. Tastan, G. Tulun

Abstract:

Efficient use of energy, the increase in demand of energy and also with the reduction of natural energy sources, has improved its importance in recent years. Most of the losses in the system from electricity produced until the point of consumption is mostly composed by the energy distribution system. In this study, analysis of the resulting loss in power distribution transformer and distribution power cable is realized which are most of the losses in the distribution system. Transformer losses in the real distribution system are analyzed by CYME Power Engineering Software program. These losses are disclosed for different voltage levels and different loading conditions.

Keywords: Distribution system, distribution transformer, power cable, technical losses.

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343 Noise Analysis of Single-Ended Input Differential Amplifier using Stochastic Differential Equation

Authors: Tarun Kumar Rawat, Abhirup Lahiri, Ashish Gupta

Abstract:

In this paper, we analyze the effect of noise in a single- ended input differential amplifier working at high frequencies. Both extrinsic and intrinsic noise are analyzed using time domain method employing techniques from stochastic calculus. Stochastic differential equations are used to obtain autocorrelation functions of the output noise voltage and other solution statistics like mean and variance. The analysis leads to important design implications and suggests changes in the device parameters for improved noise characteristics of the differential amplifier.

Keywords: Single-ended input differential amplifier, Noise, stochastic differential equation, mean and variance.

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342 Safety Compliance of Substation Earthing Design

Authors: A. Hellany, M.Nagrial, M. Nassereddine, J. Rizk

Abstract:

As new challenges emerge in power electrical workplace safety, it is the responsibility of the systems designer to seek out new approaches and solutions that address them. Design decisions made today will impact cost, safety and serviceability of the installed systems for 40 or 50 years during the useful life for the owner. Studies have shown that this cost is an order of magnitude of 7 to 10 times the installed cost of the power distribution equipment. This paper reviews some aspects of earthing system design in power substation surrounded by residential houses. The electrical potential rise and split factors are discussed and a few recommendations are provided to achieve a safety voltage in the area beyond the boundary of the substation.

Keywords: EPR, Split Factor, Earthing Design

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341 An 8-Bit, 100-MSPS Fully Dynamic SAR ADC for Ultra-High Speed Image Sensor

Authors: F. Rarbi, D. Dzahini, W. Uhring

Abstract:

In this paper, a dynamic and power efficient 8-bit and 100-MSPS Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) is presented. The circuit uses a non-differential capacitive Digital-to-Analog (DAC) architecture segmented by 2. The prototype is produced in a commercial 65-nm 1P7M CMOS technology with 1.2-V supply voltage. The size of the core ADC is 208.6 x 103.6 µm2. The post-layout noise simulation results feature a SNR of 46.9 dB at Nyquist frequency, which means an effective number of bit (ENOB) of 7.5-b. The total power consumption of this SAR ADC is only 1.55 mW at 100-MSPS. It achieves then a figure of merit of 85.6 fJ/step.

Keywords: CMOS analog to digital converter, dynamic comparator, image sensor application, successive approximation register.

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340 Mathematical Modeling of Machining Parameters in Electrical Discharge Machining of FW4 Welded Steel

Authors: M.R.Shabgard, R.M.Shotorbani

Abstract:

FW4 is a newly developed hot die material widely used in Forging Dies manufacturing. The right selection of the machining conditions is one of the most important aspects to take into consideration in the Electrical Discharge Machining (EDM) of FW4. In this paper an attempt has been made to develop mathematical models for relating the Material Removal Rate (MRR), Tool Wear Ratio (TWR) and surface roughness (Ra) to machining parameters (current, pulse-on time and voltage). Furthermore, a study was carried out to analyze the effects of machining parameters in respect of listed technological characteristics. The results of analysis of variance (ANOVA) indicate that the proposed mathematical models, can adequately describe the performance within the limits of the factors being studied.

Keywords: Electrical Discharge Machining (EDM), linearregression technique, Response Surface Methodology (RSM)

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339 A Dynamic Filter for Removal DC - Offset In Current and Voltage Waveforms

Authors: Khaled M.EL-Naggar

Abstract:

In power systems, protective relays must filter their inputs to remove undesirable quantities and retain signal quantities of interest. This job must be performed accurate and fast. A new method for filtering the undesirable components such as DC and harmonic components associated with the fundamental system signals. The method is s based on a dynamic filtering algorithm. The filtering algorithm has many advantages over some other classical methods. It can be used as dynamic on-line filter without the need of parameters readjusting as in the case of classic filters. The proposed filter is tested using different signals. Effects of number of samples and sampling window size are discussed. Results obtained are presented and discussed to show the algorithm capabilities.

Keywords: Protection, DC-offset, Dynamic Filter, Estimation.

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338 Dynamic Stability of Beams with Piezoelectric Layers Located on a Continuous Elastic Foundation

Authors: A. R. Nezamabadi, M. Karami Khorramabadi

Abstract:

This paper studies dynamic stability of homogeneous beams with piezoelectric layers subjected to periodic axial compressive load that is simply supported at both ends lies on a continuous elastic foundation. The displacement field of beam is assumed based on Bernoulli-Euler beam theory. Applying the Hamilton's principle, the governing dynamic equation is established. The influences of applied voltage, foundation coefficient and piezoelectric thickness on the unstable regions are presented. To investigate the accuracy of the present analysis, a compression study is carried out with a known data.

Keywords: Dynamic stability, Homogeneous graded beam-Piezoelectric layer, Harmonic balance method.

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337 Mechanical Modeling Issues in Optimization of Dynamic Behavior of RF MEMS Switches

Authors: Suhas K, Sripadaraja K

Abstract:

This paper details few mechanical modeling and design issues of RF MEMS switches. We concentrate on an electrostatically actuated broad side series switch; surface micromachined with a crab leg membrane. The same results are extended to any complex structure. With available experimental data and fabrication results, we present the variation in dynamic performance and compliance of the switch with reference to few design issues, which we find are critical in deciding the dynamic behavior of the switch, without compromise on the RF characteristics. The optimization of pull in voltage, transient time and resonant frequency with regard to these critical design parameters are also presented.

Keywords: Microelectromechanical Systems (MEMS), RadioFrequency MEMS, Modeling, Actuators

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336 Bias Stability of a-IGZO TFT and a new Shift-Register Design Suitable for a-IGZO TFT

Authors: Young Wook Lee, Sun-Jae Kim, Soo-Yeon Lee, Moon-Kyu Song, Woo-Geun Lee Min-Koo Han

Abstract:

We have fabricated a-IGZO TFT and investigated the stability under positive DC and AC bias stress. The threshold voltage of a-IGZO TFT shifts positively under those biases, and that reduces on-current. For this reason, conventional shift-register circuit employing TFTs which stressed by positive bias will be unstable, may do not work properly. We have designed a new 6-transistor shift-register, which has less transistors than prior circuits. The TFTs of the proposed shift-register are not suffering from positive DC or AC stress, mainly kept unbiased. Despite the compact design, the stable output signal was verified through the SPICE simulation even under RC delay of clock signal.

Keywords: Indium Gallium Zinc Oxide (IGZO), Thin FilmTransistor (TFT), shift-register

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335 Characterization of the In0.53Ga0.47As n+nn+ Photodetectors

Authors: Fatima Zohra Mahi, Luca Varani

Abstract:

We present an analytical model for the calculation of the sensitivity, the spectral current noise and the detective parameter for an optically illuminated In0.53Ga0.47As n+nn+ diode. The photocurrent due to the excess carrier is obtained by solving the continuity equation. Moreover, the current noise level is evaluated at room temperature and under a constant voltage applied between the diode terminals. The analytical calculation of the current noise in the n+nn+ structure is developed by considering the free carries fluctuations. The responsivity and the detection parameter are discussed as functions of the doping concentrations and the emitter layer thickness in one-dimensional homogeneous n+nn+ structure.

Keywords: Responsivity, detection parameter, photo-detectors, continuity equation, current noise.

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334 A Low Voltage High Linearity CMOS Gilbert Cell Using Charge Injection Method

Authors: Raheleh Hedayati, Sanaz Haddadian, Hooman Nabovati

Abstract:

A 2.4GHz (RF) down conversion Gilbert Cell mixer, implemented in a 0.18-μm CMOS technology with a 1.8V supply, is presented. Current bleeding (charge injection) technique has been used to increase the conversion gain and the linearity of the mixer. The proposed mixer provides 10.75 dB conversion gain ( C G ) with 14.3mw total power consumption. The IIP3 and 1-dB compression point of the mixer are 8dbm and -4.6dbm respectively, at 300 MHz IF frequencies. Comparing the current design against the conventional mixer design, demonstrates better performance in the conversion gain, linearity, noise figure and port-to-port isolation.

Keywords: Mixer, Gilbert Cell, Charge Injection, RFIC, CMOSTechnology.

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333 Stability of Homogeneous Smart Beams based on the First Order Shear Deformation Theory Located on a Continuous Elastic Foundation

Authors: A. R. Nezamabadi, M. Karami Khorramabadi

Abstract:

This paper studies stability of homogeneous beams with piezoelectric layers subjected to axial load that is simply supported at both ends lies on a continuous elastic foundation. The displacement field of beam is assumed based on first order shear deformation beam theory. Applying the Hamilton's principle, the governing equation is established. The influences of applied voltage, dimensionless geometrical parameter and foundation coefficient on the stability of beam are presented. To investigate the accuracy of the present analysis, a compression study is carried out with a known data.

Keywords: Stability, Homogeneous beam- Piezoelectric layer

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332 Novel Sinusoidal Pulse Width Modulation with Least Correlated Noise

Authors: Shiang-Hwua Yu, Han-Sheng Tseng

Abstract:

This paper presents a novel sinusoidal modulation scheme that features least correlated noise and high linearity. The modulation circuit, which is composed of a quantizer, a resonator, and a comparator, is capable of eliminating correlated modulation noise while doing modulation. The proposed modulation scheme combined with the linear quadratic optimal control is applied to a single-phase voltage source inverter and validated with the experiment results. The experiments show that the inverter supplies stable 60Hz 110V AC power with a total harmonic distortion of less than 1%, under the DC input variation from 190 V to 300 V and the output power variation from 0 to 600 W.

Keywords: Pulse width modulation, feedback dithering, linear quadratic control, inverter.

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