Search results for: readout circuit.

Authors: Hyun-Ho Lee, Kee-Won Kim

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The arithmetic operations over GF(2m) have been extensively used in error correcting codes and public-key cryptography schemes. Finite field arithmetic includes addition, multiplication, division and inversion operations. Addition is very simple and can be implemented with an extremely simple circuit. The other operations are much more complex. The multiplication is the most important for cryptosystems, such as the elliptic curve cryptosystem, since computing exponentiation, division, and computing multiplicative inverse can be performed by computing multiplication iteratively. In this paper, we present a parallel computation algorithm that operates Montgomery multiplication over finite field using redundant basis. Also, based on the multiplication algorithm, we present an efficient semi-systolic multiplier over finite field. The multiplier has less space and time complexities compared to related multipliers. As compared to the corresponding existing structures, the multiplier saves at least 5% area, 50% time, and 53% area-time (AT) complexity. Accordingly, it is well suited for VLSI implementation and can be easily applied as a basic component for computing complex operations over finite field, such as inversion and division operation.

Keywords: Finite field, Montgomery multiplication, systolic array, cryptography.

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Authors: M. Nirmala

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Power quality in terms of power factor, THD and precisely regulated output voltage are the major key factors for efficient operation of power electronic converters. This paper presents an easy and effective active wave shaping control scheme for the pulsed input current drawn by the uncontrolled diode bridge rectifier thereby achieving power factor nearer to unity and also satisfying the THD specifications. It also regulates the output DC-bus voltage. CCM boost power factor correction with constant frequency operation features smaller inductor current ripple resulting in low RMS currents on inductor and switch thus leading to low electromagnetic interference. The objective of this work is to develop an active PFC control circuit using CCM boost converter implementing variable duty cycle control. The proposed scheme eliminates inductor current sensing requirements yet offering good performance and satisfactory results for maintaining the power quality. Simulation results have been presented which covers load changes also.

Keywords: CCM Boost converter, Power factor Correction, Total harmonic distortion, Variable Duty Cycle.

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Authors: Ioannis Binas, Marios Moschakis

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Electrical faults in transmission and distribution networks can have great impact on the electrical equipment used. Fault effects depend on the characteristics of the fault as well as the network itself. It is important to anticipate the network’s behavior during faults when planning a new equipment installation, as well as troubleshooting. Moreover, working backwards, we could be able to estimate the characteristics of the fault when checking the perceived effects. Different transformer winding connections dominantly used in the Greek power transfer and distribution networks and the effects of 1-phase to neutral, phase-to-phase, 2-phases to neutral and 3-phase faults on different locations of the network were simulated in order to present voltage sag characteristics. The study was performed on a generic network with three steps down transformers on two voltage level buses (one 150 kV/20 kV transformer and two 20 kV/0.4 kV). We found that during faults, there are significant changes both on voltage magnitudes and on phase angles. The simulations and short-circuit analysis were performed using the PSCAD simulation package. This paper presents voltage characteristics calculated for the simulated network, with different approaches on the transformer winding connections during symmetrical and asymmetrical faults on various locations.

Keywords: Phase angle shift, power quality, transformer winding connections, voltage sag propagation.

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Authors: Jie Jin

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In this paper, a new CMOS current-mode single input and multi-outputs (SIMO) universal filter and quadrature oscillator with a similar circuit are proposed. The circuits only consist of three Current differencing transconductance amplifiers (CDTA) and two grounded capacitors, which are resistorless, and they are suitable for monolithic integration. The universal filter uses minimum CDTAs and passive elements to realize SIMO type low-pass (LP), high-pass (HP), band-pass (BP) band-stop (BS) and all-pass (AP) filter functions simultaneously without any component matching conditions. The angular frequency (ω0) and the quality factor (Q) of the proposed filter can be electronically controlled and tuned orthogonal. By some modifications of the filter, a new current-mode four-phase quadrature oscillator (QO) can be obtained easily. The condition of oscillation (CO) and frequency of oscillation (FO) of the QO can be controlled electronically and independently through the bias current of the CDTAs, and it is suitable for variable frequency oscillator. Moreover, all the passive and active sensitivities of the circuits are low. SPICE simulation results are included to confirm the theory.

Keywords: Universal Filter, Quadrature Oscillator, Current mode, Current differencing transconductance amplifiers.

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Authors: Syed Manzoor Qasim, Shuja Abbasi, Saleh Alshebeili, Bandar Almashary, Ateeq Ahmad Khan

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Higher-order Statistics (HOS), also known as cumulants, cross moments and their frequency domain counterparts, known as poly spectra have emerged as a powerful signal processing tool for the synthesis and analysis of signals and systems. Algorithms used for the computation of cross moments are computationally intensive and require high computational speed for real-time applications. For efficiency and high speed, it is often advantageous to realize computation intensive algorithms in hardware. A promising solution that combines high flexibility together with the speed of a traditional hardware is Field Programmable Gate Array (FPGA). In this paper, we present FPGA-based parallel architecture for the computation of third-order cross moments. The proposed design is coded in Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) and functionally verified by implementing it on Xilinx Spartan-3 XC3S2000FG900-4 FPGA. Implementation results are presented and it shows that the proposed design can operate at a maximum frequency of 86.618 MHz.

Keywords: Cross moments, Cumulants, FPGA, Hardware Implementation.

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Authors: B. Marungsri, S. Boonpoke, A. Rawangpai, A. Oonsivilai, C. Kritayakornupong

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This study describes analysis of tower grounding resistance effected the back flashover voltage across insulator string in a transmission system. This paper studies the 500 kV transmission lines from Mae Moh, Lampang to Nong Chok, Bangkok, Thailand, which is double circuit in the same steel tower with two overhead ground wires. The factor of this study includes magnitude of lightning stroke, and front time of lightning stroke. Steel tower uses multistory tower model. The assumption of studies based on the return stroke current ranged 1-200 kA, front time of lightning stroke between 1 μs to 3 μs. The simulations study the effect of varying tower grounding resistance that affect the lightning current. Simulation results are analyzed lightning over voltage that causes back flashover at insulator strings. This study helps to know causes of problems of back flashover the transmission line system, and also be as a guideline solving the problem for 500 kV transmission line systems, as well.

Keywords: Tower grounding resistance, back flashover, multistory tower model, lightning stroke current.

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Authors: Thiang, Handry Khoswanto, Rendy Pangaldus

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Inverse kinematics analysis plays an important role in developing a robot manipulator. But it is not too easy to derive the inverse kinematic equation of a robot manipulator especially robot manipulator which has numerous degree of freedom. This paper describes an application of Artificial Neural Network for modeling the inverse kinematics equation of a robot manipulator. In this case, the robot has three degree of freedoms and the robot was implemented for drilling a printed circuit board. The artificial neural network architecture used for modeling is a multilayer perceptron networks with steepest descent backpropagation training algorithm. The designed artificial neural network has 2 inputs, 2 outputs and varies in number of hidden layer. Experiments were done in variation of number of hidden layer and learning rate. Experimental results show that the best architecture of artificial neural network used for modeling inverse kinematics of is multilayer perceptron with 1 hidden layer and 38 neurons per hidden layer. This network resulted a RMSE value of 0.01474.

Keywords: Artificial neural network, back propagation, inverse kinematics, manipulator, robot.

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Authors: Haridas Kuruveettil, Dongning Zhao, Cheong Jia Hao, Minkyu Je

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We present the design of Analog front end (AFE) low noise pre-amplifier implemented in a high voltage 0.18-µm CMOS technology for  a three dimensional ultrasound  bio microscope (3D UBM) application. The fabricated chip has 4X16 pre-amplifiers implemented to interface   a 2-D array of    high frequency capacitive micro-machined ultrasound transducers (CMUT). Core AFE cell consists of a high-voltage pulser in the transmit path, and a low-noise transimpedance amplifier in the receive path. Proposed system offers a high image resolution by the use of high frequency CMUTs with associated high performance imaging electronics integrated together.  Performance requirements and the design methods of the high bandwidth transimpedance amplifier are described in the paper. A single cell of transimpedance (TIA) amplifier and the bias circuit occupies a silicon area of 250X380 µm² and the full chip occupies a total silicon area of 10x6.8 mm².

Keywords: Ultrasound, analog front end, medical imaging, beam forming, biomicroscope, transimpedance gain.

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Authors: Nesapriya. P., S. Rajalaxmi

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This paper is based on the bridgeless single-phase Ac–Dc Power Factor Correction (PFC) converters with Fuzzy Logic Controller. High frequency isolated Cuk converters are used as a modular dc-dc converter in Discontinuous Conduction Mode (DCM) of operation of Power Factor Correction. The aim of this paper is to simplify the program complexity of the controller by reducing the number of fuzzy sets of the Membership Functions (MFs) and to improve the efficiency and to eliminate the power quality problems. The output of Fuzzy controller is compared with High frequency triangular wave to generate PWM gating signals of Cuk converter. The proposed topologies are designed to work in Discontinuous Conduction Mode (DCM) to achieve a unity power factor and low total harmonic distortion of the input current. The Fuzzy Logic Controller gives additional advantages such as accurate result, uncertainty and imprecision and automatic control circuitry. Performance comparisons between the proposed and conventional controllers and circuits are performed based on circuit simulations.

Keywords: Fuzzy Logic Controller (FLC), Bridgeless rectifier, Cuk converter, Pulse Width Modulation (PWM), Power Factor Correction, Total Harmonic Distortion (THD).

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Authors: A. Yazdanpanah Goharrizi

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An improved topology of a voltage-fed quasi-resonant soft switching LCrCdc series-parallel half bridge inverter with a constant-frequency for electronic ballast applications is proposed in this paper. This new topology introduces a low-cost solution to reduce switching losses and circuit rating to achieve high-efficiency ballast. Switching losses effect on ballast efficiency is discussed through experimental point of view. In this discussion, an improved topology in which accomplishes soft switching operation over a wide power regulation range is proposed. The proposed structure uses reverse recovery diode to provide better operation for the ballast system. A symmetrical pulse wide modulation (PWM) control scheme is implemented to regulate a wide range of out-put power. Simulation results are kindly verified with the experimental measurements obtained by ballast-lamp laboratory prototype. Different load conditions are provided in order to clarify the performance of the proposed converter.

Keywords: Electronic ballast, Pulse wide modulation (PWM) Reverse recovery diode, Soft switching.

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Authors: Zulhisyam Salleh, Fizatul Aini Patakor, Rosilah Wahab, Awangku Khairul Ridzwan Awangku Jaya

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Autism is a lifelong developmental disability that affects how people perceive the world and interact with others. Most of these children have difficulty with fine motor skills which typically struggle with handwriting and fine activities in their routine life such as getting dressed and controlled use of the everyday tool. Because fine motor activities encompass so many routine functions, a fine motor delay can have a measurable negative impact on a person's ability to handle daily practical tasks. This project proposed a simple fine motor exercise aid plus the game (exergame) for autistic children who discover from fine motor difficulties. The proposed exergame will be blinking randomly and user needs to bend their finger accordingly. It will notify the user, whether they bend the right finger or not. The system is realized using Arduino, which is programmed to control all the operated circuit. The feasibility studies with six autistic children were conducted and found the child interested in using exergame and could quickly get used to it. This study provides important guidance for future investigations of the exergame potential for accessing and improving fine motor skill among autistic children.

Keywords: Autism children, Arduino project, fine motor skill, finger exergame.

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Authors: D. Subedi, S. Pradhan

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Current transformers are an integral part of power system because it provides a proportional safe amount of current for protection and measurement applications. However, when the power system experiences an abnormal situation leading to huge current flow, then this huge current is proportionally injected to the protection and metering circuit. Since the protection and metering equipment’s are designed to withstand only certain amount of current with respect to time, these high currents pose a risk to man and equipment. Therefore, during such instances, the CT saturation characteristics have a huge influence on the safety of both man and equipment and on the reliability of the protection and metering system. This paper shows the effect of burden on the Accuracy Limiting factor/ Instrument security factor of current transformers and the change in saturation characteristics of the CT’s. The response of the CT to varying levels of overcurrent at different connected burden will be captured using the data acquisition software LabVIEW. Analysis is done on the real time data gathered using LabVIEW. Variation of current transformer saturation characteristics with changes in burden will be discussed.

Keywords: Accuracy limiting factor, burden, current transformer, instrument security factor, saturation characteristics.

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Authors: Amir Bak Khoshnevis, Mahdieh Khodadadi, Aghil Lotfi

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For a bluff body, roughness elements in simulating a turbulent boundary layer, leading to delayed flow separation, a smaller wake, and lower form drag. In the present work, flow past a circular cylinder with using tripping wires is studied experimentally. The wind tunnel used for modeling free stream is open blow circuit (maximum speed = 30m/s and maximum turbulence of free stream = 0.1%). The selected Reynolds number for all tests was constant (Re = 25000). The circular cylinder selected for this experiment is 20 and 400mm in diameter and length, respectively. The aim of this research is to find the optimal operation mode. In this study installed some tripping wires 1mm in diameter, with a different number of wires on the circular cylinder and the wake characteristics of the circular cylinder is studied. Results showed that by increasing number of tripping wires attached to the circular cylinder (6, 8, and 10, respectively), The optimal angle for the tripping wires with 1mm in diameter to be installed on the cylinder is 60̊ (or 6 wires required at angle difference of 60̊). Strouhal number for the cylinder with tripping wires 1mm in diameter at angular position 60̊ showed the maximum value.

Keywords: Wake of a circular cylinder, trip wire, velocity defect, Strouhal number.

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Authors: T. Vigneswaran, B. Mukundhan, P. Subbarami Reddy

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Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. In addition to its main task, which is adding two numbers, it participates in many other useful operations such as subtraction, multiplication, division,, address calculation,..etc. In most of these systems the adder lies in the critical path that determines the overall speed of the system. So enhancing the performance of the 1-bit full adder cell (the building block of the adder) is a significant goal.Demands for the low power VLSI have been pushing the development of aggressive design methodologies to reduce the power consumption drastically. To meet the growing demand, we propose a new low power adder cell by sacrificing the MOS Transistor count that reduces the serious threshold loss problem, considerably increases the speed and decreases the power when compared to the static energy recovery full (SERF) adder. So a new improved 14T CMOS l-bit full adder cell is presented in this paper. Results show 50% improvement in threshold loss problem, 45% improvement in speed and considerable power consumption over the SERF adder and other different types of adders with comparable performance.

Keywords: Arithmetic circuit, full adder, multiplier, low power, very Large-scale integration (VLSI).

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Authors: Moorthi S., Meganathan D., Janarthanan D., Praveen Kumar P., J. Raja paul perinbam

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An efficient architecture for low jitter All Digital Phase Locked Loop (ADPLL) suitable for high speed SoC applications is presented in this paper. The ADPLL is designed using standard cells and described by Hardware Description Language (HDL). The ADPLL implemented in a 90 nm CMOS process can operate from 10 to 200 MHz and achieve worst case frequency acquisition in 14 reference clock cycles. The simulation result shows that PLL has cycle to cycle jitter of 164 ps and period jitter of 100 ps at 100MHz. Since the digitally controlled oscillator (DCO) can achieve both high resolution and wide frequency range, it can meet the demands of system-level integration. The proposed ADPLL can easily be ported to different processes in a short time. Thus, it can reduce the design time and design complexity of the ADPLL, making it very suitable for System-on-Chip (SoC) applications.

Keywords: All Digital Phase Locked Loop (ADPLL), Systemon-Chip (SoC), Phase Locked Loop (PLL), Very High speedIntegrated Circuit (VHSIC) Hardware Description Language(VHDL), Digitally Controlled Oscillator (DCO), Phase frequencydetector (PFD) and Voltage Controlled Oscillator (VCO).

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Authors: Noor H Jabarullah

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In the past many uneconomic solutions for limitation and interruption of short-circuit currents in low power applications have been introduced, especially polymer switch based on the positive temperature coefficient of resistance (PCTR) concept. However there are many limitations in the active material, which consists of conductive fillers. This paper presents a significantly improved and simplified approach that replaces the existing current limiters with faster switching elements. Its elegance lies in the remarkable simplicity and low-cost processes of producing the device using polyaniline (PANI) doped with methane-sulfonic acid (MSA). Samples characterized as lying in the metallic and critical regimes of metal insulator transition have been studied by means of electrical performance in the voltage range from 1V to 5 V under different environmental conditions. Moisture presence is shown to increase the resistivity and also improved its current limiting performance. Additionally, the device has also been studied for electrical resistivity in the temperature range 77 K-300 K. The temperature dependence of the electrical conductivity gives evidence for a transport mechanism based on variable range hopping in three dimensions.

Keywords: Conducting polymer, current limiter, intrinsic, moisture dependence, polyaniline, resettable, surge protection.

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Authors: Megha Rao, Søren H. Jensen, Xiufu Sun, Anke Hagen, Mogens B. Mogensen

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Solid oxide electrolysis cells have an immense potential in converting CO₂ and H₂O into syngas during co-electrolysis operation. The produced syngas can be further converted into hydrocarbons. This kind of technology is called power-to-gas or power-to-liquid. To produce hydrocarbons via this route, durability of the cells is still a challenge, which needs to be further investigated in order to improve the cells. In this work, various nickel-yttria stabilized zirconia (Ni-YSZ) fuel electrode supported or YSZ electrolyte supported cells, cerium gadolinium oxide (CGO) barrier layer, and an oxygen electrode are investigated for durability under co-electrolysis conditions in both galvanostatic and potentiostatic conditions. While changing the gas on the oxygen electrode, keeping the fuel electrode gas composition constant, a change in the gas concentration arc was observed by impedance spectroscopy. Measurements of open circuit potential revealed the presence of leaks in the setup. It is speculated that the change in concentration impedance may be related to the leaks. Furthermore, the cells were also tested under pressurized conditions to find an inter-play between the leak rate and the pressure. A mathematical modeling together with electrochemical and microscopy analysis is presented.

Keywords: Co-electrolysis, solid oxide electrolysis cells, leaks, durability, gas concentration.

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Authors: Hanifah Jambari, Naziha A. Azli, M. Afendi M. Piah

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This paper presents the generation of bipolar square wave pulses with characteristics that are suitable for liquid food sterilization using a Cascaded H-bridge Multilevel Inverter (CHMI). Bipolar square waves pulses have been reported as stable for a longer time during the sterilization process with minimum heat emission and increased efficiency. The CHMI allows the system to produce bipolar square wave pulses and yielding high output voltage without using a transformer while fulfilling the pulse requirements for effective liquid food sterilization. This in turn can reduce power consumption and cost of the overall liquid food sterilization system. The simulation results have shown that pulses with peak output voltage of 2.4 kV, pulse width of between 1 2s and 1 ms at frequencies of 50 Hz and 100 Hz can be generated by a 7-level CHMI. Results from the experimental set-up based on a 5-level CHMI has indicated the potential of the proposed circuit in producing bipolar square wave output pulses with peak values that depends on the DC source level supplied to the CHMI modules, pulse width of between 12.5 2s and 1 ms at frequencies of 50 Hz and 100 Hz.

Keywords: pulsed electric field, multilevel inverter, bipolarsquare wave, food sterilization

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Authors: Suresh Alapati, Sreehari Rao Patri, K. S. R. Krishna Prasad

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Anultra-low power capacitor less low-dropout voltage regulator with improved transient response using gain enhanced feed forward path compensation is presented in this paper. It is based on a cascade of a voltage amplifier and a transconductor stage in the feed forward path with regular error amplifier to form a composite gainenhanced feed forward stage. It broadens the gain bandwidth and thus improves the transient response without substantial increase in power consumption. The proposed LDO, designed for a maximum output current of 100 mA in UMC 180 nm, requires a quiescent current of 69 )A. An undershot of 153.79mV for a load current changes from 0mA to 100mA and an overshoot of 196.24mV for current change of 100mA to 0mA. The settling time is approximately 1.1 )s for the output voltage undershooting case. The load regulation is of 2.77 )V/mA at load current of 100mA. Reference voltage is generated by using an accurate band gap reference circuit of 0.8V.The costly features of SOC such as total chip area and power consumption is drastically reduced by the use of only a total compensation capacitance of 6pF while consuming power consumption of 0.096 mW.

Keywords: Capacitor-less LDO, frequency compensation, Transient response, latch, self-biased differential amplifier.

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Authors: Harshavardhan Reddy, Balaji Subramanian

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A systematic parametric study to find the optimum Bellmouth profile by relating geometric and performance parameters to satisfy a set of specifications is reported. A careful aerodynamic design of Bellmouth intake is critical to properly direct the flow with minimal losses and maximal flow uniformity into the honeycomb located inside the settling chamber of an indraft wind tunnel, thus improving the efficiency of the entire unit. Design charts for elliptically profiled Bellmouth's with two different contraction ratios (9 and 18) and three different test section speeds (25 m/s, 50 m/s, and 75 m/s) were presented. A significant performance improvement - especially in the coefficient of discharge and in the flow angularity and boundary layer thickness at the honeycomb inlet - was observed when an entry corner radius (r/D = 0.08) was added to the Bellmouth profile. The nonuniformity at the honeycomb inlet drops by about three times (~1% to 0.3%) when moving from square to regular octagonal cross-section. An octagonal cross-sectioned Bellmouth intake with L/d = 0.55, D/d = 1.625, and r/D = 0.08 met all the four target performance specifications and is proposed as the best choice for a low-speed wind tunnel.

Keywords: Bellmouth intake, low-speed wind tunnel, coefficient of discharge, nonuniformity, flow angularity, boundary layer thickness, CFD, aerodynamics.

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Authors: V.Sekar, T.G.Palanivelu, B.Revathi

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Electromagnetic interference (EMI) is one of the serious problems in most electrical and electronic appliances including fluorescent lamps. The electronic ballast used to regulate the power flow through the lamp is the major cause for EMI. The interference is because of the high frequency switching operation of the ballast. Formerly, some EMI mitigation techniques were in practice, but they were not satisfactory because of the hardware complexity in the circuit design, increased parasitic components and power consumption and so on. The majority of the researchers have their spotlight only on EMI mitigation without considering the other constraints such as cost, effective operation of the equipment etc. In this paper, we propose a technique for EMI mitigation in fluorescent lamps by integrating Frequency Modulation and Evolutionary Programming. By the Frequency Modulation technique, the switching at a single central frequency is extended to a range of frequencies, and so, the power is distributed throughout the range of frequencies leading to EMI mitigation. But in order to meet the operating frequency of the ballast and the operating power of the fluorescent lamps, an optimal modulation index is necessary for Frequency Modulation. The optimal modulation index is determined using Evolutionary Programming. Thereby, the proposed technique mitigates the EMI to a satisfactory level without disturbing the operation of the fluorescent lamp.

Keywords: Ballast, Electromagnetic interference (EMI), EMImitigation, Evolutionary programming (EP), Fluorescent lamp, Frequency Modulation (FM), Modulation index.

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Authors: Syed Iftekhar Ali, M. S. Islam

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In this paper we present an energy efficient match-line (ML) sensing scheme for high-speed ternary content-addressable memory (TCAM). The proposed scheme isolates the sensing unit of the sense amplifier from the large and variable ML capacitance. It employs feedback in the sense amplifier to successfully detect a match while keeping the ML voltage swing low. This reduced voltage swing results in large energy saving. Simulation performed using 130nm 1.2V CMOS logic shows at least 30% total energy saving in our scheme compared to popular current race (CR) scheme for similar search speed. In terms of speed, dynamic energy, peak power consumption and transistor count our scheme also shows better performance than mismatch-dependant (MD) power allocation technique which also employs feedback in the sense amplifier. Additionally, the implementation of our scheme is simpler than CR or MD scheme because of absence of analog control voltage and programmable delay circuit as have been used in those schemes.

Keywords: content-addressable memory, energy consumption, feedback, peak power, sensing scheme, sense amplifier, ternary.

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Authors: Muammer Kaya

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The main purpose of this article is to provide a comprehensive review of various physical and chemical processes for electronic waste (e-waste) recycling, their advantages and shortfalls towards achieving a cleaner process of waste utilization, with especial attention towards extraction of metallic values. Current status and future perspectives of waste printed circuit boards (PCBs) recycling are described. E-waste characterization, dismantling/ disassembly methods, liberation and classification processes, composition determination techniques are covered. Manual selective dismantling and metal-nonmetal liberation at – 150 µm at two step crushing are found to be the best. After size reduction, mainly physical separation/concentration processes employing gravity, electrostatic, magnetic separators, froth floatation etc., which are commonly used in mineral processing, have been critically reviewed here for separation of metals and non-metals, along with useful utilizations of the non-metallic materials. The recovery of metals from e-waste material after physical separation through pyrometallurgical, hydrometallurgical or biohydrometallurgical routes is also discussed along with purification and refining and some suitable flowsheets are also given. It seems that hydrometallurgical route will be a key player in the base and precious metals recoveries from e-waste. E-waste recycling will be a very important sector in the near future from economic and environmental perspectives.

Keywords: E-waste, WEEE, PCB, recycling, metal recovery, hydrometallurgy, pyrometallurgy, biohydrometallurgy.

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Authors: Chia-Chen Wei, Pack Hsieh, Jeffrey Chen

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Surface Mount Technology (SMT) is widely used in the area of the electronic assembly in which the electronic components are mounted to the surface of the printed circuit board (PCB). Most of the defects in the SMT process are mainly related to the quality of solder paste printing. These defects lead to considerable manufacturing costs in the electronics assembly industry. Therefore, the solder paste inspection (SPI) machine for controlling and monitoring the amount of solder paste printing has become an important part of the production process. So far, the setting of the SPI threshold is based on statistical analysis and experts’ experiences to determine the appropriate threshold settings. Because the production data are not normal distribution and there are various variations in the production processes, defects related to solder paste printing still occur. In order to solve this problem, this paper proposes an online machine learning algorithm, called the automatic threshold adjustment (ATA) algorithm, and closed-loop architecture in the SMT process to determine the best threshold settings. Simulation experiments prove that our proposed threshold settings improve the accuracy from 99.85% to 100%.

Keywords: Big data analytics, Industry 4.0, SPI threshold setting, surface mount technology.

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Authors: M. Geetha Priya, K. Baskaran, S. Srinivasan

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Digital systems are said to be constructed using basic logic gates. These gates are the NOR, NAND, AND, OR, EXOR & EXNOR gates. This paper presents a robust three transistors (3T) based NAND and NOR gates with precise output logic levels, yet maintaining equivalent performance than the existing logic structures. This new set of 3T logic gates are based on CMOS inverter and Pass Transistor Logic (PTL). The new universal logic gates are characterized by better speed and lower power dissipation which can be straightforwardly fabricated as memory ICs for high performance computer networks. The simulation tests were performed using standard BPTM 22nm process technology using SYNOPSYS HSPICE. The 3T NAND gate is evaluated using C17 benchmark circuit and 3T NOR is gate evaluated using a D-Latch. According to HSPICE simulation in 22 nm CMOS BPTM process technology under given conditions and at room temperature, the proposed 3T gates shows an improvement of 88% less power consumption on an average over conventional CMOS logic gates. The devices designed with 3T gates will make longer battery life by ensuring extremely low power consumption.

Keywords: Low power, CMOS, pass-transistor, flash memory, logic gates.

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Authors: Ali M. Eltamaly, A. I. Alolah, R. Hamouda, M. Y. Abdulghany

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In this paper a novel, simple and reliable digital firing scheme has been implemented for speed control of three-phase induction motor using ac voltage controller. The system consists of three-phase supply connected to the three-phase induction motor via three triacs and its control circuit. The ac voltage controller has three modes of operation depending on the shape of supply current. The performance of the induction motor differs in each mode where the speed is directly proportional with firing angle in two modes and inversely in the third one. So, the control system has to detect the current mode of operation to choose the correct firing angle of triacs. Three sensors are used to feed the line currents to control system to detect the mode of operation. The control strategy is implemented using a low cost Xilinx Spartan-3E field programmable gate array (FPGA) device. Three PI-controllers are designed on FPGA to control the system in the three-modes. Simulation of the system is carried out using PSIM computer program. The simulation results show stable operation for different loading conditions especially in mode 2/3. The simulation results have been compared with the experimental results from laboratory prototype.

Keywords: FPGA, Induction motor, PSIM, triac, Voltage controller.

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Authors: Mandlenkosi George Robert Mahlobo, Peter Apata Olubambi, Philippe Refait

Abstract:

The aim of this study was to use voltammetry as a method to understand the behavior of steel in unsaturated soil in the presence of cathodic protection (CP). Three carbon steel coupons were buried in artificial soil wetted at 65-70% of saturation for 37 days. All three coupons were left at open circuit potential (OCP) for the first seven days in the unsaturated soil before CP which was only applied on two of the three coupons at the protection potential -0.8 V vs. Cu/CuSO4 for the remaining 30 days of the experiment. Voltammetry was performed weekly on the coupon without CP while electrochemical impedance spectroscopy (EIS) was performed daily to monitor and correct the applied CP potential from ohmic drop. Voltammetry was finally performed the last day on the coupons under CP. All the voltammograms were modeled with mathematical equations in order to compute the electrochemical parameters and subsequently deduce the corrosion rate of the steel coupons. For the coupon without CP, the corrosion rate was determined at 300 µm/y. For the coupons under CP, the residual corrosion rate under CP was estimated at 12 µm/y while the corrosion rate of the coupons, after interruption of CP, was estimated at 25 µm/y. This showed that CP was efficient due to two effects: a direct effect, from the decreased potential, and an induced effect, associated with the increased interfacial pH that promoted the formation of a protective layer on the steel surface.

Keywords: Carbon steel, cathodic protection, voltammetry, unsaturated soil, Raman spectroscopy.

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Authors: M. Boulakroune, M. Challal, H. Louazene, S. Fentiz

Abstract:

This paper presents two types of microstrip bandpass filter (BPF) at microwave frequencies. The first one is a tunable BPF using planar patch resonators based on a varactor diode. The filter is formed by a triple mode circular patch resonator with two pairs of slots, in which the varactor diodes are connected. Indeed, this filter is initially centered at 2.4 GHz; the center frequency of the tunable patch filter could be tuned up to 1.8 GHz simultaneously with the bandwidth, reaching high tuning ranges. Lossless simulations were compared to those considering the substrate dielectric, conductor losses and the equivalent electrical circuit model of the tuning element in order to assess their effects. Within these variations, simulation results showed insertion loss better than 2 dB and return loss better than 10 dB over the passband. The second structure is a BPF for ultra-wideband (UWB) applications based on multiple-mode resonator (MMR) and rectangular-shaped defected ground structure (DGS). This filter, which is compact size of 25.2 x 3.8 mm2, provides in the pass band an insertion loss of 0.57 dB and a return loss greater than 12 dB. The proposed filters presents good performances and the simulation results are in satisfactory agreement with the experimentation ones reported elsewhere.

Keywords: Defected ground structure, varactor diode, microstrip bandpass filter, multiple-mode resonator.

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Authors: Abderrahmane El Kachani, El Mahjoub Chakir, Anass Ait Laachir, Abdelhamid Niaaniaa, Jamal Zerouaoui, Tarik Jarou

Abstract:

This paper presents a wind turbine based on the doubly fed induction generator (DFIG) connected to the utility grid through a shunt active power filter (SAPF). The whole system is controlled by a double nonlinear predictive controller (DNPC). A Taylor series expansion is used to predict the outputs of the system. The control law is calculated by optimization of the cost function. The first nonlinear predictive controller (NPC) is designed to ensure the high performance tracking of the rotor speed and regulate the rotor current of the DFIG, while the second one is designed to control the SAPF in order to compensate the harmonic produces by the three-phase diode bridge supplied by a passive circuit (rd, Ld). As a result, we obtain sinusoidal waveforms of the stator voltage and stator current. The proposed nonlinear predictive controllers (NPCs) are validated via simulation on a 1.5 MW DFIG-based wind turbine connected to an SAPF. The results obtained appear to be satisfactory and promising.

Keywords: Wind power, doubly fed induction generator, shunt active power filter, double nonlinear predictive controller.

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Authors: P. Asadee

Abstract:

Multiplication algorithms have considerable effect on processors performance. A new high-speed, low-power multiplication algorithm has been presented using modified Dadda tree structure. Three important modifications have been implemented in inner product generation step, inner product reduction step and final addition step. Optimized algorithms have to be used into basic computation components, such as multiplication algorithms. In this paper, we proposed a new algorithm to reduce power, delay, and transistor count of a multiplication algorithm implemented using low power modified counter. This work presents a novel design for Dadda multiplication algorithms. The proposed multiplication algorithm includes structured parts, which have important effect on inner product reduction tree. In this paper, a 1.3V, 64-bit carry hybrid adder is presented for fast, low voltage applications. The new 64-bit adder uses a new circuit to implement the proposed carry hybrid adder. The new adder using 80 nm CMOS technology has been implemented on 700 MHz clock frequency. The proposed multiplication algorithm has achieved 14 percent improvement in transistor count, 13 percent reduction in delay and 12 percent modification in power consumption in compared with conventional designs.

Keywords: adder, CMOS, counter, Dadda tree, encoder.

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