Search results for: interconnect modeling

Authors: Shilpi Lavania

Abstract:

As the frequency of operation has attained a range of GHz and signal rise time continues to increase interconnect technology is suffering due to various high frequency effects as well as ground bounce problem. In some recent studies a high frequency effect i.e. skin effect has been modeled and its drawbacks have been discussed. This paper strives to make an impression on the advantage side of modeling skin effect for interconnect line. The proposed method has considered a CMOS with RC interconnect. Delay and noise considering ground bounce problem and with skin effect are discussed. The simulation results reveal an advantage of considering skin effect for minimization of ground bounce problem during the working of the model. Noise and delay variations with temperature are also presented.

Keywords: Interconnect, Skin effect, Ground Bounce, Delay, Noise.

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Authors: Kureshi Abdul Kadir, Mohd. Hasan

Abstract:

Each new semiconductor technology node brings smaller transistors and wires. Although this makes transistors faster, wires get slower. In nano-scale regime, the standard copper (Cu) interconnect will become a major hurdle for FPGA interconnect due to their high resistivity and electromigration. This paper presents the comprehensive evaluation of mixed CNT bundle interconnects and investigates their prospects as energy efficient and high speed interconnect for future FPGA routing architecture. All HSPICE simulations are carried out at operating frequency of 1GHz and it is found that mixed CNT bundle implemented in FPGAs as interconnect can potentially provide a substantial delay and energy reduction over traditional interconnects at 32nm process technology.

Keywords: CMOS, Copper Interconnect, Mixed CNT Bundle Interconnect, FPGAs.

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Authors: Guang Sun, Yong Li, Yuanyuan Zhang, Shijun Lin, Li Su, Depeng Jin, Lieguang zeng

Abstract:

Network on Chip (NoC) has emerged as a promising on chip communication infrastructure. Three Dimensional Integrate Circuit (3D IC) provides small interconnection length between layers and the interconnect scalability in the third dimension, which can further improve the performance of NoC. Therefore, in this paper, a hierarchical cluster-based interconnect architecture is merged with the 3D IC. This interconnect architecture significantly reduces the number of long wires. Since this architecture only has approximately a quarter of routers in 3D mesh-based architecture, the average number of hops is smaller, which leads to lower latency and higher throughput. Moreover, smaller number of routers decreases the area overhead. Meanwhile, some dual links are inserted into the bottlenecks of communication to improve the performance of NoC. Simulation results demonstrate our theoretical analysis and show the advantages of our proposed architecture in latency, throughput and area, when compared with 3D mesh-based architecture.

Keywords: Network on Chip (NoC), interconnect architecture, performance, area, Three Dimensional Integrate Circuit (3D IC).

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Authors: Jong-Bae Lee, Seongsoo Lee

Abstract:

Local interconnect network (LIN) is a communication protocol that combines sensors, actuators, and processors to a functional module in automotive applications. In this paper, a LIN ver. 2.2A controller was designed in Verilog hardware description language (Verilog HDL) and implemented in field-programmable gate array (FPGA). Its operation was verified by making full-scale LIN network with the presented FPGA-implemented LIN controller, commercial LIN transceivers, and commercial processors. When described in Verilog HDL and synthesized in 0.18 μm technology, its gate size was about 2,300 gates.

Keywords: Local interconnect network, controller, transceiver, processor.

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Authors: G.Ramana Murthy, C.Senthilpari, P.Velrajkumar, Lim Tien Sze

Abstract:

The proposed multiplexer-based novel 1-bit full adder cell is schematized by using DSCH2 and its layout is generated by using microwind VLSI CAD tool. The adder cell layout interconnect analysis is performed by using BSIM4 layout analyzer. The adder circuit is compared with other six existing adder circuits for parametric analysis. The proposed adder cell gives better performance than the other existing six adder circuits in terms of power, propagation delay and PDP. The proposed adder circuit is further analyzed for interconnect analysis, which gives better performance than other adder circuits in terms of layout thickness, width and height.

Keywords: Full Adder, Interconnect Analysis, Low-Power, Multiplexer, Propagation Delay, Parametric Analysis.

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Authors: Kollarama Subramanyam, Nisha Kuruvilla, J. P. Raina

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Novel compact expressions for propagation constant (γ) of SWCNT and bundled SWCNTs interconnect, in terms of physical parameters such as length, operating frequency and diameter of CNTs is proposed in this work. These simplified expressions enable physical insight and accurate estimation of signal attenuation level and its phase change at any length for a particular frequency. The proposed expressions are validated against SPICE simulated results of lumped as well as distributed equivalent electrical RLC nets of CNT interconnect. These expressions also help us to evaluate the cut off frequencies of SWCNTs for different interconnect lengths.

Keywords: Attenuation constant, Bundled SWCNT, CNT interconnects, Propagation Constant.

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Authors: Susmita Sahoo, Madhumanti Datta, Rajib Kar

Abstract:

Fast delay estimation methods, as opposed to simulation techniques, are needed for incremental performance driven layout synthesis. On-chip inductive effects are becoming predominant in deep submicron interconnects due to increasing clock speed and circuit complexity. Inductance causes noise in signal waveforms, which can adversely affect the performance of the circuit and signal integrity. Several approaches have been put forward which consider the inductance for on-chip interconnect modelling. But for even much higher frequency, of the order of few GHz, the shunt dielectric lossy component has become comparable to that of other electrical parameters for high speed VLSI design. In order to cope up with this effect, on-chip interconnect has to be modelled as distributed RLCG line. Elmore delay based methods, although efficient, cannot accurately estimate the delay for RLCG interconnect line. In this paper, an accurate analytical delay model has been derived, based on first and second moments of RLCG interconnection lines. The proposed model considers both the effect of inductance and conductance matrices. We have performed the simulation in 0.18μm technology node and an error of as low as less as 5% has been achieved with the proposed model when compared to SPICE. The importance of the conductance matrices in interconnect modelling has also been discussed and it is shown that if G is neglected for interconnect line modelling, then it will result an delay error of as high as 6% when compared to SPICE.

Keywords: Delay Modelling; On-Chip Interconnect; RLCGInterconnect; Ramp Input; Damping; VLSI

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Authors: Sunil Jadav, Rajeevan Chandel Munish Vashishath

Abstract:

Today’s VLSI networks demands for high speed. And in this work the compact form mathematical model for current mode signalling in VLSI interconnects is presented.RLC interconnect line is modelled using characteristic impedance of transmission line and inductive effect. The on-chip inductance effect is dominant at lower technology node is emulated into an equivalent resistance. First order transfer function is designed using finite difference equation, Laplace transform and by applying the boundary conditions at the source and load termination. It has been observed that the dominant pole determines system response and delay in the proposed model. The novel proposed current mode model shows superior performance as compared to voltage mode signalling. Analysis shows that current mode signalling in VLSI interconnects provides 2.8 times better delay performance than voltage mode. Secondly the damping factor of a lumped RLC circuit is shown to be a useful figure of merit.

Keywords: Current Mode, Voltage Mode, VLSI Interconnect.

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Authors: Susmita Sahoo, Madhumanti Datta, Rajib Kar

Abstract:

This work proposes an accurate crosstalk noise estimation method in the presence of multiple RLC lines for the use in design automation tools. This method correctly models the loading effects of non switching aggressors and aggressor tree branches using resistive shielding effect and realistic exponential input waveforms. Noise peak and width expressions have been derived. The results obtained are at good agreement with SPICE results. Results show that average error for noise peak is 4.7% and for the width is 6.15% while allowing a very fast analysis.

Keywords: Crosstalk, distributed RLC segments, On-Chip interconnect, output response, VLSI, noise peak, noise width.

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Authors: M. İskefiyeli, İ. Özçelik

Abstract:

PROFIBUS (PROcess FIeld BUS) which is defined with international standarts (IEC61158, EN50170) is the most popular fieldbus, and provides a communication between industrial applications which are located in different control environment and location in manufacturing, process and building automation. Its communication speed is from 9.6 Kbps to 12 Mbps over distances from 100 to 1200 meters, and so it is to be often necessary to interconnect them in order to break these limits. Unfortunately this interconnection raises several issues and the solutions found so far are not very satisfactory. In this paper, we propose a new solution to interconnect PROFIBUS segments, which uses a wireless MAN based on the IEEE 802.16 standard as a backbone system. Also, the solution which is described a model for internetworking unit integrates the traffic generated by PROFIBUS segments into IEEE 802.16 wireless MAN using encapsulation technique.

Keywords: Internetworking Unit, PROFIBUS, WiMAX, WMAN, 802.16.

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Authors: Ki-Young Kim, Jae-Ho Lim, Deok-Min Kim, Seok-Yoon Kim

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Average current analysis checking the impact of current flow is very important to guarantee the reliability of semiconductor systems. As semiconductor process technologies improve, the coupling capacitance often become bigger than self capacitances. In this paper, we propose an analytic technique for analyzing average current on interconnects in multi-conductor structures. The proposed technique has shown to yield the acceptable errors compared to HSPICE results while providing computational efficiency.

Keywords: current moment, interconnect modeling, reliability analysis, worst-case switching

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Authors: Bhaskar M., Venkataramani B.

Abstract:

In the literature, surfing technique has been proposed for single ended wave-pipelined serial interconnects to increase the data transfer rate. In this paper a novel surfing technique is proposed for differential wave-pipelined serial interconnects, which uses a 'Controllable inverter pair' for surfing. To evaluate the efficiency of this technique, a transceiver with transmitter, receiver, delay locked loop (DLL) along with 40mm metal 4 interconnects using the proposed surfing technique is implemented in UMC 180nm technology and their performances are studied through post layout simulations. From the study, it is observed that the proposed scheme permits 1.875 times higher data transmission rate compared to the single ended scheme whose maximum data transfer rate is 1.33 GB/s. The proposed scheme has the ability to receive the correct data even with stuck-at-faults in the complementary line.

Keywords: Controllable inverter pair, differential interconnect, serial link, surfing, wave pipelining.

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Authors: M. B. Limooei, Hadi Ebrahimifar, Sh. Hosseini

Abstract:

Protective coatings that resist oxide scale growth and decrease chromium evaporation are necessary to make stainless steel interconnect materials for long-term durable operation of solid oxide fuel cells (SOFCs). In this study a layer of cobalt was electroplated on the surface of AISI 441 ferritic stainless steel which is used in solid oxide fuel cells for interconnect applications. The oxidation behavior of coated substrates was studied as a function of time at operating conditions of SOFCs. Cyclic oxidation has been also tested at 800ºC for 100 cycles. Cobalt coating during isothermal oxidation caused to the oxide growth resistance by limiting the outward diffusion of Cr cation and the inward diffusion of oxygen anion. Results of cyclic oxidation exhibited that coated substrates demonstrate an excellent resistance against the spallation and cracking.

Keywords: Oxidation resistance, full cell, Cobalt coating, ferritic stainless steel.

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Authors: S. N. Hosseini, M. H. Enayati, F. Karimzadeh, N. M. Sammes

Abstract:

The synthesis of CuFe2O4 spinel powders by an optimized combustion-like process followed by calcination is described herein. The samples were characterized using X-ray diffraction (XRD), differential thermal analysis (TG/DTA), scanning electron microscopy (SEM), dilatometry and 4-probe DC methods. Different glycine to nitrate (G/N) ratios of 1 (fuel-deficient), 1.48 (stoichiometric) and 2 (fuel-rich) were employed. Calcining the asprepared powders at 800 and 1000°C for 5 hours showed that the G/N ratio of 2 results in the formation of the desired copper spinel single phase at both calcination temperatures. For G/N=1, formation of CuFe2O4 takes place in three steps. First, iron and copper nitrates decompose to iron oxide and pure copper. Then, copper transforms to copper oxide and finally, copper and iron oxides react with each other to form a copper ferrite spinel phase. The electrical conductivity and the coefficient of thermal expansion of the sintered pelletized samples were 2 S.cm-1 (800°C) and 11×10-6 °C-1 (25-800°C), respectively.

Keywords: SOFC interconnect coatings, Copper ferrite, Spinels, Electrical conductivity, Glycine–nitrate process.

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Authors: Chil-Chyuan Kuo, Chen-Hsuan Tsai

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This study presents a cost-effective approach for rapid fabricating modeling platforms utilized in fused deposition modeling system. A small-batch production of modeling platforms about 20 pieces can be obtained economically through silicone rubber mold using vacuum casting without applying the plastic injection molding. The air venting systems is crucial for fabricating modeling platform using vacuum casting. Modeling platforms fabricated can be used for building rapid prototyping model after sandblasting. This study offers industrial value because it has both time-effectiveness and cost-effectiveness.

Keywords: Vacuum casting, fused deposition modeling, modeling platform, sandblasting, surface roughness.

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Authors: Pradip Peter Dey, Bhaskar Raj Sinha, Mohammad Amin, Hassan Badkoobehi

Abstract:

Mathematical, graphical and intuitive models are often constructed in the development process of computational systems. The Unified Modeling Language (UML) is one of the most popular modeling languages used by practicing software engineers. This paper critically examines UML models and suggests an augmented use case view with the addition of new constructs for modeling software. It also shows how a use case diagram can be enhanced. The improved modeling constructs are presented with examples for clarifying important design and implementation issues.

Keywords: Software architecture, software design, Unified Modeling Language (UML), user interface.

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Authors: Huaiyu Zhang

Abstract:

The method of modeling is the key technology for digital mockup (DMU). Based upon the developing for mechanical product DMU, the theory, method and approach for virtual environment (VE) and virtual object (VO) were studied. This paper has expounded the design goal and architecture of DMU system, analyzed the method of DMU application, and researched the general process of physics modeling and behavior modeling.

Keywords: DMU, VR, virtual environment, virtual object, physics modeling, behavior modeling

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Authors: Omer Mahmood, Selvakennedy Selvadurai

Abstract:

“Web of Trust" is one of the recognized goals for Web 2.0. It aims to make it possible for the people to take responsibility for what they publish on the web, including organizations, businesses and individual users. These objectives, among others, drive most of the technologies and protocols recently standardized by the governing bodies. One of the great advantages of Web infrastructure is decentralization of publication. The primary motivation behind Web 2.0 is to assist the people to add contents for Collective Intelligence (CI) while providing mechanisms to link content with people for evaluations and accountability of information. Such structure of contents will interconnect users and contents so that users can use contents to find participants and vice versa. This paper proposes conceptual information storage and linking model, based on decentralized information structure, that links contents and people together. The model uses FOAF, Atom, RDF and RDFS and can be used as a blueprint to develop Web 2.0 applications for any e-domain. However, primary target for this paper is online trust evaluation domain. The proposed model targets to assist the individuals to establish “Web of Trust" in online trust domain.

Keywords: Web of Trust, Semantic Web, Electronic SocialNetworks, Information Management

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Authors: Katalina Grigorova, Kaloyan Mironov

Abstract:

The paper focuses on the benefits of business process modeling. Although this discipline is developing for many years, there is still necessity of creating new opportunities to meet the ever increasing users’ needs. Because one of these needs is related to the conversion of business process models from one standard to another, the authors have developed a converter between BPMN and EPC standards using workflow patterns as intermediate tool. Nowadays there are too many systems for business process modeling. The variety of output formats is almost the same as the systems themselves. This diversity additionally hampers the conversion of the models. The presented study is aimed at discussing problems due to differences in the output formats of various modeling environments.

Keywords: Business process modeling, business process modeling standards, workflow patterns, converting models.

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Authors: Ziaddin Daie Koozekanani, Mina Zolfy Lighvan

Abstract:

One of the most challengeable issues in ESL (Electronic System Level) design is the lack of a general modeling scheme for on chip communication architecture. In this paper some of the mostly used methodologies for modeling and representation of on chip communication are investigated. Our goal is studying the existing methods to extract the requirements of a general representation scheme for communication architecture synthesis. The next step, will be introducing a modeling and representation method for being used in automatically synthesis process of on chip communication architecture.

Keywords: Communication architecture, System on Chip, Communication Modeling and Representation

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Authors: Charles D. Otine, Samuel B. Kucel, Lena Trojer

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Selecting the data modeling technique for an information system is determined by the objective of the resultant data model. Dimensional modeling is the preferred modeling technique for data destined for data warehouses and data mining, presenting data models that ease analysis and queries which are in contrast with entity relationship modeling. The establishment of data warehouses as components of information system landscapes in many organizations has subsequently led to the development of dimensional modeling. This has been significantly more developed and reported for the commercial database management systems as compared to the open sources thereby making it less affordable for those in resource constrained settings. This paper presents dimensional modeling of HIV patient information using open source modeling tools. It aims to take advantage of the fact that the most affected regions by the HIV virus are also heavily resource constrained (sub-Saharan Africa) whereas having large quantities of HIV data. Two HIV data source systems were studied to identify appropriate dimensions and facts these were then modeled using two open source dimensional modeling tools. Use of open source would reduce the software costs for dimensional modeling and in turn make data warehousing and data mining more feasible even for those in resource constrained settings but with data available.

Keywords: About Database, Data Mining, Data warehouse, Dimensional Modeling, Open Source.

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Authors: Adla Bentellis, Zizette Boufaïda

Abstract:

Nowadays, the pace of business change is such that, increasingly, new functionality has to be realized and reliably installed in a matter of days, or even hours. Consequently, more and more business processes are prone to a continuous change. The objective of the research in progress is to use the MAP model, in a conceptual modeling method for flexible and adaptive business process. This method can be used to capture the flexibility dimensions of a business process; it takes inspiration from modularity concept in the object oriented paradigm to establish a hierarchical construction of the BP modeling. Its intent is to provide a flexible modeling that allows companies to quickly adapt their business processes.

Keywords: Business Process, Business process modeling, flexibility, MAP Model.

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Authors: Seong-Su Jeon, Seong-Jin Kim, Goon-Cherl Park

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In this study, direct numerical simulation for the bubble condensation in the subcooled boiling flow was performed. The main goal was to develop the CFD modeling for the bubble condensation and to evaluate the accuracy of the VOF model with the developed CFD modeling. CFD modeling for the bubble condensation was developed by modeling the source terms in the governing equations of VOF model using UDF. In the modeling, the amount of condensation was determined using the interfacial heat transfer coefficient obtained from the bubble velocity, liquid temperature and bubble diameter every time step. To evaluate the VOF model using the CFD modeling for the bubble condensation, CFD simulation results were compared with SNU experimental results such as bubble volume and shape, interfacial area, bubble diameter and bubble velocity. Simulation results predicted well the behavior of the actual condensing bubble. Therefore, it can be concluded that the VOF model using the CFD modeling for the bubble condensation will be a useful computational fluid dynamics tool for analyzing the behavior of the condensing bubble in a wide range of the subcooled boiling flow.

Keywords: Bubble condensation, CFD modeling, Subcooled boiling flow, VOF model.

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Authors: Song Meng, Dianfu Ma, Yongwang Zhao, Jianxin Li

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Cooperative visual modeling is more and more necessary in our complicated world. A collaborative environment which supports interactive operation and communication is required to increase work efficiency. We present a collaborative visual modeling framework which collaborative platform could be built on. On this platform, cooperation and communication is available for designers from different regions. This framework, which is different from other collaborative frameworks, contains a uniform message format, a message handling mechanism and other functions such as message pretreatment and Role-Communication-Token Access Control (RCTAC). We also show our implementation of this framework called Orchestra Designer, which support BPLE workflow modeling cooperatively online.

Keywords: colllaborative framework; visual modeling; message handling mechanism

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Authors: Zoltan Theisz, Gergely Mezei

Abstract:

Modern industrial automation relies on service oriented concepts of Internet of Things (IoT) device modeling in order to provide a flexible and extendable environment for service meta-repository. However, state-of-the-art meta-modeling techniques prefer design-time modeling, which results in a heavy usage of class sometimes unnecessary static subtyping. Although this approach benefits from clear-cut object-oriented design principles, it also seals the model repository for further dynamic extensions. In this paper, a dynamic multi-level modeling approach is introduced that enables dynamic subtyping through a more relaxed partial instantiation mechanism. The approach is demonstrated on a simple sensor network example.

Keywords: Meta-modeling, dynamic subtyping, DMLA, industrial automation, arrowhead.

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Authors: Hidetoshi Nonaka

Abstract:

This paper presents an interactive modeling system of uniform polyhedra using the isomorphic graphs. Especially, Kepler-Poinsot solids are formed by modifications of dodecahedron and icosahedron.

Keywords: Kepler-Poinsot solid, Shape modeling, Polyhedralgraph, Graph drawing.

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Authors: A. Retbi, M. Khalidi Idrissi, S. Bennani

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The success of an e-learning system is highly dependent on the quality of its educational content and how effective, complete, and simple the design tool can be for teachers. Educational modeling languages (EMLs) are proposed as design languages intended to teachers for modeling diverse teaching-learning experiences, independently of the pedagogical approach and in different contexts. However, most existing EMLs are criticized for being too abstract and too complex to be understood and manipulated by teachers. In this paper, we present a visual EML that simplifies the process of designing learning scenarios for teachers with no programming background. Based on the conceptual framework of the activity theory, our resulting visual EML focuses on using Domainspecific modeling techniques to provide a pedagogical level of abstraction in the design process.

Keywords: Educational modeling language, Domain Specific Modeling, authoring systems, learning scenario.

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Authors: Bassam Atieh Rajabi, Sai Peck Lee

Abstract:

Business Process Modeling (BPM) is the first and most important step in business process management lifecycle. Graph based formalism and rule based formalism are the two most predominant formalisms on which process modeling languages are developed. BPM technology continues to face challenges in coping with dynamic business environments where requirements and goals are constantly changing at the execution time. Graph based formalisms incur problems to react to dynamic changes in Business Process (BP) at the runtime instances. In this research, an adaptive and flexible framework based on the integration between Object Oriented diagramming technique and Petri Net modeling language is proposed in order to support change management techniques for BPM and increase the representation capability for Object Oriented modeling for the dynamic changes in the runtime instances. The proposed framework is applied in a higher education environment to achieve flexible, updatable and dynamic BP.

Keywords: Business Process Modeling, Change Management, Graph Based Modeling, Rule Based Modeling, Object Oriented PetriNet.

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Authors: Kyong-min Lee, Moon Soo Chang, PooGyeon Park

Abstract:

In this paper, we propose a geometric modeling of illumination on the patterned image containing etching transistor. This image is captured by a commercial camera during the inspection of a TFT-LCD panel. Inspection of defect is an important process in the production of LCD panel, but the regional difference in brightness, which has a negative effect on the inspection, is due to the uneven illumination environment. In order to solve this problem, we present a geometric modeling of illumination consisting of an interpolation using the least squares method and 3D modeling using bezier surface. Our computational time, by using the sampling method, is shorter than the previous methods. Moreover, it can be further used to correct brightness in every patterned image.

Keywords: Bezier, defect, geometric modeling, illumination, inspection, LCD, panel.

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Authors: K. M. Tan, A. Anvar, T.F. Lu

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A sophisticated simulator provides a cost-effective measure to carry out preliminary mission testing and diagnostic while reducing potential failures for real life at sea trials. The presented simulation framework covers three key areas: AUV modeling, sensor modeling, and environment modeling. AUV modeling mainly covers the area of AUV dynamics. Sensor modeling deals with physics and mathematical models that govern each sensor installed onto the AUV. Environment model incorporates the hydrostatic, hydrodynamics, and ocean currents that will affect the AUV in a real-time mission. Based on this designed simulation framework, custom scenarios provided by the user can be modeled and its corresponding behaviors can be observed. This paper focuses on the accuracy of the simulated data from AUV model and environmental model derived from a developed AUV test-bed which was jointly upgraded by DSTO and the University of Adelaide. The main contribution of this paper is to experimentally verify the accuracy of the proposed simulation framework.

Keywords: Autonomous Underwater Vehicle (AUV), simulator, framework, robotics, maritime robot, modeling.

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