Search results for: Static Voltage Stability
Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 2623

Search results for: Static Voltage Stability

2413 A Cell-Based Multiphase Interleaving Buck Converter with Bypass Capacitors

Authors: T. Taufik, R. Prasetyo, D. Dolan, D. Garinto

Abstract:

Today-s Voltage Regulator Modules (VRMs) face increasing design challenges as the number of transistors in microprocessors increases per Moore-s Law. These challenges have recently become even more demanding as microprocessors operate at sub voltage range at significantly high current. This paper presents a new multiphase topology with cell configuration for improved performance in low voltage and high current applications. A lab scale hardware prototype of the new topology was design and constructed. Laboratory tests were performed on the proposed converter and compared with a commercially available VRM. Results from the proposed topology exhibit improved performance compared to the commercially available counterpart.

Keywords: Voltage Regulator Modules, dc-dc converters, powerelectronics.

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2412 Modeling Low Voltage Power Line as a Data Communication Channel

Authors: Eklas Hossain, Sheroz Khan, Ahad Ali

Abstract:

Power line communications may be used as a data communication channel in public and indoor distribution networks so that it does not require the installing of new cables. Industrial low voltage distribution network may be utilized for data transfer required by the on-line condition monitoring of electric motors. This paper presents a pilot distribution network for modeling low voltage power line as data transfer channel. The signal attenuation in communication channels in the pilot environment is presented and the analysis is done by varying the corresponding parameters for the signal attenuation.

Keywords: Data communication, indoor distribution networks, low voltage, power line.

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2411 Assessing and Visualizing the Stability of Feature Selectors: A Case Study with Spectral Data

Authors: R.Guzman-Martinez, Oscar Garcia-Olalla, R.Alaiz-Rodriguez

Abstract:

Feature selection plays an important role in applications with high dimensional data. The assessment of the stability of feature selection/ranking algorithms becomes an important issue when the dataset is small and the aim is to gain insight into the underlying process by analyzing the most relevant features. In this work, we propose a graphical approach that enables to analyze the similarity between feature ranking techniques as well as their individual stability. Moreover, it works with whatever stability metric (Canberra distance, Spearman's rank correlation coefficient, Kuncheva's stability index,...). We illustrate this visualization technique evaluating the stability of several feature selection techniques on a spectral binary dataset. Experimental results with a neural-based classifier show that stability and ranking quality may not be linked together and both issues have to be studied jointly in order to offer answers to the domain experts.

Keywords: Feature Selection Stability, Spectral data, Data visualization

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2410 Metal Berthelot Tubes with Windows for Observing Cavitation under Static Negative Pressure

Authors: K. Hiro, Y. Imai, T. Sasayama

Abstract:

Cavitation under static negative pressure is not revealed well. The Berthelot method to generate such negative pressure can be a means to study cavitation inception. In this study, metal Berthelot tubes built in observation windows are newly developed and are checked whether high static negative pressure is generated or not. Negative pressure in the tube with a pair of a corundum plate and an aluminum gasket increased with temperature cycles. The trend was similar to that as reported before.

Keywords: Berthelot method, negative pressure, cavitation.

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2409 A Comparative Study of Force Prediction Models during Static Bending Stage for 3-Roller Cone Frustum Bending

Authors: Mahesh Chudasama, Harit Raval

Abstract:

Conical sections and shells of metal plates manufactured by 3-roller conical bending process are widely used in the industries. The process is completed by first bending the metal plates statically and then dynamic roller bending sequentially. It is required to have an analytical model to get maximum bending force, for optimum design of the machine, for static bending stage. Analytical models assuming various stress conditions are considered and these analytical models are compared considering various parameters and reported in this paper. It is concluded from the study that for higher bottom roller inclination, the shear stress affects greatly to the static bending force whereas for lower bottom roller inclination it can be neglected.

Keywords: Roller-bending, static-bending, stress-conditions, analytical-modeling.

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2408 Influence of Harmonics on Medium Voltage Distribution System: A Case Study for Residential Area

Authors: O. Arikan, C. Kocatepe, G. Ucar, Y. Hacialiefendioglu

Abstract:

In this paper, influence of harmonics on medium voltage distribution system of Bogazici Electricity Distribution Inc. (BEDAS) which takes place at Istanbul/Turkey is investigated. A ring network consisting of residential loads is taken into account for this study. Real system parameters and measurement results are used for simulations. Also, probable working conditions of the system are analyzed for 50%, 75%, and 100% loading of transformers with similar harmonic contents. Results of the study are exhibited the influence of nonlinear loads on %THDV, P.F. and technical losses of the medium voltage distribution system.

Keywords: Distribution system, harmonic, technical losses, power factor (PF), total harmonic distortion (THD), residential load, medium voltage.

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2407 Delay-Dependent Stability Analysis for Neural Networks with Distributed Delays

Authors: Qingqing Wang, Shouming Zhong

Abstract:

This paper deals with the problem of delay-dependent stability for neural networks with distributed delays. Some new sufficient condition are derived by constructing a novel Lyapunov-Krasovskii functional approach. The criteria are formulated in terms of a set of linear matrix inequalities, this is convenient for numerically checking the system stability using the powerful MATLAB LMI Toolbox. Moreover, in order to show the stability condition in this paper gives much less conservative results than those in the literature, numerical examples are considered.

Keywords: Neural networks, Globally asymptotic stability , LMI approach, Distributed delays.

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2406 A Novel Zero Voltage Transition Synchronous Buck Converter for Portable Application

Authors: S. Pattnaik, A. K. Panda, Aroul K., K. K. Mahapatra

Abstract:

This paper proposes a zero-voltage transition (ZVT) PWM synchronous buck converter, which is designed to operate at low output voltage and high efficiency typically required for portable systems. To make the DC-DC converter efficient at lower voltage, synchronous converter is an obvious choice because of lower conduction loss in the diode. The high-side MOSFET is dominated by the switching losses and it is eliminated by the soft switching technique. Additionally, the resonant auxiliary circuit designed is also devoid of the switching losses. The suggested procedure ensures an efficient converter. Theoretical analysis, computer simulation, and experimental results are presented to explain the proposed schemes.

Keywords: DC-DC Converter, Switching loss, Synchronous Buck, Soft switching, ZVT.

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2405 Selective Harmonic Elimination of PWM AC/AC Voltage Controller Using Hybrid RGA-PS Approach

Authors: A. K. Al-Othman, Nabil A. Ahmed, A. M. Al-Kandari, H. K. Ebraheem

Abstract:

Selective harmonic elimination-pulse width modulation techniques offer a tight control of the harmonic spectrum of a given voltage waveform generated by a power electronic converter along with a low number of switching transitions. Traditional optimization methods suffer from various drawbacks, such as prolonged and tedious computational steps and convergence to local optima; thus, the more the number of harmonics to be eliminated, the larger the computational complexity and time. This paper presents a novel method for output voltage harmonic elimination and voltage control of PWM AC/AC voltage converters using the principle of hybrid Real-Coded Genetic Algorithm-Pattern Search (RGA-PS) method. RGA is the primary optimizer exploiting its global search capabilities, PS is then employed to fine tune the best solution provided by RGA in each evolution. The proposed method enables linear control of the fundamental component of the output voltage and complete elimination of its harmonic contents up to a specified order. Theoretical studies have been carried out to show the effectiveness and robustness of the proposed method of selective harmonic elimination. Theoretical results are validated through simulation studies using PSIM software package.

Keywords: PWM, AC/AC voltage converters, selectiveharmonic elimination, direct search method, pattern search method, Real-coded Genetic algorithms, evolutionary algorithms andoptimization.

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2404 Voltage Sag Characteristics during Symmetrical and Asymmetrical Faults

Authors: Ioannis Binas, Marios Moschakis

Abstract:

Electrical faults in transmission and distribution networks can have great impact on the electrical equipment used. Fault effects depend on the characteristics of the fault as well as the network itself. It is important to anticipate the network’s behavior during faults when planning a new equipment installation, as well as troubleshooting. Moreover, working backwards, we could be able to estimate the characteristics of the fault when checking the perceived effects. Different transformer winding connections dominantly used in the Greek power transfer and distribution networks and the effects of 1-phase to neutral, phase-to-phase, 2-phases to neutral and 3-phase faults on different locations of the network were simulated in order to present voltage sag characteristics. The study was performed on a generic network with three steps down transformers on two voltage level buses (one 150 kV/20 kV transformer and two 20 kV/0.4 kV). We found that during faults, there are significant changes both on voltage magnitudes and on phase angles. The simulations and short-circuit analysis were performed using the PSCAD simulation package. This paper presents voltage characteristics calculated for the simulated network, with different approaches on the transformer winding connections during symmetrical and asymmetrical faults on various locations.

Keywords: Phase angle shift, power quality, transformer winding connections, voltage sag propagation.

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2403 The Design of PFM Mode DC-DC Converter with DT-CMOS Switch

Authors: Jae-Chang Kwak, Yong-Seo Koo

Abstract:

The high efficiency power management IC (PMIC) with switching device is presented in this paper. PMIC is controlled with PFM control method in order to have high power efficiency at high current level. Dynamic Threshold voltage CMOS (DT-CMOS) with low on-resistance is designed to decrease conduction loss. The threshold voltage of DT-CMOS drops as the gate voltage increase, resulting in a much higher current handling capability than standard MOSFET. PFM control circuits consist of a generator, AND gate and comparator. The generator is made to have 1.2MHz oscillation voltage. The DC-DC converter based on PFM control circuit and low on-resistance switching device is presented in this paper.

Keywords: DT-CMOS, PMIC, PFM, DC-DC converter.

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2402 Stability Analysis of Linear Switched Systems with Mixed Delays

Authors: Xiuyong Ding, Lan Shu

Abstract:

This paper addresses the stability of the switched systems with discrete and distributed time delays. By applying Lyapunov functional and function method, we show that, if the norm of system matrices Bi is small enough, the asymptotic stability is always achieved. Finally, a example is provided to verify technically feasibility and operability of the developed results.

Keywords: Switched system, stability, Lyapunov function, Lyapunov functional, delays.

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2401 A Test Methodology to Measure the Open-Loop Voltage Gain of an Operational Amplifier

Authors: Maninder Kaur Gill, Alpana Agarwal

Abstract:

It is practically not feasible to measure the open-loop voltage gain of the operational amplifier in the open loop configuration. It is because the open-loop voltage gain of the operational amplifier is very large. In order to avoid the saturation of the output voltage, a very small input should be given to operational amplifier which is not possible to be measured practically by a digital multimeter. A test circuit for measurement of open loop voltage gain of an operational amplifier has been proposed and verified using simulation tools as well as by experimental methods on breadboard. The main advantage of this test circuit is that it is simple, fast, accurate, cost effective, and easy to handle even on a breadboard. The test circuit requires only the device under test (DUT) along with resistors. This circuit has been tested for measurement of open loop voltage gain for different operational amplifiers. The underlying goal is to design testable circuits for various analog devices that are simple to realize in VLSI systems, giving accurate results and without changing the characteristics of the original system. The DUTs used are LM741CN and UA741CP. For LM741CN, the simulated gain and experimentally measured gain (average) are calculated as 89.71 dB and 87.71 dB, respectively. For UA741CP, the simulated gain and experimentally measured gain (average) are calculated as 101.15 dB and 105.15 dB, respectively. These values are found to be close to the datasheet values.

Keywords: Device under test, open-loop voltage gain, operational amplifier, test circuit.

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2400 Linear Pocket Profile based Threshold Voltage Model for sub-100 nm n-MOSFET

Authors: Muhibul Haque Bhuyan, Quazi Deen Mohd Khosru

Abstract:

This paper presents a threshold voltage model of pocket implanted sub-100 nm n-MOSFETs incorporating the drain and substrate bias effects using two linear pocket profiles. Two linear equations are used to simulate the pocket profiles along the channel at the surface from the source and drain edges towards the center of the n-MOSFET. Then the effective doping concentration is derived and is used in the threshold voltage equation that is obtained by solving the Poisson-s equation in the depletion region at the surface. Simulated threshold voltages for various gate lengths fit well with the experimental data already published in the literature. The simulated result is compared with the two other pocket profiles used to derive the threshold voltage models of n-MOSFETs. The comparison shows that the linear model has a simple compact form that can be utilized to study and characterize the pocket implanted advanced ULSI devices.

Keywords: Linear pocket profile, pocket implantation, nMOSFET, threshold voltage, short channel effect (SCE), reverse short channeleffect (RSCE).

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2399 Static Study of Piezoelectric Bimorph Beams with Delamination Zone

Authors: A. Zemirline, M. Ouali, A. Mahieddine

Abstract:

The FOSDT (the First Order Shear Deformation Theory) is taking into consideration to study the static behavior of a bimorph beam, with a delamination zone between the upper and the lower layer. The effect of limit conditions and lengths of the delamination zone are presented in this paper, with a PVDF piezoelectric material application. A FEM “Finite Element Method” is used to discretize the beam. In the axial displacement, a displacement field appears in the debonded zone with inverse effect between the upper and the lower layer was observed.

Keywords: Beam, Delamination, Piezoelectricity, Static.

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2398 An On-chip LDO Voltage Regulator with Improved Current Buffer Compensation

Authors: Lv Xiaopeng, Bian Qiang, Yue Suge

Abstract:

A fully on-chip low drop-out (LDO) voltage regulator with 100pF output load capacitor is presented. A novel frequency compensation scheme using current buffer is adopted to realize single dominant pole within the unit gain frequency of the regulation loop, the phase margin (PM) is at least 50 degree under the full range of the load current, and the power supply rejection (PSR) character is improved compared with conventional Miller compensation. Besides, the differentiator provides a high speed path during the load current transient. Implemented in 0.18μm CMOS technology, the LDO voltage regulator provides 100mA load current with a stable 1.8V output voltage consuming 80μA quiescent current.

Keywords: capacitor-less LDO, frequency compensation, transient response, power supply rejection

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2397 Gravitational Search Algorithm (GSA) Optimized SSSC Based Facts Controller to Improve Power System Oscillation Stability

Authors: Gayadhar Panda, P. K. Rautraya

Abstract:

Damping of inter-area electromechanical oscillations is one of the major challenges to the electric power system operators. This paper presents Gravitational Search Algorithm (GSA) for tuning Static Synchronous Series Compensator (SSSC) based damping controller to improve power system oscillation stability. In the proposed algorithm, the searcher agents are a collection of masses which interact with each other based on the Newtonian gravity and the laws of motion. The effectiveness of the scheme in damping power system oscillations during system faults at different loading conditions is demonstrated through time-domain simulation.

Keywords: FACTS, Damping controller design, Gravitational search algorithm (GSA), Power system oscillations, Single-machine infinite Bus power system, SSSC.

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2396 A Single Phase ZVT-ZCT Power Factor Correction Boost Converter

Authors: Yakup Sahin, Naim Suleyman Ting, Ismail Aksoy

Abstract:

In this paper, a single phase soft switched Zero Voltage Transition and Zero Current Transition (ZVT-ZCT) Power Factor Correction (PFC) boost converter is proposed. In the proposed PFC converter, the main switch turns on with ZVT and turns off with ZCT without any additional voltage or current stresses. Auxiliary switch turns on and off with zero current switching (ZCS). Also, the main diode turns on with zero voltage switching (ZVS) and turns off with ZCS. The proposed converter has features like low cost, simple control and structure. The output current and voltage are controlled by the proposed PFC converter in wide line and load range. The theoretical analysis of converter is clarified and the operating steps are given in detail. The simulation results of converter are obtained for 500 W and 100 kHz. It is observed that the semiconductor devices operate with soft switching (SS) perfectly. So, the switching power losses are minimum. Also, the proposed converter has 0.99 power factor with sinusoidal current shape.

Keywords: Power factor correction, zero-voltage transition, zero-current transition, soft switching.

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2395 Influence of Paralleled Capacitance Effect in Well-defined Multiple Value Logical Level System with Active Load

Authors: Chih Chin Yang, Yen Chun Lin, Hsiao Hsuan Cheng

Abstract:

Three similar negative differential resistance (NDR) profiles with both high peak to valley current density ratio (PVCDR) value and high peak current density (PCD) value in unity resonant tunneling electronic circuit (RTEC) element is developed in this paper. The PCD values and valley current density (VCD) values of the three NDR curves are all about 3.5 A and 0.8 A, respectively. All PV values of NDR curves are 0.40 V, 0.82 V, and 1.35 V, respectively. The VV values are 0.61 V, 1.07 V, and 1.69 V, respectively. All PVCDR values reach about 4.4 in three NDR curves. The PCD value of 3.5 A in triple PVCDR RTEC element is better than other resonant tunneling devices (RTD) elements. The high PVCDR value is concluded the lower VCD value about 0.8 A. The low VCD value is achieved by suitable selection of resistors in triple PVCDR RTEC element. The low PV value less than 1.35 V possesses low power dispersion in triple PVCDR RTEC element. The designed multiple value logical level (MVLL) system using triple PVCDR RTEC element provides equidistant logical level. The logical levels of MVLL system are about 0.2 V, 0.8 V, 1.5 V, and 2.2 V from low voltage to high voltage and then 2.2 V, 1.3 V, 0.8 V, and 0.2 V from high voltage back to low voltage in half cycle of sinusoid wave. The output level of four levels MVLL system is represented in 0.3 V, 1.1 V, 1.7 V, and 2.6 V, which satisfies the NMP condition of traditional two-bit system. The remarkable logical characteristic of improved MVLL system with paralleled capacitor are with four significant stable logical levels about 220 mV, 223 mV, 228 mV, and 230 mV. The stability and articulation of logical levels of improved MVLL system are outstanding. The average holding time of improved MVLL system is approximately 0.14 μs. The holding time of improved MVLL system is fourfold than of basic MVLL system. The function of additional capacitor in the improved MVLL system is successfully discovered.

Keywords: Capacitance, Logical level, Constant current source

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2394 Characteristics Analysis of Voltage Sag and Voltage Swell in Multi-Grounded Four-Wire Power Distribution Systems

Authors: Jamal Moshtagh, Hassan Pourvali Souraki

Abstract:

In North America, Most power distribution systems employ a four-wire multi-grounded neutral (MGN) design. This paper has explained the inherent characteristics of multi-grounded three-phase four-wire distribution systems under unbalanced situations. As a result, the mechanism of voltage swell and voltage sag in MGN feeders becomes difficult to understand. The simulation tool that has been used in this paper is MATLAB under Windows software. In this paper the equivalent model of a full-scale multigrounded distribution system implemented by MATLAB is introduced. The results are expected to help utility engineers to understand the impact of MGN on distribution system operations.

Keywords: Distribution systems, multi- grounded, neutral, three-phase four-wire, ground.

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2393 Stability of Interval Fractional-order Systems with Order 0 < α < 1

Authors: Hong Li, Shou-ming Zhong, Hou-biao Li

Abstract:

In this paper, some brief sufficient conditions for the stability of FO-LTI systems dαx(t) dtα = Ax(t) with the fractional order are investigated when the matrix A and the fractional order α are uncertain or both α and A are uncertain, respectively. In addition, we also relate the stability of a fractional-order system with order 0 < α ≤ 1 to the stability of its equivalent fractional-order system with order 1 ≤ β < 2, the relationship between α and β is presented. Finally, a numeric experiment is given to demonstrate the effectiveness of our results.

Keywords: Interval fractional-order systems, linear matrix inequality (LMI), asymptotical stability.

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2392 Investigation of Threshold Voltage Shift in Gamma Irradiated N-Channel and P-Channel MOS Transistors of CD4007

Authors: S. Boorboor, S. A. H. Feghhi, H. Jafari

Abstract:

The ionizing radiations cause different kinds of damages in electronic components. MOSFETs, most common transistors in today’s digital and analog circuits, are severely sensitive to TID damage. In this work, the threshold voltage shift of CD4007 device, which is an integrated circuit including P-channel and N-channel MOS transistors, was investigated for low dose gamma irradiation under different gate bias voltages. We used linear extrapolation method to extract threshold voltage from ID-VG characteristic curve. The results showed that the threshold voltage shift was approximately 27.5 mV/Gy for N-channel and 3.5 mV/Gy for P-channel transistors at the gate bias of |9 V| after irradiation by Co-60 gamma ray source. Although the sensitivity of the devices under test were strongly dependent to biasing condition and transistor type, the threshold voltage shifted linearly versus accumulated dose in all cases. The overall results show that the application of CD4007 as an electronic buffer in a radiation therapy system is limited by TID damage. However, this integrated circuit can be used as a cheap and sensitive radiation dosimeter for accumulated dose measurement in radiation therapy systems.

Keywords: Threshold voltage shift, MOS transistor, linear extrapolation, gamma irradiation.

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2391 Design and Analysis of Low-Power, High Speed and Area Efficient 2-Bit Digital Magnitude Comparator in 90nm CMOS Technology Using Gate Diffusion Input

Authors: Fasil Endalamaw

Abstract:

Digital magnitude comparators based on Gate Diffusion Input (GDI) implementation technique are high speed and area-efficient, and they consume less power as compared to other implementation techniques. However, they are less efficient for some logic gates and have no full voltage swing. In this paper, we made a performance comparison between the GDI implementation technique and other implementation methods, such as Static CMOS, Pass Transistor Logic (PTL), and Transmission Gate (TG) in 90 nm, 120 nm, and 180 nm CMOS technologies using BSIM4 MOS model. We proposed a methodology (hybrid implementation) of implementing digital magnitude comparators which significantly improved the power, speed, area, and voltage swing requirements. Simulation results revealed that the hybrid implementation of digital magnitude comparators show a 10.84% (power dissipation), 41.6% (propagation delay), 47.95% (power-delay product (PDP)) improvement compared to the usual GDI implementation method. We used Microwind & Dsch Version 3.5 as well as the Tanner EDA 16.0 tools for simulation purposes.

Keywords: Efficient, gate diffusion input, high speed, low power, CMOS.

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2390 Influence of Heat Transfer on Stability of Newtonian and Non-Newtonian Extending Films

Authors: Olus N. Boratav, Zheming Zheng, Chunfeng Zhou

Abstract:

The stability of Newtonian and Non-Newtonian extending films under local or global heating or cooling conditions are considered. The thickness-averaged mass, momentum and energy equations with convective and radiative heat transfer are derived, both for Newtonian and non-Newtonian fluids (Maxwell, PTT and Giesekus models considered). The stability of the system is explored using either eigenvalue analysis or transient simulations. The results showed that the influence of heating and cooling on stability strongly depends on the magnitude of the Peclet number. Examples of stabilization or destabilization of heating or cooling are shown for Pe<< 1, and Pe = O(1) cases, for Newtonian and non-Newtonian flows.

Keywords: Extended films, stability, eigen-analysis for stability, transient response, polymer instability, Non-Newtonian fluids.

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2389 On Two Control Approaches for The Output Voltage Regulation of a Boost Converter

Authors: Abdelaziz Sahbani, Kamel Ben Saad, Mohamed Benrejeb

Abstract:

This paper deals with the comparison between two proposed control strategies for a DC-DC boost converter. The first control is a classical Sliding Mode Control (SMC) and the second one is a distance based Fuzzy Sliding Mode Control (FSMC). The SMC is an analytical control approach based on the boost mathematical model. However, the FSMC is a non-conventional control approach which does not need the controlled system mathematical model. It needs only the measures of the output voltage to perform the control signal. The obtained simulation results show that the two proposed control methods are robust for the case of load resistance and the input voltage variations. However, the proposed FSMC gives a better step voltage response than the one obtained by the SMC.

Keywords: Boost DC-DC converter, Sliding Mode Control (SMC), Fuzzy Sliding Mode Control (FSMC), Robustness.

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2388 Improved Asymptotic Stability Criteria for Uncertain Neutral Systems with Time-varying Discrete Delays

Authors: Changchun Shen, Shouming Zhong

Abstract:

This paper investigates the robust stability of uncertain neutral system with time-varying delay. By using Lyapunov method and linear matrix inequality technology, new delay-dependent stability criteria are obtained and formulated in terms of linear matrix inequalities (LMIs), which can be easy to check the robust stability of the considered systems. Numerical examples are given to indicate significant improvements over some existing results.

Keywords: Neutral system, linear matrix inequalities, Lyapunov, stability.

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2387 Using the Schunt Active Power Filter for Compensation of the Distorted and Umbalanced Power System Voltage

Authors: I. Habi, M. Bouguerra, D. Ouahdi, H. Meglouli

Abstract:

In this paper, we apply the PQ theory with shunt active power filter in an unbalanced and distorted power system voltage to compensate the perturbations generated by non linear load. The power factor is also improved in the current source. The PLL system is used to extract the fundamental component of the even sequence under conditions mentioned of the power system voltage.

Keywords: Converter, power filter, harmonies, non-linear load, pq theory, PLL, unbalanced voltages, distorted voltages.

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2386 Triple-input Single-output Voltage-mode Multifunction Filter Using Only Two Current Conveyors

Authors: Mehmet Sagbas, Kemal Fidanboylu, M. Can Bayram

Abstract:

A new voltage-mode triple-input single-output multifunction filter using only two current conveyors is presented. The proposed filter which possesses three inputs and single-output can generate all biquadratic filtering functions at the output terminal by selecting different input signal combinations. The validity of the proposed filter is verified through PSPICE simulations.

Keywords: Active Filters, Voltage mode, Current conveyor

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2385 Exploring SSD Suitable Allocation Schemes Incompliance with Workload Patterns

Authors: Jae Young Park, Hwansu Jung, Jong Tae Kim

Abstract:

In the Solid-State-Drive (SSD) performance, whether the data has been well parallelized is an important factor. SSD parallelization is affected by allocation scheme and it is directly connected to SSD performance. There are dynamic allocation and static allocation in representative allocation schemes. Dynamic allocation is more adaptive in exploiting write operation parallelism, while static allocation is better in read operation parallelism. Therefore, it is hard to select the appropriate allocation scheme when the workload is mixed read and write operations. We simulated conditions on a few mixed data patterns and analyzed the results to help the right choice for better performance. As the results, if data arrival interval is long enough prior operations to be finished and continuous read intensive data environment static allocation is more suitable. Dynamic allocation performs the best on write performance and random data patterns.

Keywords: Dynamic allocation, NAND Flash based SSD, SSD parallelism, static allocation.

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2384 Sensitivity of Input Blocking Capacitor on Output Voltage and Current of a PV Inverter Employing IGBTs

Authors: Z.A. Jaffery, Vinay Kumar Chandna, Sunil Kumar Chaudhary

Abstract:

This paper present a MATLAB-SIMULINK model of a single phase 2.5 KVA, 240V RMS controlled PV VSI (Photovoltaic Voltage Source Inverter) inverter using IGBTs (Insulated Gate Bipolar Transistor). The behavior of output voltage, output current, and the total harmonic distortion (THD), with the variation in input dc blocking capacitor (Cdc), for linear and non-linear load has been analyzed. The values of Cdc as suggested by the other authors in their papers are not clearly defined and it poses difficulty in selecting the proper value. As the dc power stored in Cdc, (generally placed parallel with battery) is used as input to the VSI inverter. The simulation results shows the variation in the output voltage and current with different values of Cdc for linear and non-linear load connected at the output side of PV VSI inverter and suggest the selection of suitable value of Cdc.

Keywords: DC Blocking capacitor, IGBTs, PV VSI, THD.

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