Search results for: P-type adiabatic circuits.

Authors: Jerome G. Chandraseelan, Samuel M. D. Oliveira, Antti Häkkinen, Sofia Startceva, Andre S. Ribeiro

Abstract:

We used live E. coli containing synthetic genetic oscillators to study how the degree of synchrony between the genetic circuits of sister cells changes with temperature. We found that both the mean and the variability of the degree of synchrony between the fluorescence signals from sister cells are affected by temperature. Also, while most pairs of sister cells were found to be highly synchronous in each condition, the number of asynchronous pairs increased with increasing temperature, which was found to be due to disruptions in the oscillations. Finally we provide evidence that these disruptions tend to affect multiple generations as opposed to individual cells. These findings provide insight in how to design more robust synthetic circuits and in how cell division can affect their dynamics.

Keywords: Repressilator, robustness, synchrony, synthetic biology.

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Authors: Sara Felloni, Giuliano Strini

Abstract:

We explore entanglement in composite quantum systems and how its peculiar properties are exploited in quantum information and communication protocols by means of Diagrams of States, a novel method to graphically represent and analyze how quantum information is elaborated during computations performed by quantum circuits. We present quantum diagrams of states for Bell states generation, measurements and projections, for dense coding and quantum teleportation, for probabilistic quantum machines designed to perform approximate quantum cloning and universal NOT and, finally, for quantum privacy amplification based on entanglement purification. Diagrams of states prove to be a useful approach to analyze quantum computations, by offering an intuitive graphic representation of the processing of quantum information. They also help in conceiving novel quantum computations, from describing the desired information processing to deriving the final implementation by quantum gate arrays.

Keywords: Diagrams of states, entanglement, quantum circuits, quantum information.

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Authors: K. A. Sumithradevi, Vijayalakshmi. M. N., Annamma Abraham., Dr. Vasanta

Abstract:

The various applications of VLSI circuits in highperformance computing, telecommunications, and consumer electronics has been expanding progressively, and at a very hasty pace. This paper describes a new model for partitioning a circuit using DBSCAN and fuzzy ARTMAP neural network. The first step is concerned with feature extraction, where we had make use DBSCAN algorithm. The second step is the classification and is composed of a fuzzy ARTMAP neural network. The performance of both approaches is compared using benchmark data provided by MCNC standard cell placement benchmark netlists. Analysis of the investigational results proved that the fuzzy ARTMAP with DBSCAN model achieves greater performance then only fuzzy ARTMAP in recognizing sub-circuits with lowest amount of interconnections between them The recognition rate using fuzzy ARTMAP with DBSCAN is 97.7% compared to only fuzzy ARTMAP.

Keywords: VLSI, Circuit partitioning, DBSCAN, fuzzyARTMAP.

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Authors: Jelena Slugan, Ivica Ružić

Abstract:

We are witnessing the rapid development of technologies that change the world around us. However, curriculums and teaching processes are often slow to adapt to the change; it takes time, money and expertise to implement technology in the classroom. Therefore, the University of Split, Croatia, partnered with local school Marko Marulić High School and created the project "Modern competence in modern high schools" as part of which five different curriculums for STEM areas were developed. One of the curriculums involves combining information technology with physics. The main idea was to teach students how to use different circuits and microcomputers to explore nature and physical phenomena. As a result, using electrical circuits, students are able to recreate in the classroom the phenomena that they observe every day in their environment. So far, high school students had very little opportunity to perform experiments independently, and especially, those physics experiment did not involve ICT. Therefore, this project has a great importance, because the students will finally get a chance to develop themselves in accordance to modern technologies. This paper presents some new methods of teaching physics that will help students to develop experimental skills through the study of deterministic nature of physical laws. Students will learn how to formulate hypotheses, model physical problems using the electronic circuits and evaluate their results. While doing that, they will also acquire useful problem solving skills.

Keywords: ICT in physics, curriculum, laboratory activities, STEM.

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Authors: Padmanabhan Balasubramanian, Bashetty Raghavendra

Abstract:

In this paper, an analysis is presented, which demonstrates the effect pre-logic factoring could have on an automated combinational logic synthesis process succeeding it. The impact of pre-logic factoring for some arbitrary combinatorial circuits synthesized within a FPGA based logic design environment has been analyzed previously. This paper explores a similar effect, but with the non-regenerative logic synthesized using elements of a commercial standard cell library. On an overall basis, the results obtained pertaining to the analysis on a variety of MCNC/IWLS combinational logic benchmark circuits indicate that pre-logic factoring has the potential to facilitate simultaneous power, delay and area optimized synthesis solutions in many cases.

Keywords: Algebraic factoring, Combinational logic synthesis, Standard cells, Low power, Delay optimization, Area reduction.

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Authors: Jae Young Park, Soongyu Kwon, Kyu Han Kim, Hyeong Geon Lee, Jong Tae Kim

Abstract:

This paper considers the problem of finding low cost chip set for a minimum cost partitioning of a large logic circuits. Chip sets are selected from a given library. Each chip in the library has a different price, area, and I/O pin. We propose a low cost chip set selection algorithm. Inputs to the algorithm are a netlist and a chip information in the library. Output is a list of chip sets satisfied with area and maximum partitioning number and it is sorted by cost. The algorithm finds the sorted list of chip sets from minimum cost to maximum cost. We used MCNC benchmark circuits for experiments. The experimental results show that all of chip sets found satisfy the multiple partitioning constraints.

Keywords: lowest cost chip set, MCNC benchmark, multi-way partitioning.

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Authors: Labar Hocine, Rekik Badri, Bounaya Kamel, Kelaiaia Mounia Samira

Abstract:

Diagnostic goal of transformers in service is to detect the winding or the core in fault. Transformers are valuable equipment which makes a major contribution to the supply security of a power system. Consequently, it is of great importance to minimize the frequency and duration of unwanted outages of power transformers. So, Frequency Response Analysis (FRA) is found to be a useful tool for reliable detection of incipient mechanical fault in a transformer, by finding winding or core defects. The authors propose as first part of this article, the coupled circuits method, because, it gives most possible exhaustive modelling of transformers. And as second part of this work, the application of FRA in low frequency in order to improve and simplify the response reading. This study can be useful as a base data for the other transformers of the same categories intended for distribution grid.

Keywords: Diagnostic, Coupled Circuit Method, FRA, Transformer Faults

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Authors: Shiyang Zhu, G. Q. Lo, D. L. Kwong

Abstract:

Silicon photonics has generated an increasing interest in recent years mainly for optical communications optical interconnects in microelectronic circuits or bio-sensing applications. The development of elementary passive and active components (including detectors and modulators), which are mainly fabricated on the silicon on insulator platform for CMOS-compatible fabrication, has reached such a performance level that the integration challenge of silicon photonics with microelectronic circuits should be addressed. Since crystalline silicon can only be grown from another silicon crystal, making it impossible to deposit in this state, the optical devices are typically limited to a single layer. An alternative approach is to integrate a photonic layer above the CMOS chip using back-end CMOS fabrication process. In this paper, various materials, including silicon nitride, amorphous silicon, and polycrystalline silicon, for this purpose are addressed.

Keywords: Silicon photonics, CMOS, Integration.

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Authors: M. T. Anwar, P. K. Lala, P. Thenappan

Abstract:

This paper presents the decoder design for the single error correcting and double error detecting code proposed by the authors in an earlier paper. The speed of error detection and correction of a code is largely dependent upon the associated encoder and decoder circuits. The complexity and the speed of such circuits are determined by the number of 1?s in the parity check matrix (PCM). The number of 1?s in the parity check matrix for the code proposed by the authors are fewer than in any currently known single error correcting/double error detecting code. This results in simplified encoding and decoding circuitry for error detection and correction.

Keywords: Decoder, Hsiao code, Parity Check Matrix, Syndrome Pattern.

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Authors: B. Rezaei, G. R. Boroun, M. Abdolmaleki

Abstract:

The bound state energy of three quark systems is studied in the framework of a non- relativistic spin independent phenomenological model. The hyper- spherical coordinates are considered for the solution this system. According to Jacobi coordinate, we determined the bound state energy for (uud) and (ddu) quark systems, as quarks are flavorless mass, and it is restrict that choice potential at low and high range in nucleon bag for a bound state.

Keywords: Adiabatic expansion, grand angular momentum, binding energy, perturbation, baryons.

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Authors: Mada Sanjaya, Halimatussadiyah, Dian Syah Maulana

Abstract:

The nonlinear chaotic non-autonomous fourth order system is algebraically simple but can generate complex chaotic attractors. In this paper, non-autonomous fourth order chaotic oscillator circuits were designed and simulated. Also chaotic nonautonomous Attractor is addressed suitable for chaotic masking communication circuits using Matlab® and MultiSIM® programs. We have demonstrated in simulations that chaos can be synchronized and applied to signal masking communications. We suggest that this phenomenon of chaos synchronism may serve as the basis for little known chaotic non-autonomous Attractor to achieve signal masking communication applications. Simulation results are used to visualize and illustrate the effectiveness of non-autonomous chaotic system in signal masking. All simulations results performed on nonautonomous chaotic system are verify the applicable of secure communication.

Keywords: Bidirectional chaotic synchronization, double bellattractor, secure communication

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Authors: Zahra Khalid, Gul Muhammad Khan, Arbab Masood Ahmad

Abstract:

Cartesian Genetic Programming (CGP) is explored to design an optimal circuit capable of early stage breast cancer detection. CGP is used to evolve simple multiplexer circuits for detection of malignancy in the Fine Needle Aspiration (FNA) samples of breast. The data set used is extracted from Wisconsins Breast Cancer Database (WBCD). A range of experiments were performed, each with different set of network parameters. The best evolved network detected malignancy with an accuracy of 99.14%, which is higher than that produced with most of the contemporary non-linear techniques that are computational expensive than the proposed system. The evolved network comprises of simple multiplexers and can be implemented easily in hardware without any further complications or inaccuracy, being the digital circuit.

Keywords: Breast cancer detection, cartesian genetic programming, evolvable hardware, fine needle aspiration (FNA).

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Authors: Mohamed Sanad, Noha Hassan

Abstract:

A broadband resonant terminal antenna has been developed. It can be used in different MIMO arrangements such as 2x2, 4x4, 8x8, or even 12x12 MIMO configurations. The antenna covers the whole LTE and WiFi bands besides the existing 2G/3G bands (700-5800 MHz), without using any matching/tuning circuits. Matching circuits significantly reduce the efficiency of any antenna and reduce the battery life. They also reduce the bandwidth because they are frequency dependent. The antenna can be implemented in smartphone handsets, tablets, laptops, notebooks or any other terminal. It is also suitable for different IoT and vehicle applications. The antenna is manufactured from a flexible material and can be bent or folded and shaped in any form to fit any available space in any terminal. It is self-contained and does not need to use the ground plane, the chassis or any other component of the terminal. Hence, it can be mounted on any terminal at different positions and configurations. Its performance does not get affected by the terminal, regardless of its type, shape or size. Moreover, its performance does not get affected by the human body of the terminal’s users. Because of all these unique features of the antenna, multiples of them can be simultaneously used for MIMO diversity coverage in any terminal device with a high isolation and a low correlation factor between them.

Keywords: IOT, LTE, MIMO, terminal antenna, WiFi.

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Authors: Abdeljalil Métioui

Abstract:

We discuss the alternative conceptions of students analysing the behaviour of electrical circuits. The present paper aims at, on one hand, studying the misconceptions of 80 elementary pre-service teachers from Quebec in Canada, in relation to the current source in DC circuits. To do this, they completed a two-choice questionnaire (true or false) with justification. Data analysis identifies many conceptual difficulties. For example, their majority considered a battery as a source of constant current: When a circuit composed of battery and resistors is modified, the current supplied by the battery remains unchanged. On the other hand, considering the alternatives conceptions identified we develop a two-tier test about source current. The aim of this two-tier test is to help teachers to diagnose rapidly their students’ misconceptions in order to consider in their teaching.   

Keywords: Two-tier diagnostic test, current source, pre-service teachers, alternative conceptions after teaching, qualitative study.

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Authors: Padmanabhan Balasubramanian, Karthik Anantha

Abstract:

Structural representation and technology mapping of a Boolean function is an important problem in the design of nonregenerative digital logic circuits (also called combinational logic circuits). Library aware function manipulation offers a solution to this problem. Compact multi-level representation of binary networks, based on simple circuit structures, such as AND-Inverter Graphs (AIG) [1] [5], NAND Graphs, OR-Inverter Graphs (OIG), AND-OR Graphs (AOG), AND-OR-Inverter Graphs (AOIG), AND-XORInverter Graphs, Reduced Boolean Circuits [8] does exist in literature. In this work, we discuss a novel and efficient graph realization for combinational logic circuits, represented using a NAND-NOR-Inverter Graph (NNIG), which is composed of only two-input NAND (NAND2), NOR (NOR2) and inverter (INV) cells. The networks are constructed on the basis of irredundant disjunctive and conjunctive normal forms, after factoring, comprising terms with minimum support. Construction of a NNIG for a non-regenerative function in normal form would be straightforward, whereas for the complementary phase, it would be developed by considering a virtual instance of the function. However, the choice of best NNIG for a given function would be based upon literal count, cell count and DAG node count of the implementation at the technology independent stage. In case of a tie, the final decision would be made after extracting the physical design parameters. We have considered AIG representation for reduced disjunctive normal form and the best of OIG/AOG/AOIG for the minimized conjunctive normal forms. This is necessitated due to the nature of certain functions, such as Achilles- heel functions. NNIGs are found to exhibit 3.97% lesser node count compared to AIGs and OIG/AOG/AOIGs; consume 23.74% and 10.79% lesser library cells than AIGs and OIG/AOG/AOIGs for the various samples considered. We compare the power efficiency and delay improvement achieved by optimal NNIGs over minimal AIGs and OIG/AOG/AOIGs for various case studies. In comparison with functionally equivalent, irredundant and compact AIGs, NNIGs report mean savings in power and delay of 43.71% and 25.85% respectively, after technology mapping with a 0.35 micron TSMC CMOS process. For a comparison with OIG/AOG/AOIGs, NNIGs demonstrate average savings in power and delay by 47.51% and 24.83%. With respect to device count needed for implementation with static CMOS logic style, NNIGs utilize 37.85% and 33.95% lesser transistors than their AIG and OIG/AOG/AOIG counterparts.

Keywords: AND-Inverter Graph, OR-Inverter Graph, DirectedAcyclic Graph, Low power design, Delay optimization.

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Authors: P. Pistelok

Abstract:

The article presents the concept of an electromagnetic circuit generator with permanent magnets mounted on the surface rotor core designed for single phase work. Computation field-circuit model was shown. The spectrum of time course of voltages in the idle work was presented. The cross section with graphically presentation of magnetic induction in particular parts of electromagnetic circuits was presented. Distribution of magnetic induction at the rated load point for each phase was shown. The time course of voltages and currents for each phases for rated power were displayed. An analysis of laboratory results and measurement of load characteristics of the generator was discussed. The work deals with three electromagnetic circuits of generators with permanent magnet where output voltage characteristics versus rated power were expressed.

Keywords: Permanent magnet generator, permanent magnets, vibration, course of torque, single phase work, asymmetrical three phase work.

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Authors: C. Kalamani, V. Abishek Karthick, S. Anitha, K. Kavin Kumar

Abstract:

The fault tolerant system plays a crucial role in the critical applications which are being used in the present scenario. A fault may change the functionality of circuits. Aim of this paper is to design multiplier using fault tolerant hybrid full adder. Fault tolerant hybrid full adder is designed to check and repair any fault in the circuit using self-checking circuit and the self-repairing circuit. Further, the use of conventional logic circuits may result in more area, delay as well as power consumption. In order to reduce these parameters of the circuit, GDI (Gate Diffusion Input) techniques with less number of transistors are used compared to conventional full adder circuit. This reduces the area, delay and power consumption. The proposed method solves the major problems occurring in the most crucial and critical applications.

Keywords: Gate diffusion input, hybrid full adder, self-checking, fault tolerant.

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Authors: K. Sivasubramanian, K. B. Jayanthi

Abstract:

Floorplanning plays a vital role in the physical design process of Very Large Scale Integrated (VLSI) chips. It is an essential design step to estimate the chip area prior to the optimized placement of digital blocks and their interconnections. Since VLSI floorplanning is an NP-hard problem, many optimization techniques were adopted in the literature. In this work, a music-inspired Harmony Search (HS) algorithm is used for the fixed die outline constrained floorplanning, with the aim of reducing the total chip area. HS draws inspiration from the musical improvisation process of searching for a perfect state of harmony. Initially, B*-tree is used to generate the primary floorplan for the given rectangular hard modules and then HS algorithm is applied to obtain an optimal solution for the efficient floorplan. The experimental results of the HS algorithm are obtained for the MCNC benchmark circuits.

Keywords: Floor planning, harmony search, non-slicing floorplan, very large scale integrated circuits.

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Authors: Farhana Mohamad Yusop, Syafrudin Masri, Dahaman Ishak, Mohamad Kamarol

Abstract:

Electromagnetic forces on three-phase five-wire (3P5W) busbar system is investigated under three-phase short-circuits current. The conductor busbar placed in compact galvanized steel enclosure is in the rectangular shape. Transient analysis from Opera-2D is carried out to develop the model of three-phase short-circuits current in the system. The result of the simulation is compared with the calculation result, which is obtained by applying the theories of Biot Savart’s law and Laplace equation. Under this analytical approach, the moment of peak short-circuit current is taken into account. The effect upon geometrical arrangement of the conductor and the present of the steel enclosure are considered by the theory of image. The result depict that the electromagnetic force due to the transient short-circuit from simulation is agreed with the calculation.

Keywords: Busbar, electromagnetic force, short-circuit current, transient analysis.

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Authors: Hubert Klar

Abstract:

High double excitation of two-electron atoms has been investigated using hyperpherical coordinates within a modified adiabatic expansion technique. This modification creates a novel fictitious force leading to a spontaneous exchange symmetry breaking at high double excitation. The Pauli principle must therefore be regarded as approximation valid only at low excitation energy. Threshold electron scattering from high Rydberg states shows an unexpected time reversal symmetry breaking. At threshold for double escape we discover a broad (few eV) Cooper pair.

Keywords: Correlation, resonances, threshold ionization, Cooper pair.

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Authors: Muhibul Haque Bhuyan

Abstract:

Spintronic, also termed spin electronics or spin transport electronics, is a kind of new technology, which exploits the two fundamental degrees of freedom- spin-state and charge-state of electrons to enhance the operational speed for the data storage and transfer efficiency of the device. Thus, it seems an encouraging technology to combat most of the prevailing complications in orthodox electron-based devices. This novel technology possesses the capacity to mix the semiconductor microelectronics and magnetic devices’ functionalities into one integrated circuit. Traditional semiconductor microelectronic devices use only the electronic charge to process the information based on binary numbers, 0 and 1. Due to the incessant shrinking of the transistor size, we are reaching the final limit of 1 nm or so. At this stage, the fabrication and other device operational processes will become challenging as the quantum effect comes into play. In this situation, we should find an alternative future technology, and spintronic may be such technology to transfer and store information. This review article provides a detailed discussion of the spintronic technology: fundamentals, materials, devices, circuits, challenges, and current research trends. At first, the fundamentals of spintronics technology are discussed. Then types, properties, and other issues of the spintronic materials are presented. After that, fabrication and working principles, as well as application areas and advantages/disadvantages of spintronic devices and circuits, are explained. Finally, the current challenges, current research areas, and prospects of spintronic technology are highlighted. This is a new paradigm of electronic cum magnetic devices built on the charge and spin of the electrons. Modern engineering and technological advances in search of new materials for this technology give us hope that this would be a very optimistic technology in the upcoming days.

Keywords: Spintronic technology, spin, charge, magnetic devices, spintronic devices, spintronic materials.

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Authors: Jun Sung Go, Jong Kang Park, Jong Tae Kim

Abstract:

As semi-conductor manufacturing technology evolves; the single event transient problem becomes more significant issue. Single event transient has a critical impact on both combinational and sequential logic circuits, so it is important to evaluate the soft error tolerance of the circuits at the design stage. In this paper, we present a soft error detecting simulation using scan chain. The simulation model generates a single event transient randomly in the circuit, and detects the soft error during the execution of the test patterns. We verified this model by inserting a scan chain in an 8051 microprocessor using 65 nm CMOS technology. While the test patterns generated by ATPG program are passing through the scan chain, we insert a single event transient and detect the number of soft errors per sub-module. The experiments show that the soft error rates per cell area of the SFR module is 277% larger than other modules.

Keywords: Scan chain, single event transient, soft error, 8051 processor.

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Authors: Zia Abbas, Giuseppe Scotti, Mauro Olivieri

Abstract:

Current mode circuits like current conveyors are getting significant attention in current analog ICs design due to their higher band-width, greater linearity, larger dynamic range, simpler circuitry, lower power consumption and less chip area. The second generation current controlled conveyor (CCCII) has the advantage of electronic adjustability over the CCII i.e. in CCCII; adjustment of the X-terminal intrinsic resistance via a bias current is possible. The presented approach is based on the CMOS implementation of second generation positive (CCCII+), negative (CCCII-) and dual Output Current Controlled Conveyor (DOCCCII) and its application as Universal filter. All the circuits have been designed and simulated using 65nm CMOS technology model parameters on Cadence Virtuoso / Spectre using 1V supply voltage. Various simulations have been carried out to verify the linearity between output and input ports, range of operation frequency, etc. The outcomes show good agreement between expected and experimental results.

Keywords: CCCII+, CCCII-, DOCCCII, Electronic tunability, Universal filter

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Authors: S. Chauhan, T.P.K. Grewal, S.K. Aggarwal, V.K. Srivastava

Abstract:

Solution for the complete removal of carbon monoxide from the exhaust gases still poses a challenge to the researchers and this problem is still under development. Modeling for reduction of carbon monoxide is carried out using heterogeneous reaction using low cost non-noble metal based catalysts for the purpose of controlling emissions released to the atmosphere. A simple one-dimensional model was developed for the monolith using hopcalite catalyst. The converter is assumed to be an adiabatic monolith operating under warm-up conditions. The effect of inlet gas temperatures and catalyst loading on carbon monoxide reduction during cold start period in the converter is analysed.

Keywords: carbon monoxide, catalytic, modeling, monolith

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Authors: Stelian Petrescu, Adina Frunzâ, Camelia Petrescu

Abstract:

A method to determine experimentally the melting rate, rm, and the heat transfer coefficients, αv (W/(m3K)), at convective melting in a fixed bed of particles under adiabatic regime is established in this paper. The method lies in the determining of the melting rate by measuring the fixed bed height in time. Experimental values of rm, α and α v were determined using cylindrical particles of ice (d = 6.8 mm, h = 5.5 mm) and, as a melting agent, aqueous NaCl solution with a temperature of 283 K at different values of the liquid flow rate (11.63·10-6, 28.83·10-6, 38.83·10-6 m3/s). Our experimental results were compared with those existing in literature being noticed a good agreement for Re values higher than 50.

Keywords: Convective melting, fixed bed, packed bed, heat transfer, ice melting.

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Authors: Ahtesham Javaid, Costin S. Bildea

Abstract:

The design and plantwide control of an integrated plant where the endothermic 1,4-butanediol dehydrogenation and the exothermic furfural hydrogenation is simultaneously performed in a single reactor is studied. The reactions can be carried out in an adiabatic reactor using small hydrogen excess and with reduced parameter sensitivity. The plant is robust and flexible enough to allow different production rates of γ-butyrolactone and 2-methyl furan, keeping high product purities. Rigorous steady state and dynamic simulations performed in AspenPlus and AspenDynamics to support the conclusions.

Keywords: Dehydrogenation and hydrogenation, Reaction coupling, Design and control, Process integration.

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Authors: Jie Jin

Abstract:

In this paper, a new CMOS current-mode single input and multi-outputs (SIMO) universal filter and quadrature oscillator with a similar circuit are proposed. The circuits only consist of three Current differencing transconductance amplifiers (CDTA) and two grounded capacitors, which are resistorless, and they are suitable for monolithic integration. The universal filter uses minimum CDTAs and passive elements to realize SIMO type low-pass (LP), high-pass (HP), band-pass (BP) band-stop (BS) and all-pass (AP) filter functions simultaneously without any component matching conditions. The angular frequency (ω0) and the quality factor (Q) of the proposed filter can be electronically controlled and tuned orthogonal. By some modifications of the filter, a new current-mode four-phase quadrature oscillator (QO) can be obtained easily. The condition of oscillation (CO) and frequency of oscillation (FO) of the QO can be controlled electronically and independently through the bias current of the CDTAs, and it is suitable for variable frequency oscillator. Moreover, all the passive and active sensitivities of the circuits are low. SPICE simulation results are included to confirm the theory.

Keywords: Universal Filter, Quadrature Oscillator, Current mode, Current differencing transconductance amplifiers.

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Authors: Marko Popovic

Abstract:

There are three possible effects of Special Theory of Relativity (STR) on a thermodynamic system. Planck and Einstein looked upon this process as isobaric; on the other hand Ott saw it as an adiabatic process. However plenty of logical reasons show that the process is isotherm. Our phenomenological consideration demonstrates that the temperature is invariant with Lorenz transformation. In that case process is isotherm, so volume and pressure are Lorentz covariant. If the process is isotherm the Boyles law is Lorentz invariant. Also equilibrium constant and Gibbs energy, activation energy, enthalpy entropy and extent of the reaction became Lorentz invariant.

Keywords: STR, relativistic temperature transformation, Boyle'slaw, equilibrium constant, Gibbs energy.

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Authors: K. A. Sumitra Devi, N. P. Banashree, Annamma Abraham

Abstract:

Partitioning is a critical area of VLSI CAD. In order to build complex digital logic circuits its often essential to sub-divide multi -million transistor design into manageable Pieces. This paper looks at the various partitioning techniques aspects of VLSI CAD, targeted at various applications. We proposed an evolutionary time-series model and a statistical glitch prediction system using a neural network with selection of global feature by making use of clustering method model, for partitioning a circuit. For evolutionary time-series model, we made use of genetic, memetic & neuro-memetic techniques. Our work focused in use of clustering methods - K-means & EM methodology. A comparative study is provided for all techniques to solve the problem of circuit partitioning pertaining to VLSI design. The performance of all approaches is compared using benchmark data provided by MCNC standard cell placement benchmark net lists. Analysis of the investigational results proved that the Neuro-memetic model achieves greater performance then other model in recognizing sub-circuits with minimum amount of interconnections between them.

Keywords: VLSI, circuit partitioning, memetic algorithm, genetic algorithm.

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Authors: Padmanabhan Balasubramanian, C. Ardil

Abstract:

In this paper, we consider the problem of logic simplification for a special class of logic functions, namely complementary Boolean functions (CBF), targeting low power implementation using static CMOS logic style. The functions are uniquely characterized by the presence of terms, where for a canonical binary 2-tuple, D(mj) ∪ D(mk) = { } and therefore, we have | D(mj) ∪ D(mk) | = 0 [19]. Similarly, D(Mj) ∪ D(Mk) = { } and hence | D(Mj) ∪ D(Mk) | = 0. Here, 'mk' and 'Mk' represent a minterm and maxterm respectively. We compare the circuits minimized with our proposed method with those corresponding to factored Reed-Muller (f-RM) form, factored Pseudo Kronecker Reed-Muller (f-PKRM) form, and factored Generalized Reed-Muller (f-GRM) form. We have opted for algebraic factorization of the Reed-Muller (RM) form and its different variants, using the factorization rules of [1], as it is simple and requires much less CPU execution time compared to Boolean factorization operations. This technique has enabled us to greatly reduce the literal count as well as the gate count needed for such RM realizations, which are generally prone to consuming more cells and subsequently more power consumption. However, this leads to a drawback in terms of the design-for-test attribute associated with the various RM forms. Though we still preserve the definition of those forms viz. realizing such functionality with only select types of logic gates (AND gate and XOR gate), the structural integrity of the logic levels is not preserved. This would consequently alter the testability properties of such circuits i.e. it may increase/decrease/maintain the same number of test input vectors needed for their exhaustive testability, subsequently affecting their generalized test vector computation. We do not consider the issue of design-for-testability here, but, instead focus on the power consumption of the final logic implementation, after realization with a conventional CMOS process technology (0.35 micron TSMC process). The quality of the resulting circuits evaluated on the basis of an established cost metric viz., power consumption, demonstrate average savings by 26.79% for the samples considered in this work, besides reduction in number of gates and input literals by 39.66% and 12.98% respectively, in comparison with other factored RM forms.

Keywords: Reed-Muller forms, Logic function, Hammingdistance, Algebraic factorization, Low power design.

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