Search results for: Circuit Design

Authors: Harshavardhan Reddy, Balaji Subramanian

Abstract:

A systematic parametric study to find the optimum Bellmouth profile by relating geometric and performance parameters to satisfy a set of specifications is reported. A careful aerodynamic design of Bellmouth intake is critical to properly direct the flow with minimal losses and maximal flow uniformity into the honeycomb located inside the settling chamber of an indraft wind tunnel, thus improving the efficiency of the entire unit. Design charts for elliptically profiled Bellmouth's with two different contraction ratios (9 and 18) and three different test section speeds (25 m/s, 50 m/s, and 75 m/s) were presented. A significant performance improvement - especially in the coefficient of discharge and in the flow angularity and boundary layer thickness at the honeycomb inlet - was observed when an entry corner radius (r/D = 0.08) was added to the Bellmouth profile. The nonuniformity at the honeycomb inlet drops by about three times (~1% to 0.3%) when moving from square to regular octagonal cross-section. An octagonal cross-sectioned Bellmouth intake with L/d = 0.55, D/d = 1.625, and r/D = 0.08 met all the four target performance specifications and is proposed as the best choice for a low-speed wind tunnel.

Keywords: Bellmouth intake, low-speed wind tunnel, coefficient of discharge, nonuniformity, flow angularity, boundary layer thickness, CFD, aerodynamics.

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Authors: S. Jalaja, A. M. Vijaya Prakash

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Recursive combination of an algorithm based on Karatsuba multiplication is exploited to design a generalized transpose and parallel Finite Impulse Response (FIR) Filter. Mid-range Karatsuba multiplication and Carry Save adder based on Karatsuba multiplication reduce time complexity for higher order multiplication implemented up to n-bit. As a result, we design modified N-tap Transpose and Parallel Symmetric FIR Filter Structure using Karatsuba algorithm. The mathematical formulation of the FFA Filter is derived. The proposed architecture involves significantly less area delay product (APD) then the existing block implementation. By adopting retiming technique, hardware cost is reduced further. The filter architecture is designed by using 90 nm technology library and is implemented by using cadence EDA Tool. The synthesized result shows better performance for different word length and block size. The design achieves switching activity reduction and low power consumption by applying with and without retiming for different combination of the circuit. The proposed structure achieves more than a half of the power reduction by adopting with and without retiming techniques compared to the earlier design structure. As a proof of the concept for block size 16 and filter length 64 for CKA method, it achieves a 51% as well as 70% less power by applying retiming technique, and for CSA method it achieves a 57% as well as 77% less power by applying retiming technique compared to the previously proposed design.

Keywords: Carry save adder Karatsuba multiplication, mid-range Karatsuba multiplication, modified FFA, transposed filter, retiming.

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Authors: Djalal Eddine Khodja, Aissa Kheldoun

Abstract:

In this work we present the modelling of the induction machine, taking into consideration the stator defects of the induction machine. It is based on the theory of electromagnetic coupling of electrical circuits. In fact, for the modelling of stationary defects such as short circuit between turns in the same phase, we introduce only in the matrix the coefficients of resistance and inductance of stator and in the mutual inductance stator-rotor. These coefficients take account the number of turns in short-circuit deducted from the total number of turns in the same phase; in this way we obtain the number of useful turns. In addition, all these faults involved, will be used for the creation of the database that will be used to develop an automated system failures of the induction machine.

Keywords: Asynchronous machine, Indicatory Values Statorfaults, Multi-turns Model, Three-phases Model.

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Authors: Valeri A. Makarov, Ezequiel Del Rio, Manuel G. Bedia, Manuel G. Velarde, Werner Ebeling

Abstract:

We proposed the use of a Toda-Rayleigh ring as a central pattern generator (CPG) for controlling hexapodal robots. We show that the ring composed of six Toda-Rayleigh units coupled to the limb actuators reproduces the most common hexapodal gaits. We provide an electrical circuit implementation of the CPG and test our theoretical results obtaining fixed gaits. Then we propose a method of incorporation of the actuator (motor) dynamics in the CPG. With this approach we close the loop CPG – environment – CPG, thus obtaining a decentralized model for the leg control that does not require higher level intervention to the CPG during locomotion in a nonhomogeneous environments. The gaits generated by the novel CPG are not fixed, but adapt to the current robot bahvior.

Keywords: Central pattern generator, electrical circuit, hexapod robot

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Authors: Susmita Sahoo, Madhumanti Datta, Rajib Kar

Abstract:

Fast delay estimation methods, as opposed to simulation techniques, are needed for incremental performance driven layout synthesis. On-chip inductive effects are becoming predominant in deep submicron interconnects due to increasing clock speed and circuit complexity. Inductance causes noise in signal waveforms, which can adversely affect the performance of the circuit and signal integrity. Several approaches have been put forward which consider the inductance for on-chip interconnect modelling. But for even much higher frequency, of the order of few GHz, the shunt dielectric lossy component has become comparable to that of other electrical parameters for high speed VLSI design. In order to cope up with this effect, on-chip interconnect has to be modelled as distributed RLCG line. Elmore delay based methods, although efficient, cannot accurately estimate the delay for RLCG interconnect line. In this paper, an accurate analytical delay model has been derived, based on first and second moments of RLCG interconnection lines. The proposed model considers both the effect of inductance and conductance matrices. We have performed the simulation in 0.18μm technology node and an error of as low as less as 5% has been achieved with the proposed model when compared to SPICE. The importance of the conductance matrices in interconnect modelling has also been discussed and it is shown that if G is neglected for interconnect line modelling, then it will result an delay error of as high as 6% when compared to SPICE.

Keywords: Delay Modelling; On-Chip Interconnect; RLCGInterconnect; Ramp Input; Damping; VLSI

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Authors: Horng-Yuan Wu, Chin-Yuan Hsu, Tsair-Fwu Lee

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A novel three-phase active power filter (APF) circuit with photovoltaic (PV) system to improve the quality of service and to reduce the capacity of energy storage capacitor is presented. The energy balance concept and sampling technique were used to simplify the calculation algorithm for the required utility source current and to control the voltage of the energy storage capacitor. The feasibility was verified by using the Pspice simulations and experiments. When the APF mode was used during non-operational period, not only the utilization rate, power factor and power quality could be improved, but also the capacity of energy storage capacitor could sparing. As the results, the advantages of the APF circuit are simplicity of control circuits, low cost, and good transient response.

Keywords: active power filter, sampling, energy-storagecapacitor, harmonic current, energy balance.

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Authors: Marcin Sowa

Abstract:

The paper discusses the subinterval-based numerical method for fractional derivative computations. It is now referred to by its acronym – SubIval. The basis of the method is briefly recalled. The ability of the method to be applied in time stepping solvers is discussed. The possibility of implementing a time step size adaptive solver is also mentioned. The solver is tested on a transient circuit example. In order to display the accuracy of the solver – the results have been compared with those obtained by means of a semi-analytical method called gcdAlpha. The time step size adaptive solver applying SubIval has been proven to be very accurate as the results are very close to the referential solution. The solver is currently able to solve FDE (fractional differential equations) with various derivative orders for each equation and any type of source time functions.

Keywords: Numerical method, SubIval, fractional calculus, numerical solver, circuit analysis.

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Authors: Siavash Heydarzadeh, Massoud Dousti

Abstract:

A active inductor in CMOS techonology with a supply voltage of 1.8V is presented. The value of the inductance L can be in the range from 0.12nH to 0.25nH in high frequency(HF). The proposed active inductor is designed in TSMC 0.18-um CMOS technology. The power dissipation of this inductor can retain constant at all operating frequency bands and consume around 20mW from 1.8V power supply. Inductors designed by integrated circuit occupy much smaller area, for this reason,attracted researchers attention for more than decade. In this design we used Advanced Designed System (ADS) for simulating cicuit.

Keywords: CMOS active inductor , 0.18um CMOS technology , ADS

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Authors: Igor Luiz Bernardes de Moura, Luan Carlos de Sena Monteiro Ozelim, Fabiano Araujo Soares

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The development of an low cost acquisition system of S-EMG signals which are reliable, comfortable for the user and with high mobility shows to be a relevant proposition in modern biomedical engineering scenario. In the study, the sampling capacity of the Arduino microcontroller Atmel Atmega328 with an A / D converter with 10-bit resolution and its reconstructing capability of a signal of surface electromyography is analyzed. An electronic circuit to capture the signal through two differential channels was designed, signals from Biceps Brachialis of a healthy man of 21 years was acquired to test the system prototype. ARV, MDF, MNF and RMS estimators were used to compare de acquired signals with physiological values. The Arduino was configured with a sampling frequency of 1.5kHz for each channel, and the tests with the circuit designed offered a SNR of 20.57dB.

Keywords: Eletromyography, Arduino, Low-Cost, Atmel Atmega328 microcontroller.

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Authors: A. Guechi, M. Chegaar

Abstract:

This study investigates how AlGaAs/GaAs thin film solar cells perform under varying global solar spectrum due to the changes of environmental parameters such as the air mass and the atmospheric turbidity. The solar irradiance striking the solar cell is simulated using the spectral irradiance model SMARTS2 (Simple Model of the Atmospheric Radiative Transfer of Sunshine) for clear skies on the site of Setif (Algeria). The results show a reduction in the short circuit current due to increasing atmospheric turbidity, it is 63.09% under global radiation. However increasing air mass leads to a reduction in the short circuit current of 81.73%. The efficiency decreases with increasing atmospheric turbidity and air mass.

Keywords: AlGaAs/GaAs, Solar Cells, Environmental parameters, Spectral Variation, SMARTS.

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Authors: Guo-Ming Sung, Naga Raju Naik R.

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Paper presents a low power, high speed, sense-amplifier based flip-flop (SAFF). The flip-flop’s power con-sumption and delay are greatly reduced by employing a new conditionally precharge sense-amplifier stage and a single-ended latch stage. Glitch-free and contention-free latch operation is achieved by using a conditional cut-off strategy. The design uses fewer transistors, has a lower clock load, and has a simple structure, all of which contribute to a near-zero setup time. When compared to previous flip-flop structures proposed for similar input/output conditions, this design’s performance and overall PDP have improved. The post layout simulation of the circuit uses 2.91µW of power and has a delay of 65.82 ps. Overall, the power-delay product has seen some enhancements. Cadence Virtuoso Designing tool with CMOS 90nm technology are used for all designs.

Keywords: high-speed, low-power, flip-flop, sense-amplifier

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Authors: P. Chaipanya, R. Keawchai, W. Sombatsanongkhun, S. Jantaramporn

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To manage the demand of wireless communication that has been dramatically increased, switched beam antenna in smart antenna system is focused. Implementation of switched beam antennas at mobile terminals such as notebook or mobile handset is a preferable choice to increase the performance of the wireless communication systems. This paper proposes the low complexity switched beam antenna using single element of antenna which is suitable to implement at mobile terminal. Main beam direction is switched by changing the positions of short circuit on the radiating patch. There are four cases of switching that provide four different directions of main beam. Moreover, the performance in terms of Signal to Interference Ratio when utilizing the proposed antenna is compared with the one using omni-directional antenna to confirm the performance improvable.

Keywords: Switched beam, shorted circuit, single element, signal to interference ratio.

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Authors: Kah-Hyong Chang, Xin Liu, Jia Hao Cheong, Saisundar Sankaranarayanan, Dexing Pang, Hongzhao Zheng

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A digital baseband Application-Specific Integrated Circuit (ASIC) (yclic Redundancy Checkis developed for a microchip transponder to transmit signals and temperature levels from biomedical monitoring devices. The transmission protocol is adapted from the ISO/IEC 11784/85 standard. The module has a decimation filter that employs only a single adder-subtractor in its datapath. The filtered output is coded with cyclic redundancy check and transmitted through backscattering Load Shift Keying (LSK) modulation to a reader. Fabricated using the 0.18-μm CMOS technology, the module occupies 0.116 mm² in chip area (digital baseband: 0.060 mm², decimation filter: 0.056 mm²), and consumes a total of less than 0.9 μW of power (digital baseband: 0.75 μW, decimation filter: 0.14 μW).

Keywords: Biomedical sensor, decimation filter, Radio Frequency Integrated Circuit (RFIC) baseband, temperature sensor.

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Authors: L. Tani, N. El Ouzzani

Abstract:

Crosstalk among interconnects and printed-circuit board (PCB) traces is a major limiting factor of signal quality in highspeed digital and communication equipments especially when fast data buses are involved. Such a bus is considered as a planar multiconductor transmission line. This paper will demonstrate how the finite difference time domain (FDTD) method provides an exact solution of the transmission-line equations to analyze the near end and the far end crosstalk. In addition, this study makes it possible to analyze the rise time effect on the near and far end voltages of the victim conductor. The paper also discusses a statistical analysis, based upon a set of several simulations. Such analysis leads to a better understanding of the phenomenon and yields useful information.

Keywords: Multiconductor transmission line, Crosstalk, Finite difference time domain (FDTD), printed-circuit board (PCB), Rise time, Statistical analysis.

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Authors: Eduardo N. Velloso, Fernando M. N. Dantas, Luciano S. Barros

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A common complaint from power system analysis students lies in the overly complex tools they need to learn and use just to simulate very basic systems or just to check the answers to power system calculations. The most basic power system studies are power-flow solutions and short-circuit calculations. This paper presents a simple tool with an intuitive interface to perform both these studies and assess its performance in comparison with existent commercial solutions. With this in mind, Elegant is a pure Python software tool for learning power system analysis developed for undergraduate and graduate students. It solves the power-flow problem by iterative numerical methods and calculates bolted short-circuit fault currents by modeling the network in the domain of symmetrical components. Elegant can be used with a user-friendly Graphical User Interface (GUI) and automatically generates human-readable reports of the simulation results. The tool is exemplified using a typical Brazilian regional system with 18 buses. This study performs a comparative experiment with 1 undergraduate and 4 graduate students who attempted the same problem using both Elegant and a commercial tool. It was found that Elegant significantly reduces the time and labor involved in basic power system simulations while still providing some insights into real power system designs.

Keywords: Free- and open-source software, power-flow, power system analysis, Python, short-circuit.

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Authors: Swanti Satsangi, Ashish Gulati, Prem Kumar Kalra, C. Patvardhan

Abstract:

Due to the non- intuitive nature of Quantum algorithms, it becomes difficult for a classically trained person to efficiently construct new ones. So rather than designing new algorithms manually, lately, Genetic algorithms (GA) are being implemented for this purpose. GA is a technique to automatically solve a problem using principles of Darwinian evolution. This has been implemented to explore the possibility of evolving an n-qubit circuit when the circuit matrix has been provided using a set of single, two and three qubit gates. Using a variable length population and universal stochastic selection procedure, a number of possible solution circuits, with different number of gates can be obtained for the same input matrix during different runs of GA. The given algorithm has also been successfully implemented to obtain two and three qubit Boolean circuits using Quantum gates. The results demonstrate the effectiveness of the GA procedure even when the search spaces are large.

Keywords: Ancillas, Boolean functions, Genetic algorithm, Oracles, Quantum circuits, Scratch bit

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Authors: A. Hayati Soloot, A. Gholami, E. Agheb, A. Ghorbandaeipour, P. Mokhtari

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The two significant overvoltages in power system, switching overvoltage and lightning overvoltage, are investigated in this paper. Firstly, the effect of various power system parameters on Line Energization overvoltages is evaluated by simulation in ATP. The dominant parameters include line parameters; short-circuit impedance and circuit breaker parameters. Solutions to reduce switching overvoltages are reviewed and controlled closing using switchsync controllers is proposed as proper method. This paper also investigates lightning overvoltages in the overhead-cable transition. Simulations are performed in PSCAD/EMTDC. Surge arresters are applied in both ends of cable to fulfill the insulation coordination. The maximum amplitude of overvoltages inside the cable is surveyed which should be of great concerns in insulation coordination studies.

Keywords: Switching Overvoltage, Lightning Overvoltage, Insulation Coordination, ATP, PSCAD/EMTDC.

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Authors: D. Gouwanda, S. M. N. A. Senanayake

Abstract:

This paper presents a real time force sensing instrument that is designed for human gait analysis purposes. It is capable of recording and monitoring ground reaction forces exerted by human foot during various activities such as walking, running and jumping in real time. In overall, force sensing mat mainly consists of three elements: the force sensing mat, signal conditioning circuit and data acquisition device. Force sensing mat is the mat that contains an array of force sensing elements. To control and process the incoming signal from the force sensing mat, Force-Logger and Force-Reloader are developed using National Instrument Labview. This paper describes the architecture of the force sensing mat, signal conditioning circuit and the real time streaming of the incoming data from the force sensing mat. Additionally, a preliminary experiment dataset is presented in this paper.

Keywords: Force platform, force sensing resistor, human gait analysis.

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Authors: Mohd. Hasan, Ajmal Kafeel, S. D. Pable

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Ultra-low-power (ULP) circuits have received widespread attention due to the rapid growth of biomedical applications and Battery-less Electronics. Subthreshold region of transistor operation is used in ULP circuits. Major research challenge in the subthreshold operating region is to extract the ULP benefits with minimal degradation in speed and robustness. Process, Voltage and Temperature (PVT) variations significantly affect the performance of subthreshold circuits. Designed performance parameters of ULP circuits may vary largely due to temperature variations. Hence, this paper investigates the effect of temperature variation on device and circuit performance parameters at different biasing voltages in the subthreshold region. Simulation results clearly demonstrate that in deep subthreshold and near threshold voltage regions, performance parameters are significantly affected whereas in moderate subthreshold region, subthreshold circuits are more immune to temperature variations. This establishes that moderate subthreshold region is ideal for temperature immune circuits.

Keywords: Subthreshold, temperature variations, ultralow power.

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Authors: Arup K. George, Wai Pan Chan, Zhi Hui Kong, Minkyu Je

Abstract:

This paper describes a low-power second-order filter for a continuous-time chopper stabilized capacitive sensor interface, integrated with a fully differential post-CMOS surface-micromachined MEMS pressure sensor. The circuit uses a single-ended folded-cascode operational amplifier and two GM-C filters connected in cascade. The circuit is realized in a 0.18 μm CMOS process and offers differential to single-ended conversion. The novelty of the scheme is the cascade of two GM-C filters to achieve a second-order filter while minimizing power dissipation. The simulated filter cutoff frequency is 1.14 kHz at common-mode voltage 1.65 V, operating from a 3.3 V supply while dissipating 172μW of power. The filter achieves an operating range of 1V for an output load of 1MOhm and 10pF.

Keywords: Chopper Stabilization, MEMS, Pressure Sensors, Low Pass Filter

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Authors: Zin Maw Tun, Tun Lin Naing

Abstract:

This paper presents the two loop proportional integral (PI) controller for speed control of permanent magnet DC motor (PMDC) motor drive with H-bridge DC chopper. PMDC motors are widely used in many applications because of having a good performance and it is easy to apply the speed control. The speed can be adjusted by using armature voltage control as it had only the armature circuit. H-bridge DC chopper circuit is used to obtain the desired speed in any direction. In this system, the two loop PI controller is designed by using pole-zero cancellation method. The speed and current controller gains are considered depending on the sampling frequency of the microcontroller. An Arduino IO package is used to implement the control algorithm. Both simulation and experimental results are presented to prove the correctness of the mathematical model.

Keywords: Arduino IO package, double loop PI controller, H-bridge DC chopper, low cost hardware, PMDC motor.

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Authors: Deepthi P.P., P.S. Sathidevi

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Proposal for a secure stream cipher based on Linear Feedback Shift Registers (LFSR) is presented here. In this method, shift register structure used for polynomial modular division is combined with LFSR keystream generator to yield a new keystream generator with much higher periodicity. Security is brought into this structure by using the Boolean function to combine state bits of the LFSR keystream generator and taking the output through the Boolean function. This introduces non-linearity and security into the structure in a way similar to the Non-linear filter generator. The security and throughput of the suggested stream cipher is found to be much greater than the known LFSR based structures for the same key length.

Keywords: Linear Feedback Shift Register, Stream Cipher, Filter generator, Keystream generator, Modular division circuit

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Authors: Joo-Han Kim, Jung-Moo Seo, Ha Gyeong Sung, Se Hyun Rhyu

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This study presents a blower for air management system of fuel cell modules. A blower is composed of BLDC motor and impeller. Magnetic equivalent circuit model and finite element analysis are used to design the motor, and an improved structure is considered to reduce a mechanical loss induced from bearing units. Finally, air blower system combined with the motor and an impeller is manufactured and output properties, such as an air pressure and an amount of flowing air, are measured. Through the experimental results, a validity of the simulated one is confirmed.

Keywords: Fuel cell modules, BLDC motor, Impeller, Air management

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Authors: Emanuele Stomeo, Tatiana Kalganova, Cyrille Lambert

Abstract:

The evolution of logic circuits, which falls under the heading of evolvable hardware, is carried out by evolutionary algorithms. These algorithms are able to automatically configure reconfigurable devices. One of main difficulties in developing evolvable hardware with the ability to design functional electrical circuits is to choose the most favourable EA features such as fitness function, chromosome representations, population size, genetic operators and individual selection. Until now several researchers from the evolvable hardware community have used and tuned these parameters and various rules on how to select the value of a particular parameter have been proposed. However, to date, no one has presented a study regarding the size of the chromosome representation (circuit layout) to be used as a platform for the evolution in order to increase the evolvability, reduce the number of generations and optimize the digital logic circuits through reducing the number of logic gates. In this paper this topic has been thoroughly investigated and the optimal parameters for these EA features have been proposed. The evolution of logic circuits has been carried out by an extrinsic evolvable hardware system which uses (1+λ) evolution strategy as the core of the evolution.

Keywords: Evolvable hardware, genotype size, computational intelligence, design of logic circuits.

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Authors: Niloofar Khedri, Masoud Rahgozar, MahmoudReza Hashemi

Abstract:

Design patterns describe good solutions to common and reoccurring problems in program design. Applying design patterns in software design and implementation have significant effects on software quality metrics such as flexibility, usability, reusability, scalability and robustness. There is no standard rule for using design patterns. There are some situations that a pattern is applied for a specific problem and this pattern uses another pattern. In this paper, we study the effect of using chain of patterns on software quality metrics.

Keywords: Design Patterns, Design patterns' Relationship, Software quality Metrics, Software Engineering.

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Authors: Ö. Şenyiğit, A. Çolak

Abstract:

It is of great importance for an architectural student to know the parameters through which he/she can conduct his/her design and makes his/her design effective in architectural education. Therefore; an empirical application study was carried out through the designing activity using the emulation model to support the design and design approaches of architectural students. During the investigation period, studies were done on the basic design elements and principles of the fall semester, and the emulation model, one of the designing methods that constitute the subject of the study, was fictionalized as three phased “recognition-interpretation-application”. As a result of the study, it was observed that when students were given a key method during the design process, their awareness increased and their aspects improved as well.

Keywords: Basic design, design education, design methods, emulation.

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Authors: D. Krishnaveni, M. Geetha Priya

Abstract:

Application of reversible logic in integrated circuits results in the improved optimization of power consumption. This technology can be put into use in a variety of low power applications such as quantum computing, optical computing, nano-technology, and Complementary Metal Oxide Semiconductor (CMOS) Very Large Scale Integrated (VLSI) design etc. Logic gates are the basic building blocks in the design of any logic network and thus integrated circuits. In this paper, reversible Dual Key Gate (DKG) and Dual key Gate Pair (DKGP) gates that work singly as full adder/full subtractor are used to realize the basic building blocks of logic circuits. Reversible full adder/subtractor and parallel adder/ subtractor are designed using other reversible gates available in the literature and compared with that of DKG & DKGP gates. Efficient performance of reversible logic circuits relies on the optimization of the key parameters viz number of constant inputs, garbage outputs and number of reversible gates. The full adder/subtractor and parallel adder/subtractor design with reversible DKGP and DKG gates results in least number of constant inputs, garbage outputs, and number of reversible gates compared to the other designs. Thus, this paper provides a threshold to build more complex arithmetic systems using these reversible logic gates, leading to the enhanced performance of computing systems.

Keywords: Low power CMOS, quantum computing, reversible logic gates, full adder, full subtractor, parallel adder/subtractor, basic gates, universal gates.

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Authors: R. Damaševičius

Abstract:

System-level design based on high-level abstractions is becoming increasingly important in hardware and embedded system design. This paper analyzes meta-design techniques oriented at developing meta-programs and meta-models for well-understood domains. Meta-design techniques include meta-programming and meta-modeling. At the programming level of design process, metadesign means developing generic components that are usable in a wider context of application than original domain components. At the modeling level, meta-design means developing design patterns that describe general solutions to the common recurring design problems, and meta-models that describe the relationship between different types of design models and abstractions. The paper describes and evaluates the implementation of meta-design in hardware design domain using object-oriented and meta-programming techniques. The presented ideas are illustrated with a case study.

Keywords: Design patterns, meta-design, meta-modeling, metaprogramming.

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Authors: G.Ramana Murthy, C.Senthilpari, P.Velrajkumar, Lim Tien Sze

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The proposed multiplexer-based novel 1-bit full adder cell is schematized by using DSCH2 and its layout is generated by using microwind VLSI CAD tool. The adder cell layout interconnect analysis is performed by using BSIM4 layout analyzer. The adder circuit is compared with other six existing adder circuits for parametric analysis. The proposed adder cell gives better performance than the other existing six adder circuits in terms of power, propagation delay and PDP. The proposed adder circuit is further analyzed for interconnect analysis, which gives better performance than other adder circuits in terms of layout thickness, width and height.

Keywords: Full Adder, Interconnect Analysis, Low-Power, Multiplexer, Propagation Delay, Parametric Analysis.

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Authors: Emanuele Stomeo, Tatiana Kalganova, Cyrille Lambert

Abstract:

Evolvable hardware (EHW) is a developing field that applies evolutionary algorithm (EA) to automatically design circuits, antennas, robot controllers etc. A lot of research has been done in this area and several different EAs have been introduced to tackle numerous problems, as scalability, evolvability etc. However every time a specific EA is chosen for solving a particular task, all its components, such as population size, initialization, selection mechanism, mutation rate, and genetic operators, should be selected in order to achieve the best results. In the last three decade the selection of the right parameters for the EA-s components for solving different “test-problems" has been investigated. In this paper the behaviour of mutation rate for designing logic circuits, which has not been done before, has been deeply analyzed. The mutation rate for an EHW system modifies the number of inputs of each logic gates, the functionality (for example from AND to NOR) and the connectivity between logic gates. The behaviour of the mutation has been analyzed based on the number of generations, genotype redundancy and number of logic gates for the evolved circuits. The experimental results found provide the behaviour of the mutation rate during evolution for the design and optimization of simple logic circuits. The experimental results propose the best mutation rate to be used for designing combinational logic circuits. The research presented is particular important for those who would like to implement a dynamic mutation rate inside the evolutionary algorithm for evolving digital circuits. The researches on the mutation rate during the last 40 years are also summarized.

Keywords: Design of logic circuit, evolutionary computation, evolvable hardware, mutation rate.

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