Search results for: Biological clock
Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 545

Search results for: Biological clock

515 FPGA Implementation of the BB84 Protocol

Authors: Jaouadi Ikram, Machhout Mohsen

Abstract:

The development of a quantum key distribution (QKD) system on a field-programmable gate array (FPGA) platform is the subject of this paper. A quantum cryptographic protocol is designed based on the properties of quantum information and the characteristics of FPGAs. The proposed protocol performs key extraction, reconciliation, error correction, and privacy amplification tasks to generate a perfectly secret final key. We modeled the presence of the spy in our system with a strategy to reveal some of the exchanged information without being noticed. Using an FPGA card with a 100 MHz clock frequency, we have demonstrated the evolution of the error rate as well as the amounts of mutual information (between the two interlocutors and that of the spy) passing from one step to another in the key generation process.

Keywords: QKD, BB84, protocol, cryptography, FPGA, key, security, communication.

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514 Real-Time Digital Oscilloscope Implementation in 90nm CMOS Technology FPGA

Authors: Nasir Mehmood, Jens Ogniewski, Vinodh Ravinath

Abstract:

This paper describes the design of a real-time audiorange digital oscilloscope and its implementation in 90nm CMOS FPGA platform. The design consists of sample and hold circuits, A/D conversion, audio and video processing, on-chip RAM, clock generation and control logic. The design of internal blocks and modules in 90nm devices in an FPGA is elaborated. Also the key features and their implementation algorithms are presented. Finally, the timing waveforms and simulation results are put forward.

Keywords: CMOS, VLSI, Oscilloscope, Field Programmable Gate Array (FPGA), VHDL, Video Graphics Array (VGA)

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513 Complementary Energy Path Adiabatic Logic based Full Adder Circuit

Authors: Shipra Upadhyay , R. K. Nagaria, R. A. Mishra

Abstract:

In this paper, we present the design and experimental evaluation of complementary energy path adiabatic logic (CEPAL) based 1 bit full adder circuit. A simulative investigation on the proposed full adder has been done using VIRTUOSO SPECTRE simulator of cadence in 0.18μm UMC technology and its performance has been compared with the conventional CMOS full adder circuit. The CEPAL based full adder circuit exhibits the energy saving of 70% to the conventional CMOS full adder circuit, at 100 MHz frequency and 1.8V operating voltage.

Keywords: Adiabatic, CEPAL, full adder, power clock

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512 A Reversible CMOS AD / DA Converter Implemented with Pseudo Floating-Gate

Authors: Omid Mirmotahari, Yngvar Berg, Ahmad Habibizad Navin

Abstract:

Reversible logic is becoming more and more prominent as the technology sets higher demands on heat, power, scaling and stability. Reversible gates are able at any time to "undo" the current step or function. Multiple-valued logic has the advantage of transporting and evaluating higher bits each clock cycle than binary. Moreover, we demonstrate in this paper, combining these disciplines we can construct powerful multiple-valued reversible logic structures. In this paper a reversible block implemented by pseudo floatinggate can perform AD-function and a DA-function as its reverse application.

Keywords: Reversible logic, bi-directional, Pseudo floating-gate(PFG), multiple-valued logic (MVL).

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511 Bias Stability of a-IGZO TFT and a new Shift-Register Design Suitable for a-IGZO TFT

Authors: Young Wook Lee, Sun-Jae Kim, Soo-Yeon Lee, Moon-Kyu Song, Woo-Geun Lee Min-Koo Han

Abstract:

We have fabricated a-IGZO TFT and investigated the stability under positive DC and AC bias stress. The threshold voltage of a-IGZO TFT shifts positively under those biases, and that reduces on-current. For this reason, conventional shift-register circuit employing TFTs which stressed by positive bias will be unstable, may do not work properly. We have designed a new 6-transistor shift-register, which has less transistors than prior circuits. The TFTs of the proposed shift-register are not suffering from positive DC or AC stress, mainly kept unbiased. Despite the compact design, the stable output signal was verified through the SPICE simulation even under RC delay of clock signal.

Keywords: Indium Gallium Zinc Oxide (IGZO), Thin FilmTransistor (TFT), shift-register

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510 Asynchronous Sequential Machines with Fault Detectors

Authors: Seong Woo Kwak, Jung-Min Yang

Abstract:

A strategy of fault diagnosis and tolerance for asynchronous sequential machines is discussed in this paper. With no synchronizing clock, it is difficult to diagnose an occurrence of permanent or stuck-in faults in the operation of asynchronous machines. In this paper, we present a fault detector comprised of a timer and a set of static functions to determine the occurrence of faults. In order to realize immediate fault tolerance, corrective control theory is applied to designing a dynamic feedback controller. Existence conditions for an appropriate controller and its construction algorithm are presented in terms of reachability of the machine and the feature of fault occurrences.

Keywords: Asynchronous sequential machines, corrective control, fault diagnosis and tolerance, fault detector.

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509 Biological Data Integration using SOA

Authors: Noura Meshaan Al-Otaibi, Amin Yousef Noaman

Abstract:

Nowadays scientific data is inevitably digital and stored in a wide variety of formats in heterogeneous systems. Scientists need to access an integrated view of remote or local heterogeneous data sources with advanced data accessing, analyzing, and visualization tools. This research suggests the use of Service Oriented Architecture (SOA) to integrate biological data from different data sources. This work shows SOA will solve the problems that facing integration process and if the biologist scientists can access the biological data in easier way. There are several methods to implement SOA but web service is the most popular method. The Microsoft .Net Framework used to implement proposed architecture.

Keywords: Bioinformatics, Biological data, Data Integration, SOA and Web Services.

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508 Synchronization Technique for Random Switching Frequency Pulse-Width Modulation

Authors: Apinan Aurasopon, Worawat Sa-ngiavibool

Abstract:

This paper proposes a synchronized random switching frequency pulse width modulation (SRSFPWM). In this technique, the clock signal is used to control the random noise frequency which is produced by the feedback voltage of a hysteresis circuit. These make the triangular carrier frequency equaling to the random noise frequency in each switching period with the symmetrical positive and negative slopes of triangular carrier. Therefore, there is no error voltage in PWM signal. The PSpice simulated results shown the proposed technique improved the performance in case of low frequency harmonics of PWM signal comparing with conventional random switching frequency PWM.

Keywords: Random switching frequency pulse - width modulation.

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507 Treatment of Chrome Tannery Wastewater by Biological Process - A Mini Review

Authors: Supriyo Goswami, Debabrata Mazumder

Abstract:

Chrome tannery wastewater causes serious environmental hazard due to its high pollution potential. As a result, rigorous treatment is necessary for abatement of pollution from this type of wastewater. There are many research studies on chrome tannery wastewater treatment in the field of physical, chemical, and biological methods. In general, biological treatment process is found ineffective for direct application because of adverse effects by toxic chromium, sulphide, chloride etc. However, biological methods were employed mainly for a few sub processes generating significant amount of organic matter and without chromium, chlorides etc. In this context the present paper reviews the characteristics feature and pollution potential of wastewater generated from chrome tannery units and treatment of the same. The different biological processes used earlier and their chronological development for treatment of the chrome tannery wastewater are thoroughly reviewed in this paper. In this regard, the scope of hybrid bioreactor - an advanced technology option has also been explored, as this kind of treatment is well suited for the wastewater having inhibitory substances. 

Keywords: Composite tannery wastewater, biological treatment, Hybrid bioreactor, Organic removal

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506 The Performance of the Character-Access on the Checking Phase in String Searching Algorithms

Authors: Mahmoud M. Mhashi

Abstract:

A new algorithm called Character-Comparison to Character-Access (CCCA) is developed to test the effect of both: 1) converting character-comparison and number-comparison into character-access and 2) the starting point of checking on the performance of the checking operation in string searching. An experiment is performed; the results are compared with five algorithms, namely, Naive, BM, Inf_Suf_Pref, Raita, and Circle. With the CCCA algorithm, the results suggest that the evaluation criteria of the average number of comparisons are improved up to 74.0%. Furthermore, the results suggest that the clock time required by the other algorithms is improved in range from 28% to 68% by the new CCCA algorithm

Keywords: Pattern matching, string searching, charactercomparison, character-access, and checking.

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505 Perceptions of Greenhouse Vegetable Growers Regarding Use of Biological Control Practices: A Case Study in Jiroft County, Iran

Authors: Hossein Shabanali Fami, Omid Sharifi, Javad Ghasemi, Mahtab Pouratashi, Mona Sadat Moghadasian

Abstract:

The main purpose of this study was to investigate perception of greenhouse vegetable growers regarding use of biological control practices during the growing season. The statistical population of the study included greenhouse vegetable growers in Jiroft county (N=1862). A sample of 137 vegetable growers was selected, using random sampling method. Data were collected via a questionnaire. The validity of the instrument was obtained by the faculty members of the Department of Agricultural Development and Management in the University of Tehran. Cronbach’s alpha was applied to estimate the reliability which showed a high reliability for the instrument. Data was analyzed using SPSS/Windows 13.5. The results revealed that greenhouse vegetable growers had moderate level of perception regarding biological control practices. Levels of vegetable growers’ perceptions regarding biological control practices were different on the basis of their academic qualifications as well as educational level and job. In addition, the results indicated that about 54.1% of variations in vegetable growers’ perceptions could be explained by variables such as awareness of biological control practices, knowledge on pests, annual production and age.

Keywords: Greenhouse, biological control, biological agents, perception, vegetable grower.

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504 The Effect of Application of Biological Phosphate Fertilizer (Fertile 2) and Triple Super Phosphate Chemical Fertilizers on Some Morphological Traits of Corn (SC704)

Authors: M. Mojaddam, M. Araei, T. Saki Nejad, M. Soltani Howyzeh

Abstract:

In order to study the effect of different levels of triple super phosphate chemical fertilizer and biological phosphate fertilizer (fertile 2) on some morphological traits of corn this research was carried out in Ahvaz in 2002 as a factorial experiment in randomized complete block design with 4 replications). The experiment included two factors: first, biological phosphate fertilizer (fertile 2) at three levels of 0, 100, 200 g/ha; second, triple super phosphate chemical fertilizer at three levels of 0, 60, 90 kg/ha of pure phosphorus (P2O5). The obtained results indicated that fertilizer treatments had a significant effect on some morphological traits at 1% probability level. In this regard, P2B2 treatment (100 g/ha biological phosphate fertilizer (fertile 2) and 60 kg/ha triple super phosphate fertilizer) had the greatest plant height, stem diameter, number of leaves and ear length. It seems that in Ahvaz weather conditions, decrease of consumption of triple superphosphate chemical fertilizer to less than a half along with the consumption of biological phosphate fertilizer (fertile 2) is highly important in order to achieve optimal results. Therefore, it can be concluded that biological fertilizers can be used as a suitable substitute for some of the chemical fertilizers in sustainable agricultural systems.

Keywords: Biological phosphate fertilizer, corn (SC704), morphological, triple super phosphate.

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503 Biological Soil Conservation Planning by Spatial Multi-Criteria Evaluation Techniques (Case Study: Bonkuh Watershed in Iran)

Authors: Ali Akbar Jamali

Abstract:

This paper discusses site selection process for biological soil conservation planning. It was supported by a valuefocused approach and spatial multi-criteria evaluation techniques. A first set of spatial criteria was used to design a number of potential sites. Next, a new set of spatial and non-spatial criteria was employed, including the natural factors and the financial costs, together with the degree of suitability for the Bonkuh watershed to biological soil conservation planning and to recommend the most acceptable program. The whole process was facilitated by a new software tool that supports spatial multiple criteria evaluation, or SMCE in GIS software (ILWIS). The application of this tool, combined with a continual feedback by the public attentions, has provided an effective methodology to solve complex decisional problem in biological soil conservation planning.

Keywords: GIS, Biological soil conservation planning, Spatial multi-criteria evaluation, Iran

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502 Fast and Efficient On-Chip Interconnection Modeling for High Speed VLSI Systems

Authors: A.R. Aswatha, T. Basavaraju, S. Sandeep Kumar

Abstract:

Timing driven physical design, synthesis, and optimization tools need efficient closed-form delay models for estimating the delay associated with each net in an integrated circuit (IC) design. The total number of nets in a modern IC design has increased dramatically and exceeded millions. Therefore efficient modeling of interconnection is needed for high speed IC-s. This paper presents closed–form expressions for RC and RLC interconnection trees in current mode signaling, which can be implemented in VLSI design tool. These analytical model expressions can be used for accurate calculation of delay after the design clock tree has been laid out and the design is fully routed. Evaluation of these analytical models is several orders of magnitude faster than simulation using SPICE.

Keywords: IC design, RC/RLC Interconnection, VLSI Systems.

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501 The Negative Effect of Traditional Loops Style on the Performance of Algorithms

Authors: Mahmoud Moh'd Mhashi

Abstract:

A new algorithm called Character-Comparison to Character-Access (CCCA) is developed to test the effect of both: 1) converting character-comparison and number-comparison into character-access and 2) the starting point of checking on the performance of the checking operation in string searching. An experiment is performed using both English text and DNA text with different sizes. The results are compared with five algorithms, namely, Naive, BM, Inf_Suf_Pref, Raita, and Cycle. With the CCCA algorithm, the results suggest that the evaluation criteria of the average number of total comparisons are improved up to 35%. Furthermore, the results suggest that the clock time required by the other algorithms is improved in range from 22.13% to 42.33% by the new CCCA algorithm.

Keywords: Pattern matching, string searching, charactercomparison, character-access, text type, and checking

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500 Aggressive Interactions in Hospital Emergency Units

Authors: C. Blatier, M. El Methni, F. Carpentier, S. Abdellaoui, C. Kock, M. Maillard

Abstract:

International literature emphasizes on the concern regarding the phenomenon of aggression in hospital. This paper focuses on the reality of aggressive interactions reigning within an emergency triage involving three chaps of protagonists: the professionals, the patients and their carers. The data collection was made from a grid of observation, in which the various variables exposed in the literature were integrated. They observations took place around the clock, for three weeks, at the rate of one week a month. In this research 331 aggressive interactions have been listed and analyzed by means of the software SPSS. This research is one of the very few continuous observation surveys in the literature. It shows the various human factors at play in the emergence of aggressive interaction. The data may be used both for taking steps in primary prevention, thanks to the analysis of interaction modes, and in secondary prevention by integrating the useful results in situational prevention.

Keywords: Aggressive interaction, emergency unit, observational study.

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499 A Novel Digital Calibration Technique for Gain and Offset Mismatch in TIΣΔ ADCs

Authors: Ali Beydoun, Van-Tam Nguyen, Patrick Loumeau

Abstract:

Time interleaved sigma-delta (TIΣΔ) architecture is a potential candidate for high bandwidth analog to digital converters (ADC) which remains a bottleneck for software and cognitive radio receivers. However, the performance of the TIΣΔ architecture is limited by the unavoidable gain and offset mismatches resulting from the manufacturing process. This paper presents a novel digital calibration method to compensate the gain and offset mismatch effect. The proposed method takes advantage of the reconstruction digital signal processing on each channel and requires only few logic components for implementation. The run time calibration is estimated to 10 and 15 clock cycles for offset cancellation and gain mismatch calibration respectively.

Keywords: sigma-delta, calibration, gain and offset mismatches, analog-to-digital conversion, time-interleaving.

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498 A 5-V to 30-V Current-Mode Boost Converter with Integrated Current Sensor and Power-on Protection

Authors: Jun Yu, Yat-Hei Lam, Boris Grinberg, Kevin Chai Tshun Chuan

Abstract:

This paper presents a 5-V to 30-V current-mode boost converter for powering the drive circuit of a micro-electro-mechanical sensor. The design of a transconductance amplifier and an integrated current sensing circuit are presented. In addition, essential building blocks for power-on protection such as a soft-start and clamp block and supply and clock ready block are discussed in details. The chip is fabricated in a 0.18-μm CMOS process. Measurement results show that the soft-start and clamp block can effectively limit the inrush current during startup and protect the boost converter from startup failure.

Keywords: Boost Converter, Current Sensing, Power-on protection, Step-up Converter, Soft-start.

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497 Neutralization of Alkaline Waste-Waters using a Blend of Microorganisms

Authors: Rita Kumar, Alka Sharma, Purnima Dhall, Niha M. Kulshreshtha, Anil Kumar

Abstract:

The efficient operation of any biological treatment process requires pre-treatment of incompatible pollutants such as acids, bases, oil, toxic substances, etc. which hamper the treatment of other major components which are otherwise degradable. The pre-treatment of alkaline waste-waters, generated from various industries like textile, paper & pulp, potato-processing industries, etc., having a pH of 10 or higher, is essential. The pre-treatment, i.e., neutralization of such alkaline waste-waters can be achieved by chemical as well as biological means. However, the biological pretreatment offers better package over the chemical means by being safe and economical. The biological pre-treatment can be accomplished by using a blend of microorganisms able to withstand such harsh alkaline conditions. In the present study, for the proper pre-treatment of alkaline waste-waters, a package of alkalophilic bacteria is formulated to neutralise the alkaline pH of the industrial waste-waters. The developed microbial package is cost-effective as well as environmental friendly.

Keywords: alkaline, alkalophilic bacteria, biological, pollutants, textile.

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496 A Pipelined FSBM Hardware Architecture for HTDV-H.26x

Authors: H. Loukil, A. Ben Atitallah, F. Ghozzi, M. A. Ben Ayed, N. Masmoudi

Abstract:

In MPEG and H.26x standards, to eliminate the temporal redundancy we use motion estimation. Given that the motion estimation stage is very complex in terms of computational effort, a hardware implementation on a re-configurable circuit is crucial for the requirements of different real time multimedia applications. In this paper, we present hardware architecture for motion estimation based on "Full Search Block Matching" (FSBM) algorithm. This architecture presents minimum latency, maximum throughput, full utilization of hardware resources such as embedded memory blocks, and combining both pipelining and parallel processing techniques. Our design is described in VHDL language, verified by simulation and implemented in a Stratix II EP2S130F1020C4 FPGA circuit. The experiment result show that the optimum operating clock frequency of the proposed design is 89MHz which achieves 160M pixels/sec.

Keywords: SAD, FSBM, Hardware Implementation, FPGA.

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495 Hardware Prototyping of an Efficient Encryption Engine

Authors: Muhammad I. Ibrahimy, Mamun B.I. Reaz, Khandaker Asaduzzaman, Sazzad Hussain

Abstract:

An approach to develop the FPGA of a flexible key RSA encryption engine that can be used as a standard device in the secured communication system is presented. The VHDL modeling of this RSA encryption engine has the unique characteristics of supporting multiple key sizes, thus can easily be fit into the systems that require different levels of security. A simple nested loop addition and subtraction have been used in order to implement the RSA operation. This has made the processing time faster and used comparatively smaller amount of space in the FPGA. The hardware design is targeted on Altera STRATIX II device and determined that the flexible key RSA encryption engine can be best suited in the device named EP2S30F484C3. The RSA encryption implementation has made use of 13,779 units of logic elements and achieved a clock frequency of 17.77MHz. It has been verified that this RSA encryption engine can perform 32-bit, 256-bit and 1024-bit encryption operation in less than 41.585us, 531.515us and 790.61us respectively.

Keywords: RSA, FPGA, Communication, Security, VHDL.

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494 Identifying Network Subgraph-Associated Essential Genes in Molecular Networks

Authors: Efendi Zaenudin, Chien-Hung Huang, Ka-Lok Ng

Abstract:

Essential genes play an important role in the survival of an organism. It has been shown that cancer-associated essential genes are genes necessary for cancer cell proliferation, where these genes are potential therapeutic targets. Also, it was demonstrated that mutations of the cancer-associated essential genes give rise to the resistance of immunotherapy for patients with tumors. In the present study, we focus on studying the biological effects of the essential genes from a network perspective. We hypothesize that one can analyze a biological molecular network by decomposing it into both three-node and four-node digraphs (subgraphs). These network subgraphs encode the regulatory interaction information among the network’s genetic elements. In this study, the frequency of occurrence of the subgraph-associated essential genes in a molecular network was quantified by using the statistical parameter, odds ratio. Biological effects of subgraph-associated essential genes are discussed. In summary, the subgraph approach provides a systematic method for analyzing molecular networks and it can capture useful biological information for biomedical research.

Keywords: Biological molecular networks, essential genes, graph theory, network subgraphs.

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493 A Novel Implementation of Application Specific Instruction-set Processor (ASIP) using Verilog

Authors: Kamaraju.M, Lal Kishore.K, Tilak.A.V.N

Abstract:

The general purpose processors that are used in embedded systems must support constraints like execution time, power consumption, code size and so on. On the other hand an Application Specific Instruction-set Processor (ASIP) has advantages in terms of power consumption, performance and flexibility. In this paper, a 16-bit Application Specific Instruction-set processor for the sensor data transfer is proposed. The designed processor architecture consists of on-chip transmitter and receiver modules along with the processing and controlling units to enable the data transmission and reception on a single die. The data transfer is accomplished with less number of instructions as compared with the general purpose processor. The ASIP core operates at a maximum clock frequency of 1.132GHz with a delay of 0.883ns and consumes 569.63mW power at an operating voltage of 1.2V. The ASIP is implemented in Verilog HDL using the Xilinx platform on Virtex4.

Keywords: ASIP, Data transfer, Instruction set, Processor

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492 A Virtual Learning Environment for Deaf Children: Design and Evaluation

Authors: Nicoletta Adamo-Villani

Abstract:

The object of this research is the design and evaluation of an immersive Virtual Learning Environment (VLE) for deaf children. Recently we have developed a prototype immersive VR game to teach sign language mathematics to deaf students age K- 4 [1] [2]. In this paper we describe a significant extension of the prototype application. The extension includes: (1) user-centered design and implementation of two additional interactive environments (a clock store and a bakery), and (2) user-centered evaluation including development of user tasks, expert panel-based evaluation, and formative evaluation. This paper is one of the few to focus on the importance of user-centered, iterative design in VR application development, and to describe a structured evaluation method.

Keywords: 3D Animation, Virtual Reality, Virtual Learning Environments, User-Centered Design, User-centered Evaluation.

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491 Design and Analysis of a Low Power High Speed 1 Bit Full Adder Cell Based On TSPC Logic with Multi-Threshold CMOS

Authors: Ankit Mitra

Abstract:

An adder is one of the most integral component of a digital system like a digital signal processor or a microprocessor. Being an extremely computationally intensive part of a system, the optimization for speed and power consumption of the adder is of prime importance. In this paper we have designed a 1 bit full adder cell based on dynamic TSPC logic to achieve high speed operation. A high threshold voltage sleep transistor is used to reduce the static power dissipation in standby mode. The circuit is designed and simulated in TSPICE using TSMC 180nm CMOS process. Average power consumption, delay and power-delay product is measured which showed considerable improvement in performance over the existing full adder designs.

Keywords: CMOS, TSPC, MTCMOS, ALU, Clock gating, power gating, pipelining.

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490 A Study of Removing SUVA and Trihalomethanes by Biological Activated Carbon

Authors: Tseng, Wei-Bin., Lou, Jie-Chung, Han, Jia-Yun

Abstract:

SUVA (equivalent to UV254/DOC) value in raw water is a precursor for the formation of trihalomethane during chlorination at a water treatment plant. This study collected rapidly filtered water from an advanced water treatment plant for use in experiments on raw water. The removal rate of treating the trihalomethanes formation potential (THMFP) was conducted by using a biological activated carbon. The hydraulic retention time and SUVA loading were major factors in biological degradation tests. The results showed that biological powder-activated carbon (BPAC) lowered the average concentration of UV254 and value of SUVA in raw water. A removal efficiency of THMFP was present in the treatment of the three primary organic carbon items. These results highlighted the importance of the BPAC had an excellent treatment efficiency on THMFP.

Keywords: Water treatment, BPAC, THMFP, SUVA, correlation analysis.

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489 Quantum Dot Cellular Automata Based Effective Design of Combinational and Sequential Logical Structures

Authors: Hema Sandhya Jagarlamudi, Mousumi Saha, Pavan Kumar Jagarlamudi

Abstract:

The use of Quantum dots is a promising emerging Technology for implementing digital system at the nano level. It is effecient for attractive features such as faster speed , smaller size and low power consumption than transistor technology. In this paper, various Combinational and sequential logical structures - HALF ADDER, SR Latch and Flip-Flop, D Flip-Flop preceding NAND, NOR, XOR,XNOR are discussed based on QCA design, with comparatively less number of cells and area. By applying these layouts, the hardware requirements for a QCA design can be reduced. These structures are designed and simulated using QCA Designer Tool. By taking full advantage of the unique features of this technology, we are able to create complete circuits on a single layer of QCA. Such Devices are expected to function with ultra low power Consumption and very high speeds.

Keywords: QCA, QCA Designer, Clock, Majority Gate

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488 Biological and Chemical Filter Treatment for Wastewater Reuse

Authors: M. J. Go, H. S. Shin, D. W. Kim, D. Chang, S. B. Han, J. M. Hur, B. R. Chung, J. K. Choi, J. Fan

Abstract:

This study developed a high efficient and combined biological and chemical filter treatment process. This process used PAC (Powder Activated Carbon), Alum and attached growth treatment process. The system removals of total nitrogen and total phosphorus ratio of two were as high as 70% and 73%, moreover, the effluent water was suitable to urban and agricultural water. Also the advantages of this process are not only occupies small place but is simple, economic and easy operating. Besides, our developed process can keep stable process efficiency even in relative low load level. Therefore, this study judges that use of the high efficient and combined biological and chemical filter treatment process, it is expected that the effluent water in this system can be reused as urban and agricultural water.

Keywords: biological and chemical filter treatment, wastewaterreuse, PAC, Alum

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487 An Efficient VLSI Design Approach to Reduce Static Power using Variable Body Biasing

Authors: Md. Asif Jahangir Chowdhury, Md. Shahriar Rizwan, M. S. Islam

Abstract:

In CMOS integrated circuit design there is a trade-off between static power consumption and technology scaling. Recently, the power density has increased due to combination of higher clock speeds, greater functional integration, and smaller process geometries. As a result static power consumption is becoming more dominant. This is a challenge for the circuit designers. However, the designers do have a few methods which they can use to reduce this static power consumption. But all of these methods have some drawbacks. In order to achieve lower static power consumption, one has to sacrifice design area and circuit performance. In this paper, we propose a new method to reduce static power in the CMOS VLSI circuit using Variable Body Biasing technique without being penalized in area requirement and circuit performance.

Keywords: variable body biasing, state saving technique, stack effect, dual V-th, static power reduction.

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486 Dynamic Behavior of the Nanostructure of Load-bearing Biological Materials

Authors: M. Qwamizadeh, K. Zhou, Z. Zhang, YW. Zhang

Abstract:

Typical load-bearing biological materials like bone, mineralized tendon and shell, are biocomposites made from both organic (collagen) and inorganic (biomineral) materials. This amazing class of materials with intrinsic internally designed hierarchical structures show superior mechanical properties with regard to their weak components from which they are formed. Extensive investigations concentrating on static loading conditions have been done to study the biological materials failure. However, most of the damage and failure mechanisms in load-bearing biological materials will occur whenever their structures are exposed to dynamic loading conditions. The main question needed to be answered here is: What is the relation between the layout and architecture of the load-bearing biological materials and their dynamic behavior? In this work, a staggered model has been developed based on the structure of natural materials at nanoscale and Finite Element Analysis (FEA) has been used to study the dynamic behavior of the structure of load-bearing biological materials to answer why the staggered arrangement has been selected by nature to make the nanocomposite structure of most of the biological materials. The results showed that the staggered structures will efficiently attenuate the stress wave rather than the layered structure. Furthermore, such staggered architecture is effectively in charge of utilizing the capacity of the biostructure to resist both normal and shear loads. In this work, the geometrical parameters of the model like the thickness and aspect ratio of the mineral inclusions selected from the typical range of the experimentally observed feature sizes and layout dimensions of the biological materials such as bone and mineralized tendon. Furthermore, the numerical results validated with existing theoretical solutions. Findings of the present work emphasize on the significant effects of dynamic behavior on the natural evolution of load-bearing biological materials and can help scientists to design bioinspired materials in the laboratories.

Keywords: Load-bearing biological materials, nanostructure, staggered structure, stress wave decay.

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