Hardware Prototyping of an Efficient Encryption Engine

Authors: Muhammad I. Ibrahimy, Mamun B.I. Reaz, Khandaker Asaduzzaman, Sazzad Hussain

Abstract:

An approach to develop the FPGA of a flexible key RSA encryption engine that can be used as a standard device in the secured communication system is presented. The VHDL modeling of this RSA encryption engine has the unique characteristics of supporting multiple key sizes, thus can easily be fit into the systems that require different levels of security. A simple nested loop addition and subtraction have been used in order to implement the RSA operation. This has made the processing time faster and used comparatively smaller amount of space in the FPGA. The hardware design is targeted on Altera STRATIX II device and determined that the flexible key RSA encryption engine can be best suited in the device named EP2S30F484C3. The RSA encryption implementation has made use of 13,779 units of logic elements and achieved a clock frequency of 17.77MHz. It has been verified that this RSA encryption engine can perform 32-bit, 256-bit and 1024-bit encryption operation in less than 41.585us, 531.515us and 790.61us respectively.

Keywords: RSA, FPGA, Communication, Security, VHDL.

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1081297

References:

[1] M.K. Hani, T.S. Lin, N. Shaikh-Husin, "FPGA Implementation of RSA Public-Key Cryptographic Coprocessor", in Proceedings of TENCON, vol. 3, pp. 6-11, Kuala Lumpur, Malaysia, 2000.
[2] Y.S. Kim, W.S. Kang, J.R. Choi, "Implementation of 1024-bit Modular Processor for RSA Cryptosystem", in Proceedings of Asia-Pasific Conference on ASIC, pp. 187-190, Cheju Island, Korea, 2000.
[3] M. Shand and J. Vuillemin, "Fast Implementation of RSA Cryptography", in Proceedings of 11th IEEE Symposium on Computer Arithmetic, pp. 252-259, Windsor, Ontario, 1993.
[4] C. Brueggen, J. Singh, D. Lord, B. Siever, D. Sullins, "A Hardware Approach to RSA Encryption", Department of Electrical and Computer Engineering University of Missouri-Rolla, pp. 1-14, Citing Internet Sources; URL: http://www.mentor.com/partners/hep/HDLcontest.htm
[5] Rivest, R., Shamir, A., and Adleman, L, "A Method for Obtaining Digital Signatures and Public Key Cryptosystems", Communications of the ACM, 1978, vol. 21, no. 2, pp. 120-126.
[6] C. K. Koc., "RSA Hardware Implementation. Technical Report TR 801", RSA Laboratories, 1996, pp. 1-24.