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A Novel Digital Calibration Technique for Gain and Offset Mismatch in TIΣΔ ADCs
Abstract:Time interleaved sigma-delta (TIΣΔ) architecture is a potential candidate for high bandwidth analog to digital converters (ADC) which remains a bottleneck for software and cognitive radio receivers. However, the performance of the TIΣΔ architecture is limited by the unavoidable gain and offset mismatches resulting from the manufacturing process. This paper presents a novel digital calibration method to compensate the gain and offset mismatch effect. The proposed method takes advantage of the reconstruction digital signal processing on each channel and requires only few logic components for implementation. The run time calibration is estimated to 10 and 15 clock cycles for offset cancellation and gain mismatch calibration respectively.
Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1078307Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 4979
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