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A Novel Implementation of Application Specific Instruction-set Processor (ASIP) using Verilog
Abstract:The general purpose processors that are used in embedded systems must support constraints like execution time, power consumption, code size and so on. On the other hand an Application Specific Instruction-set Processor (ASIP) has advantages in terms of power consumption, performance and flexibility. In this paper, a 16-bit Application Specific Instruction-set processor for the sensor data transfer is proposed. The designed processor architecture consists of on-chip transmitter and receiver modules along with the processing and controlling units to enable the data transmission and reception on a single die. The data transfer is accomplished with less number of instructions as compared with the general purpose processor. The ASIP core operates at a maximum clock frequency of 1.132GHz with a delay of 0.883ns and consumes 569.63mW power at an operating voltage of 1.2V. The ASIP is implemented in Verilog HDL using the Xilinx platform on Virtex4.
Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1080656Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 2004
 ARINC Digital Data System Compendium, ARINC Report 419- 3,November 5, 1984.
 ARINC Specification 429P1-15, Sep. 1, 1995.
 ARINC Specification 429P2-15, March 6, 1996.
 "ARINC 629 P1-4 Multi-Transmitter Data Bus","Part1, Technical Description", December 1995.
 ARINC Airborne Computer Data Loader,ARINC Report 615-2, June 1, 1991.
 Baburao.K, Apparao.T, Prabu.A.V, RamBabu.E, "VHDL Implementation and Verification of ARINC-429 Core",International Journal of engineering, technology and science,vol . 2,2011,pp 174-178.
 Jin Soo Kim Sunwoo, Myung H. Sunwoo, "Three low power ASIP processor designs for communications, video, and audio applications", International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2007. DTIS , pp. 241-244.
 Kamaraju.M, Tilak.A.V.N, Lalkishore.K, Baburao.K, "VHDL implementation and verification of ARINC-429 core", CoRR International Journal, vol.1,2010,pp1-5.
 Kane.G., and Heinrich.J,MIPS RISC Architecture: reference for the R2000, R3000, R6000 and the new R4000 instruction set computer architecture. Prentice-Hall, EnglewoodCliffs, NJ, 1992.
 Krall.A. "An extended Prolog instruction set for RISC processors", in VLSI for Artificial Intelligence and Neural Networks (New York, NY, 1991), J. G. Delgado-Frias and W. R. Moore, Eds., Plenum Press, pp. 101-108.
 Mohan.R, Land.I, "Building Integrated ARINC 429 Interfaces using an FPGA". Actel Corporation, Mountain View, California,2005.
 Motorola Inc.,"M68000 8-/16-/32-Bit Microprocessors User-s Manual,"
[Onlinedocument],1993(Ninth Edition), available at http://www.freescale.com/files/32bit/doc/ref_manual/MC68000UM.pdf.
 Rose.J, GamaL.A.E, and A. Sangiovanni Vincentelli.A, "Architecture of Field-Programmable Gate Arrays," Proc. IEEE, vol. 81, no. 7, July 1993, pp.1013-102.
 Sato.J, Alomary,A. Y., Honma,Y., Nakata, T., Shiomi, A., Hikichi, N., and Imai, M. PEAS-I: "A hardware/software codesign system for ASIP development", IEICE Transactions on Fundamentals of Electronics, Communications and Computer Science E77-A, 3 (March 1994),pp 483-491.
 Van prate.J, Goossens.G, Lanneer.D, and De man.H " Instruction set definition and instruction set selection for ASIPs", In Proc. of the 7th International Symposium on High-Level Synthesis 1994, pp. 11-16.