Search results for: Gate delay

Authors: Hana Naghawi, Khair Jadaan, Rabab Al-Louzi, Taqwa Hadidi

Abstract:

This paper is aimed to evaluate and compare the operational performance of three Unconventional Arterial Intersection Designs (UAIDs) including Median U-Turn, Superstreet, and Single Quadrant Intersection using real traffic data. For this purpose, the heavily congested signalized intersection of Wadi Saqra in Amman was selected. The effect of implementing each of the proposed UAIDs was not only evaluated on the isolated Wadi Saqra signalized intersection, but also on the arterial road including both surrounding intersections. The operational performance of the isolated intersection was based on the level of service (LOS) expressed in terms of control delay and volume to capacity ratio. On the other hand, the measures used to evaluate the operational performance on the arterial road included traffic progression, stopped delay per vehicle, number of stops and the travel speed. The analysis was performed using SYNCHRO 8 microscopic software. The simulation results showed that all three selected UAIDs outperformed the conventional intersection design in terms of control delay but only the Single Quadrant Intersection design improved the main intersection LOS from F to B. Also, the results indicated that the Single Quadrant Intersection design resulted in an increase in average travel speed by 52%, and a decrease in the average stopped delay by 34% on the selected corridor when compared to the corridor with conventional intersection design. On basis of these results, it can be concluded that the Median U-Turn and the Superstreet do not perform the best under heavy traffic volumes.

Keywords: Median U-turn, single quadrant, superstreet, unconventional arterial intersection design.

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Authors: Ebrahim Safarian, Kadir Bilen, Akif Ceviz

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The turbocharger and turbocharging have been the inherent component of diesel engines, so that critical parameters of such engines, as BSFC (Brake Specific Fuel Consumption) or thermal efficiency, fuel consumption, BMEP (Brake Mean Effective Pressure), the power density output and emission level have been improved extensively. In general, the turbocharger can be considered as the most complex component of diesel engines, because it has closely interrelated turbomachinery concepts of the turbines and the compressors to thermodynamic fundamentals of internal combustion engines and stress analysis of all components. In this paper, a waste gate for a conventional single stage radial turbine is investigated by consideration of turbochargers operation constrains and engine operation conditions, without any detail designs in the turbine and the compressor. Amount of opening waste gate which extended between the ranges of full opened and closed valve, is demonstrated by limiting compressor boost pressure ratio. Obtaining of an optimum point by regard above mentioned items is surveyed by three linked meanline modeling programs together which consist of Turbomatch®, Compal®, Rital® madules in concepts NREC® respectively.

Keywords: Turbocharger, Wastegate, diesel engine, CONCEPT NREC programs.

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Authors: Yavar Safaei Mehrabani, Mehdi Hosseinzadeh

Abstract:

As embedded and portable systems were emerged power consumption of circuits had been major challenge. On the other hand latency as determines frequency of circuits is also vital task. Therefore, trade off between both of them will be desirable. Modulo 2n+1 adders are important part of the residue number system (RNS) based arithmetic units with the interesting moduli set (2n-1,2n, 2n+1). In this manuscript we have introduced novel binary representation to the design of modulo 2n+1 adder. VLSI realization of proposed architecture under 180 nm full static CMOS technology reveals its superiority in terms of area, power consumption and power-delay product (PDP) against several peer existing structures.

Keywords: Computer arithmetic, modulo 2n+1 adders, Residue Number System (RNS), VLSI.

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Authors: Mamoon Mousa Atout

Abstract:

Projects managers in construction industry usually face a difficult organizational environment especially if the project is unique. The organization lacks the processes to practice construction management correctly, and the executive’s technical managers who have lack of experience in playing their role and responsibilities correctly. Project managers need to adopt best practices that allow them to do things effectively to make sure that the project can be delivered without any delay even though the executive’s technical managers should follow a certain process to avoid any factor might cause any delay during the project life cycle. The purpose of the paper is to examine the awareness level of projects managers about construction management processes, tools, techniques and implications to complete projects on time. The outcome and the results of the study are prepared based on the designed questionnaires and interviews conducted with many project managers. The method used in this paper is a quantitative study. A survey with a sample of 100 respondents was prepared and distributed in a construction company in Dubai, which includes nine questions to examine the level of their awareness. This research will also identify the necessary benefits of processes of construction management that has to be adopted by projects managers to mitigate the maximum potential problems which might cause any delay to the project life cycle.

Keywords: Construction Methodology, Design Process, Project Managers, Scheduling and Resource Planning.

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Authors: Bit-Na Kwon, Dong-Hyun Ha, Hyoung-Kyu Song

Abstract:

In wireless communication, space-time block code (STBC), cyclic delay diversity (CDD) and space-time cyclic delay diversity (STCDD)are used as the spatial diversity schemes and have been widely studied for the reliablecommunication. If these schemes are used, the communication system can obtain the improved performance. However,the quality of the system is degraded when the distance between a source and a destination is distant in wireless communication system. In this paper, the cooperative transmission scheme using two sources is proposed and improves the performance of the wireless communication system.

Keywords: OFDM, Cooperative communication, CDD, STBC, STCDD.

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Authors: Jiri Sebesta

Abstract:

Phase locked loops (PLL) and delay locked loops (DLL) play an important role in establishing coherent references (phase of carrier and symbol timing) in digital communication systems. Fully digital receiver including digital carrier synchronizer and symbol timing synchronizer fulfils the conditions for universal multi-mode communication receiver with option of symbol rate setting over several digit places and long-term stability of requirement parameters. Afterwards it is necessary to realize PLL and DLL in synchronizer in digital form and to approach to these subsystems as a discrete representation of analog template. Analysis of discrete phase locked loop (DPLL) or discrete delay locked loop (DDLL) and technique to determine their characteristics based on analog (continuous-time) template is performed in this posed paper. There are derived transmission response and error function for 1st order discrete locked loop and resulting equations and graphical representations for 2nd order one. It is shown that the spectrum translation due to sampling takes effect at frequency characteristics computing for specific values of loop parameters.

Keywords: Carrier synchronization, coherent demodulation, software defined receiver, symbol timing.

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Authors: Hafiz ul Azad, Dragan V.Lazic, Waqar Shahid

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This paper presents implementation of attitude controller for a small UAV using field programmable gate array (FPGA). Due to the small size constrain a miniature more compact and computationally extensive; autopilot platform is needed for such systems. More over UAV autopilot has to deal with extremely adverse situations in the shortest possible time, while accomplishing its mission. FPGAs in the recent past have rendered themselves as fast, parallel, real time, processing devices in a compact size. This work utilizes this fact and implements different attitude controllers for a small UAV in FPGA, using its parallel processing capabilities. Attitude controller is designed in MATLAB/Simulink environment. The discrete version of this controller is implemented using pipelining followed by retiming, to reduce the critical path and thereby clock period of the controller datapath. Pipelined, retimed, parallel PID controller implementation is done using rapidprototyping and testing efficient development tool of “system generator", which has been developed by Xilinx for FPGA implementation. The improved timing performance enables the controller to react abruptly to any changes made to the attitudes of UAV.

Keywords: Field Programmable gate array (FPGA), Hardwaredescriptive Language (HDL), PID, Pipelining, Retiming, XilinxSystem Generator.

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Authors: Beata Jackowska-Zduniak

Abstract:

We formulate and analyze a mathematical model describing dynamics of the hypothalamus-pituitary-thyroid homoeostatic mechanism in endocrine system. We introduce to this system two types of couplings and delay. In our model, feedback controls the secretion of thyroid hormones and delay reflects time lags required for transportation of the hormones. The influence of delayed feedback on the stability behaviour of the system is discussed. Analytical results are illustrated by numerical examples of the model dynamics. This system of equations describes normal activity of the thyroid and also a couple of types of malfunctions (e.g. hyperthyroidism).

Keywords: Mathematical modeling, ordinary differential equations, endocrine system, stability analysis.

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Authors: M. Kollar, A. Zieba

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In this paper, we present a method for a time synchronization between the two eNodeBs (eNBs) in E-UTRAN (Evolved Universal Terrestrial Radio Access) network. The two eNBs are cooperating in so-called inter eNB CA (Carrier Aggregation) case and connected via asymmetrical IP network. We solve the problem by using broadcasting signals generated in E-UTRAN as synchronization signals. The results show that the time synchronization with the proposed method is possible with the error significantly less than 1 ms which is sufficient considering the time transmission interval is 1 ms in E-UTRAN. This makes this method (with low complexity) more suitable than Network Time Protocol (NTP) in the mobile applications with generated broadcasting signals where time synchronization in asymmetrical network is required.

Keywords: E-UTRAN, IP scheduled throughput, initial burst delay, synchronization, NTP, delay, asymmetric network.

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Authors: Y. Harold Robinson, E. Golden Julie, S. Balaji

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The scheduling based routing scheme is presented in this paper to avoid link failure. The main objective of this system is to introduce a cross-layer protocol framework that integrates routing with priority-based traffic management and distributed transmission scheduling. The reservation scheme is based on ID. The presented scheme guarantees that bandwidth reserved time slot is used by another packet in which end-to-end reservation is achieved. The Bandwidth and Delay Aware Routing Protocol with Scheduling Algorithm is presented to allocate channels efficiently. The experimental results show that the presented schemes performed well in various parameters compared to existing methods.

Keywords: Integrated routing, scheduling, MAC layer, IEEE 802.11.

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Authors: H. El-Madbouly

Abstract:

For future Broad band ISDN, Asynchronous Transfer Mode (ATM) is designed not only to support a wide range of traffic classes with diverse flow characteristics, but also to guarantee the different quality of service QOS requirements. The QOS may be measured in terms of cell loss probability and maximum cell delay. In this paper, ATM networks in which the virtual path (VP) concept is implemented are considered. By applying the Markov Deterministic process method, an efficient algorithm to compute the minimum capacity required to satisfy the QOS requirements when multiple classes of on-off are multiplexed on to a single VP. Using the result, we then proposed a simple algorithm to determine different combinations of VP to achieve the optimum of the total capacity required for satisfying the individual QOS requirements (loss- delay).

Keywords: Bandwidth allocation, Quality of services, ATMNetwork, virtual path.

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Authors: Q. Zafar, R. Akram, Kh.S. Karimov, T.A. Khan, M. Farooq, M.M. Tahir

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In this study we present the effect of elevated temperatures from 300K to 400K on the electrical properties of copper Phthalocyanine (CuPc) based organic field effect transistors (OFET). Thin films of organic semiconductor CuPc (40nm) and semitransparent Al (20nm) were deposited in sequence, by vacuum evaporation on a glass substrate with previously deposited Ag source and drain electrodes with a gap of 40 μm. Under resistive mode of operation, where gate was suspended it was observed that drain current of this organic field effect transistor (OFET) show an increase with temperature. While in grounded gate condition metal (aluminum) – semiconductor (Copper Phthalocyanine) Schottky junction dominated the output characteristics and device showed switching effect from low to high conduction states like Zener diode at higher bias voltages. This threshold voltage for switching effect has been found to be inversely proportional to temperature and shows an abrupt decrease after knee temperature of 360K. Change in dynamic resistance (Rd = dV/dI) with respect to temperature was observed to be -1%/K.

Keywords: Copper Phthalocyanine, Metal-Semiconductor Schottky Junction, Organic Field Effect Transistor, Switching effect, Temperature Sensor

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Authors: Yasunori Sugita, Toshinori Yoshikawa, Naoyuki Aikawa

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Variable digital filters are useful for various signal processing and communication applications where the frequency characteristics, such as fractional delays and cutoff frequencies, can be varied. In this paper, we propose a design method of variable FIR digital filters with an approximate linear phase characteristic in the passband. The proposed variable FIR filters have some large attenuation in stopband and their large attenuation can be varied by spectrum parameters. In the proposed design method, a quasi-equiripple characteristic can be obtained by using an iterative weighted least square method. The usefulness of the proposed design method is verified through some examples.

Keywords: Weighted Least Squares Approximation, Variable FIR Filters, Low-Delay, Quasi-Equiripple

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Authors: Qingqing Wang, Baocheng Chen, Shouming Zhong

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In this paper, utilizing the Lyapunov functional method and combining linear matrix inequality (LMI) techniques and integral inequality approach (IIA) to study the exponential stability problem for neural networks with discrete and distributed time-varying delays.By constructing new Lyapunov-Krasovskii functional and dividing the discrete delay interval into multiple segments,some new delay-dependent exponential stability criteria are established in terms of LMIs and can be easily checked.In order to show the stability condition in this paper gives much less conservative results than those in the literature,numerical examples are considered.

Keywords: Neural networks, Exponential stability, LMI approach, Time-varying delays.

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Authors: Sami Mutair, Yasuyuki Ikegami

Abstract:

This paper reports on the results of experimental investigations of flash evaporation from superheated jet issues vertically upward from a round straight nozzle of 81.3 mm diameter. For the investigated range of jet superheat degree and velocity, it was shown that flash evaporation enhances with initial temperature increase. Due to the increase of jet inertia and subsequently the delay of jet shattering, increase of jet velocity was found to result in increase of evaporation "delay period". An empirical equation predicts the jet evaporation completion height was developed, this equation is thought to be useful in designing the flash evaporation chamber. In attempts for enhancement of flash evaporation, use of steel wire mesh located at short distance downstream was found effective with no consequent pressure drop.

Keywords: Enhancement; Flash Evaporation; OTEC; superheated jet

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Authors: M. Geetha Priya, K. Baskaran, S. Srinivasan

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Digital systems are said to be constructed using basic logic gates. These gates are the NOR, NAND, AND, OR, EXOR & EXNOR gates. This paper presents a robust three transistors (3T) based NAND and NOR gates with precise output logic levels, yet maintaining equivalent performance than the existing logic structures. This new set of 3T logic gates are based on CMOS inverter and Pass Transistor Logic (PTL). The new universal logic gates are characterized by better speed and lower power dissipation which can be straightforwardly fabricated as memory ICs for high performance computer networks. The simulation tests were performed using standard BPTM 22nm process technology using SYNOPSYS HSPICE. The 3T NAND gate is evaluated using C17 benchmark circuit and 3T NOR is gate evaluated using a D-Latch. According to HSPICE simulation in 22 nm CMOS BPTM process technology under given conditions and at room temperature, the proposed 3T gates shows an improvement of 88% less power consumption on an average over conventional CMOS logic gates. The devices designed with 3T gates will make longer battery life by ensuring extremely low power consumption.

Keywords: Low power, CMOS, pass-transistor, flash memory, logic gates.

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Authors: Shu Lü, Shouming Zhong, Zixin Liu

Abstract:

In this paper, the robust exponential stability problem of discrete-time uncertain stochastic neural networks with timevarying delays is investigated. By introducing a new augmented Lyapunov function, some delay-dependent stable results are obtained in terms of linear matrix inequality (LMI) technique. Compared with some existing results in the literature, the conservatism of the new criteria is reduced notably. Three numerical examples are provided to demonstrate the less conservatism and effectiveness of the proposed method.

Keywords: Robust exponential stability, delay-dependent stability, discrete-time neural networks, stochastic, time-varying delays.

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Authors: Changjin Xu

Abstract:

In this paper, applying frequency domain approach, a delayed predator-prey fishery model with prey reserve is investigated. By choosing the delay τ as a bifurcation parameter, It is found that Hopf bifurcation occurs as the bifurcation parameter τ passes a sequence of critical values. That is, a family of periodic solutions bifurcate from the equilibrium when the bifurcation parameter exceeds a critical value. The length of delay which preserves the stability of the positive equilibrium is calculated. Some numerical simulations are included to justify the theoretical analysis results. Finally, main conclusions are given.

Keywords: Predator-prey model, stability, Hopf bifurcation, frequency domain, Nyquist criterion.

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Authors: Padmanabhan Balasubramanian, C. Ardil

Abstract:

In this paper, we consider the problem of logic simplification for a special class of logic functions, namely complementary Boolean functions (CBF), targeting low power implementation using static CMOS logic style. The functions are uniquely characterized by the presence of terms, where for a canonical binary 2-tuple, D(mj) ∪ D(mk) = { } and therefore, we have | D(mj) ∪ D(mk) | = 0 [19]. Similarly, D(Mj) ∪ D(Mk) = { } and hence | D(Mj) ∪ D(Mk) | = 0. Here, 'mk' and 'Mk' represent a minterm and maxterm respectively. We compare the circuits minimized with our proposed method with those corresponding to factored Reed-Muller (f-RM) form, factored Pseudo Kronecker Reed-Muller (f-PKRM) form, and factored Generalized Reed-Muller (f-GRM) form. We have opted for algebraic factorization of the Reed-Muller (RM) form and its different variants, using the factorization rules of [1], as it is simple and requires much less CPU execution time compared to Boolean factorization operations. This technique has enabled us to greatly reduce the literal count as well as the gate count needed for such RM realizations, which are generally prone to consuming more cells and subsequently more power consumption. However, this leads to a drawback in terms of the design-for-test attribute associated with the various RM forms. Though we still preserve the definition of those forms viz. realizing such functionality with only select types of logic gates (AND gate and XOR gate), the structural integrity of the logic levels is not preserved. This would consequently alter the testability properties of such circuits i.e. it may increase/decrease/maintain the same number of test input vectors needed for their exhaustive testability, subsequently affecting their generalized test vector computation. We do not consider the issue of design-for-testability here, but, instead focus on the power consumption of the final logic implementation, after realization with a conventional CMOS process technology (0.35 micron TSMC process). The quality of the resulting circuits evaluated on the basis of an established cost metric viz., power consumption, demonstrate average savings by 26.79% for the samples considered in this work, besides reduction in number of gates and input literals by 39.66% and 12.98% respectively, in comparison with other factored RM forms.

Keywords: Reed-Muller forms, Logic function, Hammingdistance, Algebraic factorization, Low power design.

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Authors: H. Bentarzi, A. Zitouni

Abstract:

The reliability of the power grid depends on the successful operation of thousands of protective relays. The failure of one relay to operate as intended may lead the entire power grid to blackout. In fact, major power system failures during transient disturbances may be caused by unnecessary protective relay tripping rather than by the failure of a relay to operate. Adequate relay testing provides a first defense against false trips of the relay and hence improves power grid stability and prevents catastrophic bulk power system failures. The goal of this research project is to design and enhance the relay tester using a technology such as Field Programmable Gate Array (FPGA) card NI 7851. A PC based tester framework has been developed using Simulink power system model for generating signals under different conditions (faults or transient disturbances) and LabVIEW for developing the graphical user interface and configuring the FPGA. Besides, the interface system has been developed for outputting and amplifying the signals without distortion. These signals should be like the generated ones by the real power system and large enough for testing the relay’s functionality. The signals generated that have been displayed on the scope are satisfactory. Furthermore, the proposed testing system can be used for improving the performance of protective relay.

Keywords: Amplifier class D, FPGA, protective relay, tester.

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Authors: Zixin Liu, Jian Yu, Daoyun Xu

Abstract:

This paper aims to establish a delayed dynamical relationship between payoffs of players in a zero-sum game. By introducing Markovian chain and time delay in the network model, a delayed game network model with sector bounds and slope bounds restriction nonlinear function is first proposed. As a result, a direct dynamical relationship between payoffs of players in a zero-sum game can be illustrated through a delayed singular system. Combined with Finsler-s Lemma and Lyapunov stable theory, a sufficient condition guaranteeing the unique existence and stability of zero-sum game-s Nash equilibrium is derived. One numerical example is presented to illustrate the validity of the main result.

Keywords: Game networks, zero-sum game, delayed singular system, nonlinear perturbation, time delay.

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Authors: A. Hamdoune, M. Abdelmoumene, A. Hamroun

Abstract:

The objective of this paper is to simulate static I-V and dynamic characteristics of an appropriated and recessed n-GaN/AlxGa1-xN/GaN high electron mobility (HEMT). Using SILVACO TCAD device simulation, and optimized technological parameters; we calculate the drain-source current (lDS) as a function of the drain-source voltage (VDS) for different values ​​of the gate-source voltage (VGS), and the drain-source current (lDS) depending on the gate-source voltage (VGS) for a drain-source voltage (VDS) of 20 V, for various temperatures. Then, we calculate the cut-off frequency and the maximum oscillation frequency for different temperatures.

We obtain a high drain-current equal to 60 mA, a low knee voltage (Vknee) of 2 V, a high pinch-off voltage (VGS0) of 53.5 V, a transconductance greater than 600 mS/mm, a cut-off frequency (f_T) of about 330 GHz, and a maximum oscillation frequency (fmax) of about 1 THz.

Keywords: n-GaN/AlGaN/GaN HEMT, drain-source current (IDS), transconductance (gm), cut-off frequency (fT), maximum oscillation frequency (fmax).

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Authors: Ali Heidari

Abstract:

This paper presents the principles for improving flood mitigation operation in multipurpose dams and maximizing reservoir performance during flood occurrence with a focus on the real-time operation of gated spillways. The criteria of operation include the safety of dams during flood management, minimizing the downstream flood risk by decreasing the flood hazard and fulfilling water supply and other purposes of the dam operation in mid and long terms horizons. The parameters deemed to be important include flood inflow, outlet capacity restrictions, downstream flood inundation damages, economic revenue of dam operation, and environmental and sedimentation restrictions. A simulation model was used to determine the real-time release of the Dez Dam located in the Dez Rivers in southwest Iran, considering the gate regulation curves for the gated spillway. The results of the simulation model show that there is a possibility to improve the current procedures used in the real-time operation of the dams, particularly using gate regulation curves and early flood forecasting system results. The Dez Dam operation data show that in one of the best flood control records, 17% of the total active volume and flood control pool of the reservoir have not been used in decreasing the downstream flood hazard despite the availability of a flood forecasting system.

Keywords: Dam operation, flood control criteria, Dez Dam, Iran.

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Authors: Marwan Ihsan Shukur, Lee Sheng Chyan, Vooi Voon Yap

Abstract:

Wireless sensor networks is an emerging technology that serves as environment monitors in many applications. Yet these miniatures suffer from constrained resources in terms of computation capabilities and energy resources. Limited energy resource in these nodes demands an efficient consumption of that resource either by developing the modules itself or by providing an efficient communication protocols. This paper presents a comprehensive summarization and a comparative study of the available MAC protocols proposed for Wireless Sensor Networks showing their capabilities and efficiency in terms of energy consumption and delay guarantee.

Keywords: MAC (Medium Access Control), SEA (Simple EnergyAware), WSNs (Wireless Sensor Nodes or Networks) RTS (RequestTo Send), CTS (Clear To Send), SYNCH (Synchronize), NS2(Network Simulator 2).

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Authors: Zhenguo Vincent Chia, Sheung Yan Simon Ng, Minkyu Je

Abstract:

This paper presents CMOS Current Mode Logic (CML) circuits for a high speed Digital to Analog Converter (DAC) using standard CMOS 65nm process. The CML circuits have the propagation delay advantage over its conventional CMOS counterparts due to smaller output voltage swing and tunable bias current. The CML circuits proposed in this paper can achieve a maximum propagation delay of only 9.3ps, which can satisfy the stringent requirement for the 5 GHz high speed DAC application. Another advantage for CML circuits is its dynamic symmetry characteristic resulting in a reduction of an additional inverter. Simulation results show that the proposed CML circuits can operate from 1.08V to 1.3V with temperature ranging from -40 to +120°C.

Keywords: Conventional, Current Mode Logic, DAC, Decoder

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Authors: Shumin Hou, Yourong Li, Sanxing Zhao

Abstract:

Much time series data is generally from continuous dynamic system. Firstly, this paper studies the detection of the nonlinearity of time series from continuous dynamics systems by applying the Phase-randomized surrogate algorithm. Then, the Delay Vector Variance (DVV) method is introduced into nonlinearity test. The results show that under the different sampling conditions, the opposite detection of nonlinearity is obtained via using traditional test statistics methods, which include the third-order autocovariance and the asymmetry due to time reversal. Whereas the DVV method can perform well on determining nonlinear of Lorenz signal. It indicates that the proposed method can describe the continuous dynamics signal effectively.

Keywords: Nonlinearity, Time series, continuous dynamics system, DVV method

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Authors: Manoj Kumar Dutta

Abstract:

Wavelength Division Multiplexing (WDM) technology is the most promising technology for the proper utilization of huge raw bandwidth provided by an optical fiber. One of the key problems in implementing the all-optical WDM network is the packet contention. This problem can be solved by several different techniques. In time domain approach the packet contention can be reduced by incorporating Fiber Delay Lines (FDLs) as optical buffer in the switch architecture. Different types of buffering architectures are reported in literatures. In the present paper a comparative performance analysis of three most popular FDL architectures are presented in order to obtain the best contention resolution performance. The analysis is further extended to consider the effect of different fiber non-linearities on the network performance.

Keywords: WDM network, contention resolution, optical buffering, non-linearity, throughput.

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Authors: Zixin Liu, Huawei Yang, Fangwei Chen

Abstract:

This paper studies the mean square exponential synchronization problem of a class of stochastic neutral type chaotic neural networks with mixed delay. On the Basis of Lyapunov stability theory, some sufficient conditions ensuring the mean square exponential synchronization of two identical chaotic neural networks are obtained by using stochastic analysis and inequality technique. These conditions are expressed in the form of linear matrix inequalities (LMIs), whose feasibility can be easily checked by using Matlab LMI Toolbox. The feedback controller used in this paper is more general than those used in previous literatures. One simulation example is presented to demonstrate the effectiveness of the derived results.

Keywords: Exponential synchronization, stochastic analysis, chaotic neural networks, neutral type system.

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Authors: P. Pongsumpun, I.M. Tang

Abstract:

Plasmodium vivax malaria differs from P. falciparum malaria in that a person suffering from P. vivax infection can suffer relapses of the disease. This is due the parasite being able to remain dormant in the liver of the patients where it is able to re-infect the patient after a passage of time. During this stage, the patient is classified as being in the dormant class. The model to describe the transmission of P. vivax malaria consists of a human population divided into four classes, the susceptible, the infected, the dormant and the recovered. The effect of a time delay on the transmission of this disease is studied. The time delay is the period in which the P. vivax parasite develops inside the mosquito (vector) before the vector becomes infectious (i.e., pass on the infection). We analyze our model by using standard dynamic modeling method. Two stable equilibrium states, a disease free state E0 and an endemic state E1, are found to be possible. It is found that the E0 state is stable when a newly defined basic reproduction number G is less than one. If G is greater than one the endemic state E1 is stable. The conditions for the endemic equilibrium state E1 to be a stable spiral node are established. For realistic values of the parameters in the model, it is found that solutions in phase space are trajectories spiraling into the endemic state. It is shown that the limit cycle and chaotic behaviors can only be achieved with unrealistic parameter values.

Keywords: Equilibrium states, Hopf bifurcation, limit cyclebehavior, local stability, Plasmodium Vivax, time delay.

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Authors: S. Gherbi, F. Bouchareb

Abstract:

This paper deals with the novel intelligent bio-inspired control strategies, it presents a novel approach based on an optimal fuzzy immune PID parameters tuning, it is a combination of a PID controller, inspired by the human immune mechanism with fuzzy logic. Such controller offers more possibilities to deal with the delayed systems control difficulties due to the delay term. Indeed, we use an optimization approach to tune the four parameters of the controller in addition to the fuzzy function; the obtained controller is implemented in a modified Smith predictor structure, which is well known that it is the most efficient to the control of delayed systems. The application of the presented approach to control a three tank delay system shows good performances and proves the efficiency of the method.

Keywords: Delayed systems, Fuzzy Immune PID, Optimization, Smith predictor.

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