Search results for: Analog Integrated Circuit Design

Authors: Hee-Guk Chae, Bo-Bae Song, Kyoung-Il Do, Jeong-Yun Seo, Yong-Seo Koo

Abstract:

In this study, an improved Electrostatic Discharge (ESD) protection circuit with low trigger voltage and high holding voltage is proposed. ESD has become a serious problem in the semiconductor process because the semiconductor density has become very high these days. Therefore, much research has been done to prevent ESD. The proposed circuit is a stacked structure of the new unit structure combined by the Zener Triggering (SCR ZTSCR) and the High Holding Voltage SCR (HHVSCR). The simulation results show that the proposed circuit has low trigger voltage and high holding voltage. And the stack technology is applied to adjust the various operating voltage. As the results, the holding voltage is 7.7 V for 2-stack and 10.7 V for 3-stack.

Keywords: ESD, SCR, latch-up, power clamp, holding voltage.

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Authors: E. Farshidi

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In this paper, based on a novel synthesis, a set of new simplified circuit design to implement the linguistic-hedge operations for adjusting the fuzzy membership function set is presented. The circuits work in current-mode and employ floating-gate MOS (FGMOS) transistors that operate in weak inversion region. Compared to the other proposed circuits, these circuits feature severe reduction of the elements number, low supply voltage (0.7V), low power consumption (<200nW), immunity from body effect and wide input dynamic range (>60dB). In this paper, a set of fuzzy linguistic hedge circuits, including absolutely, very, much more, more, plus minus, more or less and slightly, has been implemented in 0.18 mm CMOS process. Simulation results by Hspice confirm the validity of the proposed design technique and show high performance of the circuits.

Keywords: Current-mode, Linguistic-Hedge, Fuzzy Logic, lowpower

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Authors: C. Matiz C., N. Olarte L., A. Rubiano F.

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This paper presents the design related to the electronic system design of the respiratory signal, including phases for processing, followed by the transmission and reception of this signal and finally display. The processing of this signal is added to the ECG and temperature sign, put up last year. Under this scheme is proposed that in future also be conditioned blood pressure signal under the same final printed circuit and worked.

Keywords: Conditioning, Respiratory Signal, Storage, Teleconsultation.

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Authors: Mamidi Ramakrishna Rao

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Doubly-fed induction generator (DFIG) is currently the choice for many wind turbines. These generators, when connected to the grid through a converter, is subjected to varied power system conditions like voltage variation, frequency variation, short circuit fault conditions, etc. Further, many countries like Canada, Germany, UK, Scotland, etc. have distinct grid codes relating to wind turbines. Accordingly, following the network faults, wind turbines have to supply a definite reactive current. To satisfy the requirements including reactive current capability, an optimum electrical design becomes a mandate for DFIG to function. This paper intends to optimize the equivalent circuit parameters of an electrical design for satisfactory DFIG performance. Direct search method has been used for optimization of the parameters. The variables selected include electromagnetic core dimensions (diameters and stack length), slot dimensions, radial air gap between stator and rotor and winding copper cross section area. Optimization for 2 MW DFIG has been executed separately for three objective functions - maximum reactive power capability (Case I), maximum efficiency (Case II) and minimum weight (Case III). In the optimization analysis program, voltage variations (10%), power factor- leading and lagging (0.95), speeds for corresponding to slips (-0.3 to +0.3) have been considered. The optimum designs obtained for objective functions were compared. It can be concluded that direct search method of optimization helps in determining an optimum electrical design for each objective function like efficiency or reactive power capability or weight minimization.

Keywords: Direct search, DFIG, equivalent circuit parameters, optimization.

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Authors: Arthur David Snider, Laiq Azam

Abstract:

The classic problem of recovering arbitrary values of a band-limited signal from its samples has an added complication in software radio applications; namely, the resampling calculations inevitably fold aliases of the analog signal back into the original bandwidth. The phenomenon is quantified by the spur-free dynamic range. We demonstrate how a novel application of the Remez (Parks- McClellan) algorithm permits optimal signal recovery and SFDR, far surpassing state-of-the-art resamplers.

Keywords: Sampling methods, Signal sampling, Digital radio, Digital-analog conversion.

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Authors: H. Loukil, A. Ben Atitallah, F. Ghozzi, M. A. Ben Ayed, N. Masmoudi

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In MPEG and H.26x standards, to eliminate the temporal redundancy we use motion estimation. Given that the motion estimation stage is very complex in terms of computational effort, a hardware implementation on a re-configurable circuit is crucial for the requirements of different real time multimedia applications. In this paper, we present hardware architecture for motion estimation based on "Full Search Block Matching" (FSBM) algorithm. This architecture presents minimum latency, maximum throughput, full utilization of hardware resources such as embedded memory blocks, and combining both pipelining and parallel processing techniques. Our design is described in VHDL language, verified by simulation and implemented in a Stratix II EP2S130F1020C4 FPGA circuit. The experiment result show that the optimum operating clock frequency of the proposed design is 89MHz which achieves 160M pixels/sec.

Keywords: SAD, FSBM, Hardware Implementation, FPGA.

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Authors: S. H. Iranmanesh, L. Aliabadi, A. Mollajan

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Integrated resilience engineering (IRE) is capable of returning banking systems to the normal state in extensive economic circumstances. In this study, information system of a large bank (with several branches) is assessed and optimized under severe economic conditions. Data envelopment analysis (DEA) models are employed to achieve the objective of this study. Nine IRE factors are considered to be the outputs, and a dummy variable is defined as the input of the DEA models. A standard questionnaire is designed and distributed among executive managers to be considered as the decision-making units (DMUs). Reliability and validity of the questionnaire is examined based on Cronbach's alpha and t-test. The most appropriate DEA model is determined based on average efficiency and normality test. It is shown that the proposed integrated design provides higher efficiency than the conventional RE design. Results of sensitivity and perturbation analysis indicate that self-organization, fault tolerance, and reporting culture respectively compose about 50 percent of total weight.

Keywords: Banking system, data envelopment analysis, DEA, integrated resilience engineering, IRE, performance evaluation, perturbation analysis.

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Authors: Ahtesham Javaid, Costin S. Bildea

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The design and plantwide control of an integrated plant where the endothermic 1,4-butanediol dehydrogenation and the exothermic furfural hydrogenation is simultaneously performed in a single reactor is studied. The reactions can be carried out in an adiabatic reactor using small hydrogen excess and with reduced parameter sensitivity. The plant is robust and flexible enough to allow different production rates of γ-butyrolactone and 2-methyl furan, keeping high product purities. Rigorous steady state and dynamic simulations performed in AspenPlus and AspenDynamics to support the conclusions.

Keywords: Dehydrogenation and hydrogenation, Reaction coupling, Design and control, Process integration.

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Authors: Jawad Ahmad, Hee-Jun Kim

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This paper describes the design of a voltage based maximum power point tracker (MPPT) for photovoltaic (PV) applications. Of the various MPPT methods, the voltage based method is considered to be the simplest and cost effective. The major disadvantage of this method is that the PV array is disconnected from the load for the sampling of its open circuit voltage, which inevitably results in power loss. Another disadvantage, in case of rapid irradiance variation, is that if the duration between two successive samplings, called the sampling period, is too long there is a considerable loss. This is because the output voltage of the PV array follows the unchanged reference during one sampling period. Once a maximum power point (MPP) is tracked and a change in irradiation occurs between two successive samplings, then the new MPP is not tracked until the next sampling of the PV array voltage. This paper proposes an MPPT circuit in which the sampling interval of the PV array voltage, and the sampling period have been shortened. The sample and hold circuit has also been simplified. The proposed circuit does not utilize a microcontroller or a digital signal processor and is thus suitable for low cost and low power applications.

Keywords: Maximum power point tracker, Sample and hold amplifier, Sampling interval, Sampling period.

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Authors: R. M. Siddiqui, D. Z. Moghaddam, T. R. Turlapati, S. H. Khan, I. Ul Ahad

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Quality of 2D and 3D cross-sectional images produce by Computed Tomography primarily depend upon the degree of precision of primary and secondary X-Ray intensity detection. Traditional method of primary intensity detection is apt to errors. Recently the X-Ray intensity measurement system along with smart X-Ray sensors is developed by our group which is able to detect primary X-Ray intensity unerringly. In this study a new smart X-Ray sensor is developed using Light-to-Frequency converter TSL230 from Texas Instruments which has numerous advantages in terms of noiseless data acquisition and transmission. TSL230 construction is based on a silicon photodiode which converts incoming X-Ray radiation into the proportional current signal. A current to frequency converter is attached to this photodiode on a single monolithic CMOS integrated circuit which provides proportional frequency count to incoming current signal in the form of the pulse train. The frequency count is delivered to the center of PICDEM FS USB board with PIC18F4550 microcontroller mounted on it. With highly compact electronic hardware, this Demo Board efficiently read the smart sensor output data. The frequency output approaches overcome nonlinear behavior of sensors with analog output thus un-attenuated X-Ray intensities could be measured precisely and better normalization could be acquired in order to attain high resolution.

Keywords: Computed tomography, detector technology, X-Ray intensity measurement

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Authors: Mehdi Hosseinzadeh, Somayyeh Jafarali Jassbi, Keivan Navi

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Residue Number System (RNS) is a modular representation and is proved to be an instrumental tool in many digital signal processing (DSP) applications which require high-speed computations. RNS is an integer and non weighted number system; it can support parallel, carry-free, high-speed and low power arithmetic. A very interesting correspondence exists between the concepts of Multiple Valued Logic (MVL) and Residue Number Arithmetic. If the number of levels used to represent MVL signals is chosen to be consistent with the moduli which create the finite rings in the RNS, MVL becomes a very natural representation for the RNS. There are two concerns related to the application of this Number System: reaching the most possible speed and the largest dynamic range. There is a conflict when one wants to resolve both these problem. That is augmenting the dynamic range results in reducing the speed in the same time. For achieving the most performance a method is considere named “One-Hot Residue Number System" in this implementation the propagation is only equal to one transistor delay. The problem with this method is the huge increase in the number of transistors they are increased in order m² . In real application this is practically impossible. In this paper combining the Multiple Valued Logic and One-Hot Residue Number System we represent a new method to resolve both of these two problems. In this paper we represent a novel design of an OHRNS-based adder circuit. This circuit is useable for Multiple Valued Logic moduli, in comparison to other RNS design; this circuit has considerably improved the number of transistors and power consumption.

Keywords: Computer Arithmetic, Residue Number System, Multiple Valued Logic, One-Hot, VLSI.

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Authors: Zina Saheb, Ezz El-Masry, Jean-François Bousquet

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This paper presents an enhanced efficiency simultaneous dual band energy harvesting system for wireless body area network. A bulk biasing is used to enhance the efficiency of the adapted rectifier design to reduce V_th of MOSFET. The presented circuit harvests the radio frequency (RF) energy from two frequency bands: 1 GHz and 2.4 GHz. It is designed with TSMC 65-nm CMOS technology and high quality factor dual matching network to boost the input voltage. Full circuit analysis and modeling is demonstrated. The simulation results demonstrate a harvester with an efficiency of 23% at 1 GHz and 46% at 2.4 GHz at an input power as low as -30 dBm.

Keywords: Energy harvester, simultaneous, dual band, CMOS, differential rectifier, voltage boosting, TSMC 65nm.

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Authors: Santanu Santra, Utpal Roy

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Quantum-dot Cellular Automata (QCA) is one of the most substitute emerging nanotechnologies for electronic circuits, because of lower power consumption, higher speed and smaller size in comparison with CMOS technology. The basic devices, a Quantum-dot cell can be used to implement logic gates and wires. As it is the fundamental building block on nanotechnology circuits. By applying XOR gate the hardware requirements for a QCA circuit can be decrease and circuits can be simpler in terms of level, delay and cell count. This article present a modest approach for implementing novel optimized XOR gate, which can be applied to design many variants of complex QCA circuits. Proposed XOR gate is simple in structure and powerful in terms of implementing any digital circuits. In order to verify the functionality of the proposed design some complex implementation of parity generator and parity checker circuits are proposed and simulating by QCA Designer tool and compare with some most recent design. Simulation results and physical relations confirm its usefulness in implementing every digital circuit.

Keywords: Clock, CMOS technology, Logic gates, QCA Designer, Quantum-dot Cellular Automata (QCA).

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Authors: G. Renuka Devi

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This paper analyzes the experimental investigation of indirect field oriented control of Field Programmable Gate Array (FPGA) based five-phase induction motor drive. A detailed d-q modeling and Space Vector Pulse Width Modulation (SVPWM) technique of 5-phase drive is elaborated in this paper. In the proposed work, the prototype model of 1 hp 5-phase Voltage Source Inverter (VSI) fed drive is implemented in hardware. SVPWM pulses are generated in FPGA platform through Very High Speed Integrated Circuit Hardware Description Language (VHDL) coding. The experimental results are observed under different loading conditions and compared with simulation results to validate the simulation model.

Keywords: Five-phase induction motor drive, field programmable gate array, indirect field oriented control, multi-phase, space vector pulse width modulation, voltage source inverter, very high speed integrated circuit hardware description language.

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Authors: Dr.K.Sri Rama Krishna, J.Lakshmi Narayana, Dr.L.Pratap Reddy

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Microstrip lines, widely used for good reason, are broadband in frequency and provide circuits that are compact and light in weight. They are generally economical to produce since they are readily adaptable to hybrid and monolithic integrated circuit (IC) fabrication technologies at RF and microwave frequencies. Although, the existing EM simulation models used for the synthesis and analysis of microstrip lines are reasonably accurate, they are computationally intensive and time consuming. Neural networks recently gained attention as fast and flexible vehicles to microwave modeling, simulation and optimization. After learning and abstracting from microwave data, through a process called training, neural network models are used during microwave design to provide instant answers to the task learned.This paper presents simple and accurate ANN models for the synthesis and analysis of Microstrip lines to more accurately compute the characteristic parameters and the physical dimensions respectively for the required design specifications.

Keywords: Neural Models, Algorithms, Microstrip Lines, Analysis, Synthesis

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Authors: Tien-Tung Chung, Chin-Te Lin, Chung-Yun Lee, Kuang-Chao Fan, Shou-Heng Chen

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This paper studies the optimum design for reducing optical loss of an 8x8 mechanical type optical switch due to the temperature change. The 8x8 optical switch is composed of a base, 8 input fibers, 8 output fibers, 3 fixed mirrors and 17 movable mirrors. First, an innovative switch configuration is proposed with thermal-compensated design. Most mechanical type optical switches have a disadvantage that their precision and accuracy are influenced by the ambient temperature. Therefore, the thermal-compensated design is to deal with this situation by using materials with different thermal expansion coefficients (α). Second, a parametric modeling program is developed to generate solid models for finite element analysis, and the thermal and structural behaviors of the switch are analyzed. Finally, an integrated optimum design program, combining Autodesk Inventor Professional software, finite element analysis software, and genetic algorithms, is developed for improving the thermal behaviors that the optical loss of the switch is reduced. By changing design parameters of the switch in the integrated design program, the final optimum design that satisfies the design constraints and specifications can be found.

Keywords: Optical switch, finite element analysis, thermal-compensated design, optimum design.

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Authors: Amit Sachan

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The purpose of this paper is to acquire the remote electrical parameters like Voltage, Current, and Frequency from Smart grid and send these real time values over GSM network using GSM Modem/phone along with temperature at power station. This project is also designed to protect the electrical circuitry by operating an Electromagnetic Relay. The Relay can be used to operate a Circuit Breaker to switch off the main electrical supply. User can send commands in the form of SMS messages to read the remote electrical parameters. This system also can automatically send the real time electrical parameters periodically (based on time settings) in the form of SMS. This system also send SMS alerts whenever the Circuit Breaker trips or whenever the Voltage or Current exceeds the predefined limits.

Keywords: GSM Modem, Initialization of ADC module of microcontroller, PIC-C compiler for Embedded C programming, PIC kit 2 programmer for dumping code into Micro controller, Express SCH for Circuit design, Proteus for hardware simulation.

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Authors: A. Kojah, A. Nacaroğlu

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Single phase transmission lines are used to transfer data or energy between two users. Transient conditions such as switching operations and short circuit faults cause the generation of the fluctuation on the waveform to be transmitted. Spatial voltage distribution on the single phase transmission line may change owing to the position and duration of the short circuit fault in the system. In this paper, the state space representation of the single phase transmission line for short circuit fault and for various types of terminations is given. Since the transmission line is modeled in time domain using distributed parametric elements, the mathematical representation of the event is given in state space (time domain) differential equation form. It also makes easy to solve the problem because of the time and space dependent characteristics of the voltage variations on the distributed parametrically modeled transmission line.

Keywords: Energy transmission, transient effects, transmission line, transient voltage, RLC short circuit, single phase.

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Authors: Ming-Chu Yin, Ping-An Du

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The shielding ability of a shielding cavity with an aperture will be greatly degraded at resonance frequencies, and the resonance modes and frequencies are affected by aperture resonances and aperture-cavity coupling, which are closely related with aperture sizes. The equivalent circuit method and numerical method of Transmission Line Matrix (TLM) are used to analyze the effects of aperture resonances and aperture-cavity coupling on the electromagnetic resonances of a cavity with an aperture in this paper. Both analytical and numerical results show that the resonance modes of a shielding cavity with an aperture consist of cavity resonance modes and aperture resonance modes, and the resonance frequencies will shift with the change of the aperture sizes because of the aperture resonances and aperture-cavity coupling. Variation rules of electromagnetic resonances with aperture sizes for a cavity with an aperture are given, which will be useful for design of shielding cavities.

Keywords: Aperture-cavity coupling, equivalent circuit method, resonances, shielding equipment.

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Authors: Yu-Sheng Lee, Qi An

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Offset mismatch, gain mismatch, and time-skew error between time-interleaved channels limit the performance of time-interleaved analog-to-digital converters (TIADC). This paper focused on the time-skew error. A new technique for calibrating time-skew error in M-channels TIADC is described, and simulation results are also presented.

Keywords: Calibration, time-skew error, time-interleavedanalog-to-digital converters.

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Authors: Emanuele Stomeo, Tatiana Kalganova, Cyrille Lambert

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Evolvable hardware (EHW) refers to a selfreconfiguration hardware design, where the configuration is under the control of an evolutionary algorithm (EA). A lot of research has been done in this area several different EA have been introduced. Every time a specific EA is chosen for solving a particular problem, all its components, such as population size, initialization, selection mechanism, mutation rate, and genetic operators, should be selected in order to achieve the best results. In the last three decade a lot of research has been carried out in order to identify the best parameters for the EA-s components for different “test-problems". However different researchers propose different solutions. In this paper the behaviour of mutation rate on (1+λ) evolution strategy (ES) for designing logic circuits, which has not been done before, has been deeply analyzed. The mutation rate for an EHW system modifies values of the logic cell inputs, the cell type (for example from AND to NOR) and the circuit output. The behaviour of the mutation has been analyzed based on the number of generations, genotype redundancy and number of logic gates used for the evolved circuits. The experimental results found provide the behaviour of the mutation rate to be used during evolution for the design and optimization of logic circuits. The researches on the best mutation rate during the last 40 years are also summarized.

Keywords: Evolvable hardware, mutation rate, evolutionarycomputation, design of logic circuit.

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Authors: Safyeh Soufian, Hoosein Naderi-Manesh, Abdoali Alizadeh, Mohammad Nabi Sarbolouki

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Aurein 1.2 is a 13-residue amphipathic peptide with antibacterial and anticancer activity. Aurein1.2 and its retro analog were synthesized to study the activity of the peptides in relation to their structure. The antibacterial test result showed the retro-analog is inactive. The secondary structural analysis by CD spectra indicated that both of the peptides at TFE/Water adopt alpha-helical conformation. MD simulation was performed on aurein 1.2 and retro-analog in water and TFE in order to analyse the factors that are involved in the activity difference between retro and the native peptide. The simulation results are discussed and validated in the light of experimental data from the CD experiment. Both of the peptides showed a relatively similar pattern for their hydrophobicity, hydrophilicity, solvent accessible surfaces, and solvent accessible hydrophobic surfaces. However, they showed different in directions of dipole moment of peptides. Also, Our results further indicate that the reversion of the amino acid sequence affects flexibility .The data also showed that factors causing structural rigidity may decrease the activity. Consequently, our finding suggests that in the case of sequence-reversed peptide strategy, one has to pay attention to the role of amino acid sequence order in making flexibility and role of dipole moment direction in peptide activity. KeywordsAntimicrobial peptides, retro, molecular dynamic, circular dichroism.

Keywords: Antimicrobial peptides, retro, molecular dynamic, circular dichroism.

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Authors: Chih-Chiang Hua, Yi-Hsiung Fang, Yuan-Jhen Siao

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A bridgeless boost (BLB) power factor correction (PFC) rectifier with hold-up time extension circuit is proposed in this paper. A full bridge rectifier is widely used in the front end of the ac/dc converter. Since the shortcomings of the full bridge rectifier, the bridgeless rectifier is developed. A BLB rectifier topology is utilized with the hold-up time extension circuit. Unlike the traditional hold-up time extension circuit, the proposed extension scheme uses fewer active switches to achieve a longer hold-up time. Simulation results are presented to verify the converter performance.

Keywords: Bridgeless boost, boost converter, power factor correction, hold-up time.

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Authors: Yukinari Minagi , Akinori Kanasugi

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This paper describes about dynamic reconfiguration to miniaturize arithmetic circuits in general-purpose processor. Dynamic reconfiguration is a technique to realize required functions by changing hardware construction during operation. The proposed arithmetic circuit performs floating-point arithmetic which is frequently used in science and technology. The data format is floating-point based on IEEE754. The proposed circuit is designed using VHDL, and verified the correct operation by simulations and experiments.

Keywords: dynamic reconfiguration, floating-point arithmetic, double precision, FPGA

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Authors: S. B. V. S. P. Sastry, V. V. S. Kesava Rao

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In this paper, x-ray impact of Taguchi method and design of experiment philosophy to project relationship between various factors leading to output yield strength of rebar is studied. In bar mill of an integrated steel plant, there are two production lines called as line 1 and line 2. The metallic properties e.g. yield strength of finished product of the same material is varying for a particular grade material when rolled simultaneously in both the lines. A study has been carried out to set the process parameters at optimal level for obtaining equal value of yield strength simultaneously for both lines.

Keywords: Bar mill, design of experiment, Taguchi, yield strength.

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Authors: Arup K. George, Wai Pan Chan, Zhi Hui Kong, Minkyu Je

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This paper describes a low-power second-order filter for a continuous-time chopper stabilized capacitive sensor interface, integrated with a fully differential post-CMOS surface-micromachined MEMS pressure sensor. The circuit uses a single-ended folded-cascode operational amplifier and two GM-C filters connected in cascade. The circuit is realized in a 0.18 μm CMOS process and offers differential to single-ended conversion. The novelty of the scheme is the cascade of two GM-C filters to achieve a second-order filter while minimizing power dissipation. The simulated filter cutoff frequency is 1.14 kHz at common-mode voltage 1.65 V, operating from a 3.3 V supply while dissipating 172μW of power. The filter achieves an operating range of 1V for an output load of 1MOhm and 10pF.

Keywords: Chopper Stabilization, MEMS, Pressure Sensors, Low Pass Filter

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Authors: Jinghao Sun, Guozhen Tan, Guangjian Hou

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The Chinese Postman Problem (CPP) is one of the classical problems in graph theory and is applicable in a wide range of fields. With the rapid development of hybrid systems and model based testing, Chinese Postman Problem with Time Dependent Travel Times (CPPTDT) becomes more realistic than the classical problems. In the literature, we have proposed the first integer programming formulation for the CPPTDT problem, namely, circuit formulation, based on which some polyhedral results are investigated and a cutting plane algorithm is also designed. However, there exists a main drawback: the circuit formulation is only available for solving the special instances with all circuits passing through the origin. Therefore, this paper proposes a new integer programming formulation for solving all the general instances of CPPTDT. Moreover, the size of the circuit formulation is too large, which is reduced dramatically here. Thus, it is possible to design more efficient algorithm for solving the CPPTDT in the future research.

Keywords: Chinese Postman Problem, Time Dependent, Integer Programming, Upper Bound Analysis.

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Authors: A. D. Parekh, P. R. Tailor

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The present work deals with thermodynamic analysis of cascade refrigeration system using ozone friendly refrigerants pair R507A and R23. R507A is azeotropic mixture composed of HFC refrigerants R125/R143a (50%/50% wt.). R23 is a single component HFC refrigerant used as replacement to CFC refrigerant R13 in low temperature applications. These refrigerants have zero ozone depletion potential and are non-flammable and as R507A an azeotropic mixture there is no problem of temperature glide. This study thermodynamically analyzed R507A-R23 cascade refrigeration system to optimize the design and operating parameters of the system. The design and operating parameters include: Condensing, evaporating, subcooling and superheating temperatures in the high temperature circuit, temperature difference in the cascade heat exchanger, Condensing, evaporating, subcooling and superheating temperatures in the low temperature circuit.

Keywords: COP, R507A, R23, cascade refrigeration system

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Authors: P. Prasad Rao, K. Lal Kishore

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Pipeline ADCs are becoming popular at high speeds and with high resolution. This paper discusses the options of number of bits/stage conversion techniques in pipelined ADCs and their effect on Area, Speed, Power Dissipation and Linearity. The basic building blocks like op-amp, Sample and Hold Circuit, sub converter, DAC, Residue Amplifier used in every stage is assumed to be identical. The sub converters use flash architectures. The design is implemented using 0.18

Keywords: 1.5 bits/stage, Conversion Frequency, Redundancy Switched Capacitor Sample and Hold Circuit

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Authors: Abdelmonaem Ayachi, Belgacem Hamdi

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This paper presents a fault-tolerant implementation for adder schemes using the dual duplication code. To prove the efficiency of the proposed method, the circuit is simulated in double pass transistor CMOS 32nm technology and some transient faults are voluntary injected in the Layout of the circuit. This fully differential implementation requires only 20 transistors which mean that the proposed design involves 28.57% saving in transistor count compared to standard CMOS technology.

Keywords: Semiconductors, digital electronics, double pass transistor technology, Full adder, fault tolerance.

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