Search results for: open circuit test

Authors: Wei Yi Lim, M. Annamalai Arasu, M. Kumarasamy Raja, Minkyu Je

Abstract:

In this paper, the design of wide-swing constant transconductance (g_m) bias circuit that generates bias voltage for low-noise amplifier (LNA) circuit design by using an off-chip resistor is demonstrated. The overall transconductance (G_m) generated by the constant g_m bias circuit is important to maintain the overall gain and noise figure of the LNA circuit. Therefore, investigation is performed to study the variation in G_m with process, temperature and supply voltage (PVT).  Temperature and supply voltage are swept from -10 °C to 85 °C and 1.425 V to 1.575 V respectively, while the process conditions are also varied to the extreme and the g_m variation is eventually concluded at between -3 % to 7 %. With the slight variation in the g_m value, through simulation, at worst condition of state SS, we are able to attain a conversion gain (S₂₁) variation of -3.10 % and a noise figure (NF) variation of 18.71 %. The whole constant g_m circuit draws approximately 100 µA from a 1.5V supply and is designed based on 0.13 µm CMOS process. 

Keywords: Transconductance, LNA, temperature, process.

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Authors: Min-ju Kwon, Chae-won Kim, Jeong-yun Seo, Hee-guk Chae, Yong-seo Koo

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In this paper, we presented the LDO (low-dropout) regulator which enhanced the PSRR by applying the constant current source generation technique through the BGR (Band Gap Reference) to form the noise sensing circuit. The current source through the BGR has a constant current value even if the applied voltage varies. Then, the noise sensing circuit, which is composed of the current source through the BGR, operated between the error amplifier and the pass transistor gate of the LDO regulator. As a result, the LDO regulator has a PSRR of -68.2 dB at 1k Hz, -45.85 dB at 1 MHz and -45 dB at 10 MHz. the other performance of the proposed LDO was maintained at the same level of the conventional LDO regulator.

Keywords: LDO regulator, noise sensing circuit, current reference, pass transistor.

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Authors: Ibrahim A. Khorwat, Nabil Naas

Abstract:

In this paper, we present a simple circuit for Manchester decoding and without using any complicated or programmable devices. This circuit can decode 90kbps of transmitted encoded data; however, greater than this transmission rate can be decoded if high speed devices were used. We also present a new method for extracting the embedded clock from Manchester data in order to use it for serial-to-parallel conversion. All of our experimental measurements have been done using simulation.

Keywords: High threshold level, level segregation, lowthreshold level, smoothing circuit synchronization..

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Authors: Abolhassan Razminia, Mohammad-Ali Sadrnia

Abstract:

Chua’s circuit is one of the most important electronic devices that are used for Chaos and Bifurcation studies. A central role of secure communication is devoted to it. Since the adaptive control is used vastly in the linear systems control, here we introduce a new trend of application of adaptive method in the chaos controlling field. In this paper, we try to derive a new adaptive control scheme for Chua’s circuit controlling because control of chaos is often very important in practical operations. The novelty of this approach is for sake of its robustness against the external perturbations which is simulated as an additive noise in all measured states and can be generalized to other chaotic systems. Our approach is based on Lyapunov analysis and the adaptation law is considered for the feedback gain. Because of this, we have named it NAFT (Nonlinear Adaptive Feedback Technique). At last, simulations show the capability of the presented technique for Chua’s circuit.

Keywords: Chaos, adaptive control, nonlinear control, Chua's circuit.

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Authors: Azza M. Anis, M. M. Abutaleb, Hani F. Ragai, M. I. Eladawy

Abstract:

This paper presents the characterization and design of a capacitive pressure sensor with LC-based 0.35 µm CMOS readout circuit. SPICE is employed to evaluate the characteristics of the readout circuit and COMSOL multiphysics structural analysis is used to simulate the behavior of the pressure sensor. The readout circuit converts the capacitance variation of the pressure sensor into the frequency output. Simulation results show that the proposed pressure sensor has output frequency from 2.50 to 2.28 GHz in a pressure range from 0.1 to 2 MPa almost linearly. The sensitivity of the frequency shift with respect to the applied pressure load is 0.11 GHz/MPa.

Keywords: CMOS LC-based oscillator, micro pressure sensor, silicon carbide

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Authors: R. Khaldi, N. Benamrouche, M. Bouheraoua

Abstract:

The ability to predict an accurate temperature distribution requires the knowledge of the losses, the thermal characteristics of the materials, and the cooling conditions, all of which are very difficult to quantify. In this paper, the impact of the effects of iron and copper losses are investigated separately and their effects on the heating in various points of the stator of an induction motor, is highlighted by using two simple tests. In addition, the effect of a defect, such as an open circuit in a phase of the stator, on the heating is also obtained by a no-load test. The squirrel cage induction motor is rated at 2.2 kW; 380 V; 5.2 A; Δ connected; 50 Hz; 1420 rpm and the class of insulation F, has been thermally tested under several load conditions. Several thermocouples were placed in strategic points of the stator.

Keywords: induction motor, temperature, heating, losses

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Authors: Yin Yin Phyo, Tun Lin Naing

Abstract:

This paper investigated the simulation of two-phase interleaved boost converter (IBC) with free and open-source software Scilab/Xcos. By using interleaved method, it can reduce current stress on components, components size, input current ripple and output voltage ripple. The required mathematical model is obtained from the equivalent circuit of its different four modes of operation for simulation. The equivalent circuits are considered in continuous conduction mode (CCM). The average values of the system variables are derived from the state-space equation to find the equilibrium point. Scilab is now becoming more and more popular among students, engineers and scientists because it is open-source software and free of charge. It gives a great convenience because it has powerful computation and simulation function. The waveforms of output voltage, input current and inductors current are obtained by using Scilab/Xcos.

Keywords: Two-phase boost converter, continuous conduction mode, free and open-source, interleaved method, dynamic simulation.

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Authors: Markus G. Ortner, Christian Magele, Klaus Krischan

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Knowledge about the magnetic quantities in a magnetic circuit is always of great interest. On the one hand, this information is needed for the simulation of a transformer. On the other hand, parameter studies are more reliable, if the magnetic quantities are derived from a well established model. One possibility to model the 3-phase transformer is by using a magnetic equivalent circuit (MEC). Though this is a well known system, it is often not an easy task to set up such a model for a large number of lumped elements which additionally includes the nonlinear characteristic of the magnetic material. Here we show the setup of a solver for a MEC and the results of the calculation in comparison to measurements taken. The equations of the MEC are based on a rearranged system of the nodal analysis. Thus it is possible to achieve a minimum number of equations, and a clear and simple structure. Hence, it is uncomplicated in its handling and it supports the iteration process. Additional helpful tasks are implemented within the solver to enhance the performance. The electric circuit is described by an electric equivalent circuit (EEC). Our results for the 3-phase transformer demonstrate the computational efficiency of the solver, and show the benefit of the application of a MEC.

Keywords: Inrush current, magnetic equivalent circuit, nonlinear behavior, transformer.

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Authors: Marcus Banda

Abstract:

In this article the influence of higher frequency effects in addition to a special damper design on the electrical behavior of a synchronous generator main exciter machine is investigated. On the one hand these machines are often highly stressed by harmonics from the bridge rectifier thus facing additional eddy current losses. On the other hand the switching may cause the excitation of dangerous voltage peaks in resonant circuits formed by the diodes of the rectifier and the commutation reactance of the machine. Therefore modern rotating exciters are treated like synchronous generators usually modeled with a second order equivalent circuit. Hence the well known Standstill Frequency Response Test (SSFR) method is applied to a test machine in order to determine parameters for the simulation. With these results it is clearly shown that higher frequencies have a strong impact on the conventional equivalent circuit model. Because of increasing field displacement effects in the stranded armature winding the sub-transient reactance is even smaller than the armature leakage at high frequencies. As a matter of fact this prevents the algorithm to find an equivalent scheme. This issue is finally solved using Laplace transfer functions fully describing the transient behavior at the model ports.

Keywords: Synchronous exciter machine, Linear transfer function, SSFR, Equivalent Circuit

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Authors: Qingjiang Li, Hui Xu, Haijun Liu, Xiaobo Tian

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To judge whether the memristor can be interpreted as the fourth fundamental circuit element, we propose a variable-relation criterion of fundamental circuit elements. According to the criterion, we investigate the nature of three fundamental circuit elements and the memristor. From the perspective of variables relation, the memristor builds a direct relation between the voltage across it and the current through it, instead of a direct relation between the magnetic flux and the charge. Thus, it is better to characterize the memristor and the resistor as two special cases of the same fundamental circuit element, which is the memristive system in Chua-s new framework. Finally, the definition of memristor is refined according to the difference between the magnetic flux and the flux linkage.

Keywords: Memristor, Fundamental, Variable-Relation Criterion, Memristive system

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Authors: Md. Asif Jahangir Chowdhury, Md. Shahriar Rizwan, M. S. Islam

Abstract:

In CMOS integrated circuit design there is a trade-off between static power consumption and technology scaling. Recently, the power density has increased due to combination of higher clock speeds, greater functional integration, and smaller process geometries. As a result static power consumption is becoming more dominant. This is a challenge for the circuit designers. However, the designers do have a few methods which they can use to reduce this static power consumption. But all of these methods have some drawbacks. In order to achieve lower static power consumption, one has to sacrifice design area and circuit performance. In this paper, we propose a new method to reduce static power in the CMOS VLSI circuit using Variable Body Biasing technique without being penalized in area requirement and circuit performance.

Keywords: variable body biasing, state saving technique, stack effect, dual V-th, static power reduction.

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Authors: J. Mohan, S. Maheshwari

Abstract:

A new circuit topology realizing a first-order currentmode all-pass filter is proposed using two dual-output second generation current conveyor and two passive components. The circuit possesses low-input and high-output impedance, which makes it ideal for current-mode systems. The proposed circuit is verified through PSPICE simulation results.

Keywords: active filter, all-pass filter, current-mode, current conveyor.

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Authors: Raj Kumar Rajak, Bharat Mishra

Abstract:

Bio-batteries represent an entirely new long-term, reasonable, reachable, and eco-friendly approach to generation of sustainable energy. In the present experimental work, we have studied the effect of the generation of power by bio-battery using different electrode pairs. The tests show that it is possible to generate electricity using cow’s urine as an electrolyte. C-Mg electrode pair shows maximum Voltage and Short Circuit Current (SCC), while C-Zn electrode pair shows less Open Circuit Voltage (OCV) and SCC. By the studies of cow urine and different electrodes, it is found that C-Zn electrode battery is more economical. The cow urine battery with C-Zn electrode provides maximum power (707.4 mW) and durability (up to 145 h). This result shows that the bio-batteries have the potency to full fill the need of electricity demand for lower energy equipment.

Keywords: Bio-batteries, cow’s urine, electrodes, non-conventional.

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Authors: Hee-Guk Chae, Bo-Bae Song, Kyoung-Il Do, Jeong-Yun Seo, Yong-Seo Koo

Abstract:

In this study, an improved Electrostatic Discharge (ESD) protection circuit with low trigger voltage and high holding voltage is proposed. ESD has become a serious problem in the semiconductor process because the semiconductor density has become very high these days. Therefore, much research has been done to prevent ESD. The proposed circuit is a stacked structure of the new unit structure combined by the Zener Triggering (SCR ZTSCR) and the High Holding Voltage SCR (HHVSCR). The simulation results show that the proposed circuit has low trigger voltage and high holding voltage. And the stack technology is applied to adjust the various operating voltage. As the results, the holding voltage is 7.7 V for 2-stack and 10.7 V for 3-stack.

Keywords: ESD, SCR, latch-up, power clamp, holding voltage.

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Authors: C. Ardil

Abstract:

This paper presents the open science philosophy and paradigm of scientific research on how to transform classical research and innovation approaches. Open science is the practice of providing free and unrestricted online access to the products of scholarly research. Open science advocates for the immediate and unrestricted online access to published, peer-reviewed research in digital format. Open science research is made available for free in perpetuity and includes guidelines and/or licenses that communicate how researchers and readers can share and re-use the digital content. The emergence of open science has changed the scholarly research and publishing landscape, making research more broadly accessible to academic and non-academic audiences alike. Consequently, open science philosophy and its practice are discussed to cover all aspects of cyberscience in the context of research and innovation excellence for the benefit of global society.

Keywords: Open science, open data, open access, cyberscience , cybertechnology.

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Authors: Aakash Subramanian, Vansh Pal Singh Makh, Abhijit Mitra

Abstract:

A new digital transceiver circuit for asynchronous frame detection is proposed where both the transmitter and receiver contain all digital components, thereby avoiding possible use of conventional devices like monostable multivibrators with unstable external components such as resistances and capacitances. The proposed receiver circuit, in particular, uses a combinational logic block yielding an output which changes its state as soon as the start bit of a new frame is detected. This, in turn, helps in generating an efficient receiver sampling clock. A data latching circuit is also used in the receiver to latch the recovered data bits in any new frame. The proposed receiver structure is also extended from 4- bit information to any general n data bits within a frame with a common expression for the output of the combinational logic block. Performance of the proposed hardware design is evaluated in terms of time delay, reliability and robustness in comparison with the standard schemes using monostable multivibrators. It is observed from hardware implementation that the proposed circuit achieves almost 33 percent speed up over any conventional circuit.

Keywords: Asynchronous Communication, Digital Detector, Combinational logic output, Sampling clock generator, Hardwareimplementation.

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Authors: Agord M. Pinto Jr., Yuzo Iano, Leandro T. Manera, Raphael R. N. Souza

Abstract:

This paper describes an optimization tool-based design strategy for a Current Mode Logic CML divide-by-2 circuit. Representing a building block for output frequency generation in a RFID protocol based-frequency synthesizer, the circuit was designed to minimize the power consumption for driving of multiple loads with unbalancing (at transceiver level). Implemented with XFAB XC08 180 nm technology, the circuit was optimized through MunEDA WiCkeD tool at Cadence Virtuoso Analog Design Environment ADE.

Keywords: Divide-by-2 circuit, CMOS technology, PLL phase locked-loop, optimization tool, CML current mode logic, RF transceiver.

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Authors: Anamika Jain, A. S. Thoke, R. N. Patel

Abstract:

This paper addresses the problems encountered by conventional distance relays when protecting double-circuit transmission lines. The problems arise principally as a result of the mutual coupling between the two circuits under different fault conditions; this mutual coupling is highly nonlinear in nature. An adaptive protection scheme is proposed for such lines based on application of artificial neural network (ANN). ANN has the ability to classify the nonlinear relationship between measured signals by identifying different patterns of the associated signals. One of the key points of the present work is that only current signals measured at local end have been used to detect and classify the faults in the double circuit transmission line with double end infeed. The adaptive protection scheme is tested under a specific fault type, but varying fault location, fault resistance, fault inception angle and with remote end infeed. An improved performance is experienced once the neural network is trained adequately, which performs precisely when faced with different system parameters and conditions. The entire test results clearly show that the fault is detected and classified within a quarter cycle; thus the proposed adaptive protection technique is well suited for double circuit transmission line fault detection & classification. Results of performance studies show that the proposed neural network-based module can improve the performance of conventional fault selection algorithms.

Keywords: Double circuit transmission line, Fault detection and classification, High impedance fault and Artificial Neural Network.

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Authors: C. Kalamani, V. Abishek Karthick, S. Anitha, K. Kavin Kumar

Abstract:

The fault tolerant system plays a crucial role in the critical applications which are being used in the present scenario. A fault may change the functionality of circuits. Aim of this paper is to design multiplier using fault tolerant hybrid full adder. Fault tolerant hybrid full adder is designed to check and repair any fault in the circuit using self-checking circuit and the self-repairing circuit. Further, the use of conventional logic circuits may result in more area, delay as well as power consumption. In order to reduce these parameters of the circuit, GDI (Gate Diffusion Input) techniques with less number of transistors are used compared to conventional full adder circuit. This reduces the area, delay and power consumption. The proposed method solves the major problems occurring in the most crucial and critical applications.

Keywords: Gate diffusion input, hybrid full adder, self-checking, fault tolerant.

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Authors: Ruilian Zhao, Shukai Zhang, Yan Wang, Weiwei Wang

Abstract:

Repairing broken test cases is an expensive and challenging task in evolving software systems. Although an automated repair technique with intent-preservation has been proposed, it does not take into account the association between test repairs and assertions, leading a large number of irrelevant candidates and decreasing the repair capability. This paper proposes a assertion-driven test repair approach. Furthermore, a intent-oriented priority criterion is raised to guide the repair candidate generation, making the repairs closer to the intent of the test. In more detail, repair targets are determined through post-dominance relations between assertions and the methods that directly cause compilation errors. Then, test repairs are generated from the target in a bottom-up way, guided by the the intent-oriented priority criteria. Finally, the generated repair candidates are prioritized to match the original test intent. The approach is implemented and evaluated on the benchmark of 4 open-source programs and 91 broken test cases. The result shows that the approach can fix 89% (81/91) broken test cases, which are more effective than the existing intent-preserved test repair approach, and our intent-oriented priority criteria work well.

Keywords: Test repair, test intent, software test, test case evolution.

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Authors: Guiheng Zhang, Wei Zhang, Jun Fu, Yudong Wang

Abstract:

A 900 MHz three-stage SiGe power amplifier (PA) with high power gain is presented in this paper. Volterra Series is applied to analyze nonlinearity sources of SiGe HBT device model clearly. Meanwhile, the influence of operating current to IMD3 is discussed. Then a β-helper current mirror bias circuit is applied to improve linearity, since the β-helper current mirror bias circuit can offer stable base biasing voltage. Meanwhile, it can also work as predistortion circuit when biasing voltages of three bias circuits are fine-tuned, by this way, the power gain and operating current of PA are optimized for best linearity. The three power stages which fabricated by 0.18 μm SiGe technology are bonded to the printed circuit board (PCB) to obtain impedances by Load-Pull system, then matching networks are done for best linearity with discrete passive components on PCB. The final measured three-stage PA exhibits 21.1 dBm of output power at 1 dB compression point (OP1dB) with power added efficiency (PAE) of 20.6% and 33 dB power gain under 3.3 V power supply voltage.

Keywords: High gain power amplifier, linearization bias circuit, SiGe HBT model, Volterra Series.

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Authors: Loke Mun Sei

Abstract:

Software testing has become a mandatory process in assuring the software product quality. Hence, test management is needed in order to manage the test activities conducted in the software test life cycle. This paper discusses on the challenges faced in the software test life cycle, and how the test processes and test activities, mainly on test cases creation, test execution, and test reporting is being managed and automated using several test automation tools, i.e. Jira, Robot Framework, and Jenkins.

Keywords: Test automation tools, test case, test execution, test reporting.

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Authors: Urva Maryam

Abstract:

Private data are more often breached by clever social engineering rather than exploiting technical vulnerabilities in the systems. Complete information security requires good data safety practices to go along with technical solutions. Hackers often begin their operation by simply sending spoofed emails or fraudulent URLs to their targets and trick them into providing sensitive information such as passwords or bank account details. This technique is called phishing. Phishing attacks can be launched on email addresses, open ports and unsecured web browsers. This study uses quantitative method of research to execute phishing experiments on the participants to test their response to the phishing emails. These experiments were run on Kali Linux distribution which came bundled with multiple open-source intelligence (OSINT) tools that were used in the study. The aim of this research is to see how successful phishing attacks can be launched using OSINT and to test the response of people to spoofed emails.

Keywords: OSINT, phishing, spear phishing, email spoofing, theHarvester, Maltego.

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Authors: A. Kojah, A. Nacaroğlu

Abstract:

Single phase transmission lines are used to transfer data or energy between two users. Transient conditions such as switching operations and short circuit faults cause the generation of the fluctuation on the waveform to be transmitted. Spatial voltage distribution on the single phase transmission line may change owing to the position and duration of the short circuit fault in the system. In this paper, the state space representation of the single phase transmission line for short circuit fault and for various types of terminations is given. Since the transmission line is modeled in time domain using distributed parametric elements, the mathematical representation of the event is given in state space (time domain) differential equation form. It also makes easy to solve the problem because of the time and space dependent characteristics of the voltage variations on the distributed parametrically modeled transmission line.

Keywords: Energy transmission, transient effects, transmission line, transient voltage, RLC short circuit, single phase.

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Authors: Sheela Tiwari, R. Naresh, R. Jha

Abstract:

The paper presents an investigation in to the effect of neural network predictive control of UPFC on the transient stability performance of a multimachine power system. The proposed controller consists of a neural network model of the test system. This model is used to predict the future control inputs using the damped Gauss-Newton method which employs ‘backtracking’ as the line search method for step selection. The benchmark 2 area, 4 machine system that mimics the behavior of large power systems is taken as the test system for the study and is subjected to three phase short circuit faults at different locations over a wide range of operating conditions. The simulation results clearly establish the robustness of the proposed controller to the fault location, an increase in the critical clearing time for the circuit breakers, and an improved damping of the power oscillations as compared to the conventional PI controller.

Keywords: Identification, Neural networks, Predictive control, Transient stability, UPFC.

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Authors: Chih-Chiang Hua, Yi-Hsiung Fang, Yuan-Jhen Siao

Abstract:

A bridgeless boost (BLB) power factor correction (PFC) rectifier with hold-up time extension circuit is proposed in this paper. A full bridge rectifier is widely used in the front end of the ac/dc converter. Since the shortcomings of the full bridge rectifier, the bridgeless rectifier is developed. A BLB rectifier topology is utilized with the hold-up time extension circuit. Unlike the traditional hold-up time extension circuit, the proposed extension scheme uses fewer active switches to achieve a longer hold-up time. Simulation results are presented to verify the converter performance.

Keywords: Bridgeless boost, boost converter, power factor correction, hold-up time.

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Authors: Yukinari Minagi , Akinori Kanasugi

Abstract:

This paper describes about dynamic reconfiguration to miniaturize arithmetic circuits in general-purpose processor. Dynamic reconfiguration is a technique to realize required functions by changing hardware construction during operation. The proposed arithmetic circuit performs floating-point arithmetic which is frequently used in science and technology. The data format is floating-point based on IEEE754. The proposed circuit is designed using VHDL, and verified the correct operation by simulations and experiments.

Keywords: dynamic reconfiguration, floating-point arithmetic, double precision, FPGA

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Authors: A. Hossain, M. A. Gafur, F. Gulshan, A. S. W. Kurny

Abstract:

Al-Si-Mg-Ni(-Cu) alloys are widely used in the automotive industry. They have the advantage of low weight associated with low coefficient of thermal expansion and excellent mechanical properties – mainly at high temperatures. The corrosion resistance of these alloys in coastal area, particularly sea water, however is not yet known. In this investigation, electrochemical impedance spectroscopy (EIS) and potentiodynamic polarization have been used to evaluate the corrosion resistance of Al-6Si-0.5Mg-2Ni (-2Cu) alloys in simulated sea water environments. The potentiodynamic polarization curves reveal that 2 wt% Cu content alloy (Alloy-2) is more prone to corrosion than the Cu free alloy (Alloy-1). But the EIS test results showed that corrosion resistance or charge transfer resistance (Rct) increases with the addition of Cu. Due to addition of Cu and thermal treatment, the magnitude of open circuit potential (OCP), corrosion potential (Ecorr) and pitting corrosion potential (Epit) of Al-6Si-0.5Mg-2Ni alloy in NaCl solution were shifted to the more noble direction.

Keywords: Al-Si alloy, potentiodynamic polarization, EIS, SEM.

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Authors: M. L. Akinyemi, T. J. Abodurin, A. O. Boyo, J. A. O. Olugbuyiro

Abstract:

Organic dyes from Cola acuminata (C. acuminata), Lupinus arboreus (L. arboreus) and Bougainvillea spectabilis (B. spectabilis) leaves and their mixtures were used as sensitizers to manufacture dye-sensitized solar cells (DSSC). Photoelectric measurements of C. acuminata showed a short circuit current (J_sc) of 0.027 mA/ cm², 0.026 mA/ cm² and 0.018 mA/ cm² with a mixture of mercury chloride and iodine (Hgcl₂ + I); potassium bromide and iodine (KBr + I); and potassium chloride and iodine (KCl + I) respectively. The open circuit voltage (V_oc) was 24 mV, 25 mV and 20 mV for the three dyes respectively. L. arboreus had J_sc of 0.034 mA/ cm², 0.021 mA/ cm² and 0.013 mA/ cm²; and corresponding V_oc of 28 mV, 14.2 mV and 15 mV for the three electrolytes respectively. B. spectabilis recorded J_sc 0.023 mA/ cm², 0.026 mA/ cm² and 0.015 mA/ cm²; and corresponding V_oc values of 6.2 mV, 14.3 mV and 4.0 mV for the three electrolytes respectively. It was observed that the fill factor (FF) was 0.140 for C. acuminata, 0.3198 for L. arboreus and 0.1138 for B. spectabilis. Internal conversions of 0.096%, 0.056% and 0.063% were recorded for three dyes when combined with (KBr + I) electrolyte. The internal efficiency of C. acuminata DSSC was highest in value.

Keywords: Dye-sensitized Solar Cells, Organic dye, C. acuminate, L. arboreus, B. spectabilis, Dye Mixture.

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Authors: Hossein Sahoolizadeh, Alishir Moradi Kordalivand, Zargham Heidari

Abstract:

In first stage of each microwave receiver there is Low Noise Amplifier (LNA) circuit, and this stage has important rule in quality factor of the receiver. The design of a LNA in Radio Frequency (RF) circuit requires the trade-off many importance characteristics such as gain, Noise Figure (NF), stability, power consumption and complexity. This situation Forces desingners to make choices in the desing of RF circuits. In this paper the aim is to design and simulate a single stage LNA circuit with high gain and low noise using MESFET for frequency range of 5 GHz to 6 GHz. The desing simulation process is down using Advance Design System (ADS). A single stage LNA has successfully designed with 15.83 dB forward gain and 1.26 dB noise figure in frequency of 5.3 GHz. Also the designed LNA should be working stably In a frequency range of 5 GHz to 6 GHz.

Keywords: Advance Design System, Low Noise Amplifier, Radio Frequency, Noise Figure.

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