Search results for: Bridge Circuit

Authors: Gianluca Cornetta, Abdellah Touhafi, David J. Santos, Jose Manuel Vazquez

Abstract:

A direct downconversion receiver implemented in 0.13 μm 1P8M process is presented. The circuit is formed by a single-end LNA, an active balun for conversion into balanced mode, a quadrature double-balanced passive switch mixer and a quadrature voltage-controlled oscillator. The receiver operates in the 2.4 GHz ISM band and complies with IEEE 802.15.4 (ZigBee) specifications. The circuit exhibits a very low noise figure of only 2.27 dB and dissipates only 14.6 mW with a 1.2 V supply voltage and is hence suitable for low-power applications.

Keywords: LNA, Active Balun, Passive Mixer, VCO, IEEE 802.15.4(ZigBee).

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Authors: B. G. Sheeparamatti, J. S. Kadadevarmath

Abstract:

Microcantilevers are the basic MEMS devices, which can be used as sensors, actuators and electronics can be easily built into them. The detection principle of microcantilever sensors is based on the measurement of change in cantilever deflection or change in its resonance frequency. The objective of this work is to explore the analogies between mechanical and electrical equivalent of microcantilever beams. Normally scientists and engineers working in MEMS use expensive software like CoventorWare, IntelliSuite, ANSYS/Multiphysics etc. This paper indicates the need of developing electrical equivalent of the MEMS structure and with that, one can have a better insight on important parameters, and their interrelation of the MEMS structure. In this work, considering the mechanical model of microcantilever, equivalent electrical circuit is drawn and using force-voltage analogy, it is analyzed with circuit simulation software. By doing so, one can gain access to powerful set of intellectual tools that have been developed for understanding electrical circuits Later the analysis is performed using ANSYS/Multiphysics - software based on finite element method (FEM). It is observed that both mechanical and electrical domain results for a rectangular microcantlevers are in agreement with each other.

Keywords: Electrical equivalent circuit analogy, FEM analysis, micro cantilevers, micro sensors.

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Authors: V. Pizarro-Carmona, S. Castano-Solis, M. Cortés-Carmona, J. Fraile-Ardanuy, D. Jimenez-Bermejo

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The purpose of this article is to optimize the Equivalent Electric Circuit Model (EECM) of different orders to obtain greater precision in the modeling of Li-ion battery packs. Optimization includes considering circuits based on 1RC, 2RC and 3RC networks, with a dependent voltage source and a series resistor. The parameters are obtained experimentally using tests in the time domain and in the frequency domain. Due to the high non-linearity of the behavior of the battery pack, Genetic Algorithm (GA) was used to solve and optimize the parameters of each EECM considered (1RC, 2RC and 3RC). The objective of the estimation is to minimize the mean square error between the measured impedance in the real battery pack and those generated by the simulation of different proposed circuit models. The results have been verified by comparing the Nyquist graphs of the estimation of the complex impedance of the pack. As a result of the optimization, the 2RC and 3RC circuit alternatives are considered as viable to represent the battery behavior. These battery pack models are experimentally validated using a hardware-in-the-loop (HIL) simulation platform that reproduces the well-known New York City cycle (NYCC) and Federal Test Procedure (FTP) driving cycles for electric vehicles. The results show that using GA optimization allows obtaining EECs with 2RC or 3RC networks, with high precision to represent the dynamic behavior of a battery pack in vehicular applications.

Keywords: Li-ion battery packs modeling optimized, EECM, GA, electric vehicle applications.

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Authors: Bo Bae Song, Byung Seok Lee, Hyun Young Kim, Chung Kwang Lee, Yong Seo Koo

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This paper proposed a silicon controller rectifier (SCR) based ESD protection device to protect low voltage ESD for integrated circuit. The proposed ESD protection device has low trigger voltage and high holding voltage compared with conventional SCR-based ESD protection devices. The proposed ESD protection circuit is verified and compared by TCAD simulation. This paper verified effective low voltage ESD characteristics with low trigger voltage of 5.79V and high holding voltage of 3.5V through optimization depending on design variables (D1, D2, D3 and D4).

Keywords: ESD, SCR, Holding voltage, Latch-up.

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Authors: Ho-Young Kim, Jae-Hoon Lee, Do-Kyu Hwang, Im-Jong Kwahk, Tae-Hoon Kim, Seung-Hoon Lee

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Hollow section for bridge columns has some advantages. However, current seismic design codes do not provide design regulations for hollow bridge piers. There have been many experimental studied for hollow reinforced concrete piers in the world. But, Study for hollow section for bridge piers in Korea has been begun with approximately 2000s. There has been conducted experimental study for hollow piers of flexural controlled sections by Yeungnam University, Sung kyunkwan University, Korea Expressway Corporation in 2009. This study concluded that flexural controlled sections for hollow piers showed the similar behavior to solid sections. And there have been conducted experimental study for hollow piers of compression controlled sections by Yeungnam University, Korea Institute of Construction Technology in 2012. This study concluded that compression controlled sections for hollow piers showed compression fracture of concrete in inside wall face. Samsung Construction & Trading Corporation has been conducted study with Yeungnam University for reduce the quantity of reinforcement details about hollow piers. Reduce the quantity of reinforcement details are triangular cross tie. This study concluded that triangular reinforcement details showed the similar behavior as compared with existing reinforcement details.

Keywords: Hollow pier, flexural controlled section, compression controlled section, reduce the quantity of reinforcement details.

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Authors: Rahul Bansal, Sudipta Majumdar

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This paper presents the closed form nonlinear expressions of bipolar junction transistor (BJT) differential amplifier (DA) using perturbation method. Circuit equations have been derived using Kirchhoff’s voltage law (KVL) and Kirchhoff’s current law (KCL). The perturbation method has been applied to state variables for obtaining the linear and nonlinear terms. The implementation of the proposed method is simple. The closed form nonlinear expressions provide better insights of physical systems. The derived equations can be used for signal processing applications.

Keywords: Differential amplifier, perturbation method, Taylor series.

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Authors: Vijay Janyani, Trevor M. Benson, Ana Vukovic

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A time-domain numerical model within the framework of transmission line modeling (TLM) is developed to simulate electromagnetic pulse propagation inside multiple microcavities forming photonic crystal (PhC) structures. The model developed is quite general and is capable of simulating complex electromagnetic problems accurately. The field quantities can be mapped onto a passive electrical circuit equivalent what ensures that TLM is provably stable and conservative at a local level. Furthermore, the circuit representation allows a high level of hybridization of TLM with other techniques and lumped circuit models of components and devices. A photonic crystal structure formed by rods (or blocks) of high-permittivity dieletric material embedded in a low-dielectric background medium is simulated as an example. The model developed gives vital spatio-temporal information about the signal, and also gives spectral information over a wide frequency range in a single run. The model has wide applications in microwave communication systems, optical waveguides and electromagnetic materials simulations.

Keywords: Computational Electromagnetics, Numerical Simulation, Transmission Line Modeling.

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Authors: P. Prasad Rao, K. Lal Kishore

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Pipeline ADCs are becoming popular at high speeds and with high resolution. This paper discusses the options of number of bits/stage conversion techniques in pipelined ADCs and their effect on Area, Speed, Power Dissipation and Linearity. The basic building blocks like op-amp, Sample and Hold Circuit, sub converter, DAC, Residue Amplifier used in every stage is assumed to be identical. The sub converters use flash architectures. The design is implemented using 0.18

Keywords: 1.5 bits/stage, Conversion Frequency, Redundancy Switched Capacitor Sample and Hold Circuit

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Authors: Abdelmonaem Ayachi, Belgacem Hamdi

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This paper presents a fault-tolerant implementation for adder schemes using the dual duplication code. To prove the efficiency of the proposed method, the circuit is simulated in double pass transistor CMOS 32nm technology and some transient faults are voluntary injected in the Layout of the circuit. This fully differential implementation requires only 20 transistors which mean that the proposed design involves 28.57% saving in transistor count compared to standard CMOS technology.

Keywords: Semiconductors, digital electronics, double pass transistor technology, Full adder, fault tolerance.

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Authors: Shobha Sharma, Amita Dev

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Data driven dynamic logic is the high speed dynamic circuit with low area. The clock of the dynamic circuit is removed and data drives the circuit instead of clock for precharging purpose. This data driven dynamic nand gate is given static forward substrate biasing of Vsupply/2 as well as the substrate bias is connected to the input data, resulting in dynamic substrate bias. The dynamic substrate bias gives the shortest propagation delay with a penalty on the power dissipation. Propagation delay is reduced by 77.8% compared to the normal reverse substrate bias Data driven dynamic nand. Also dynamic substrate biased D3nand’s propagation delay is reduced by 31.26% compared to data driven dynamic nand gate with static forward substrate biasing of Vdd/2. This data driven dynamic nand gate with dynamic body biasing gives us the highest speed with no area penalty and finds its applications where power penalty is acceptable. Also combination of Dynamic and static Forward body bias can be used with reduced propagation delay compared to static forward biased circuit and with comparable increase in an average power. The simulations were done on hspice simulator with 22nm High-k metal gate strained Si technology HP models of Arizona State University, USA.

Keywords: Data driven nand gate, dynamic substrate biasing, nand gate, static substrate biasing.

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Authors: S. J. Arif

Abstract:

In the presented technique, a simple method is given for accurate measurement and control of power frequency deviation. The sinusoidal signal for which the frequency deviation measurement is required is transformed to a low voltage level and passed through a zero crossing detector to convert it into a pulse train. Another stable square wave signal of 10 KHz is obtained using a crystal oscillator and decade dividing assemblies (DDA). These signals are combined digitally and then passed through decade counters to give a unique combination of pulses or levels, which are further encoded to make them equally suitable for both control applications and display units. The developed circuit using discrete components has a resolution of 0.5 Hz and completes measurement within 20 ms. The realized circuit is simulated and synthesized using Verilog HDL and subsequently implemented on FPGA. The results of measurement on FPGA are observed on a very high resolution logic analyzer. These results accurately match the simulation results as well as the results of same circuit implemented with discrete components. The proposed system is suitable for accurate measurement and control of power frequency deviation.

Keywords: Digital encoder for frequency measurement, frequency deviation measurement, measurement and control systems, power systems.

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Authors: Fei Long Wei, Hua Yang, Hai Tao Zhang, Zhou Ping Yin

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In this study, an local invariant generalized Houghtransform (LI-GHT) method is proposed for integrated circuit (IC) visual positioning. The original generalized Hough transform (GHT) is robust to external noise; however, it is not suitable for visual positioning of IC chips due to the four-dimensionality (4D) of parameter space which leads to the substantial storage requirement and high computational complexity. The proposed LI-GHT method can reduce the dimensionality of parameter space to 2D thanks to the rotational invariance of local invariant geometric feature and it can estimate the accuracy position and rotation angle of IC chips in real-time under noise and blur influence. The experiment results show that the proposed LI-GHT can estimate position and rotation angle of IC chips with high accuracy and fast speed. The proposed LI-GHT algorithm was implemented in IC visual positioning system of radio frequency identification (RFID) packaging equipment.

Keywords: Integrated Circuit Visual Positioning, Generalized Hough Transform, Local invariant Generalized Hough Transform, ICpacking equipment.

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Authors: Julio Cesar Lopes de Oliveira, Carlos Henrique Gonc¸alves Treviso

Abstract:

The shortage of the automotive market in relation to options for sources of high power car audio systems, led to development of this work. Thus, we developed a source with stabilized voltage with 4320 W effective power. Designed to the voltage of 14.4 V and a choice of two currents: 30 A load option in battery banks and 300 A at full load. This source can also be considered as a source of general use dedicated commercial with a simple control circuit in analog form based on discrete components. The assembly of power circuit uses a methodology for higher power than the initially stipulated.

Keywords: DC-DC power converters, converters, power convertion, pulse width modulation converters.

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Authors: Mehdi Hosseinzadeh, Somayyeh Jafarali Jassbi, Keivan Navi

Abstract:

Residue Number System (RNS) is a modular representation and is proved to be an instrumental tool in many digital signal processing (DSP) applications which require high-speed computations. RNS is an integer and non weighted number system; it can support parallel, carry-free, high-speed and low power arithmetic. A very interesting correspondence exists between the concepts of Multiple Valued Logic (MVL) and Residue Number Arithmetic. If the number of levels used to represent MVL signals is chosen to be consistent with the moduli which create the finite rings in the RNS, MVL becomes a very natural representation for the RNS. There are two concerns related to the application of this Number System: reaching the most possible speed and the largest dynamic range. There is a conflict when one wants to resolve both these problem. That is augmenting the dynamic range results in reducing the speed in the same time. For achieving the most performance a method is considere named “One-Hot Residue Number System" in this implementation the propagation is only equal to one transistor delay. The problem with this method is the huge increase in the number of transistors they are increased in order m² . In real application this is practically impossible. In this paper combining the Multiple Valued Logic and One-Hot Residue Number System we represent a new method to resolve both of these two problems. In this paper we represent a novel design of an OHRNS-based adder circuit. This circuit is useable for Multiple Valued Logic moduli, in comparison to other RNS design; this circuit has considerably improved the number of transistors and power consumption.

Keywords: Computer Arithmetic, Residue Number System, Multiple Valued Logic, One-Hot, VLSI.

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Authors: Syed Javed Arif, Mohd Ayyub Khan, Saleem Anwar Khan

Abstract:

In this paper, a simple method is presented for measurement of power frequency deviations. A phase locked loop (PLL) is used to multiply the signal under test by a factor of 100. The number of pulses in this pulse train signal is counted over a stable known period, using decade driving assemblies (DDAs) and flip-flops. These signals are combined using logic gates and then passed through decade counters to give a unique combination of pulses or levels, which are further encoded. These pulses are equally suitable for both control applications and display units. The experimental circuit developed gives a resolution of 1 Hz within the measurement period of 20 ms. The proposed circuit is also simulated in Verilog Hardware Description Language (VHDL) and implemented using Field Programing Gate Arrays (FPGAs). A Mixed signal Oscilloscope (MSO) is used to observe the results of FPGA implementation. These results are compared with the results of the proposed circuit of discrete components. The proposed system is useful for frequency deviation measurement and control in power systems.

Keywords: Frequency measurement, digital control, phase locked loop, encoding, Verilog HDL.

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Authors: Janisse Vivas, Doug Stead, Davide Elmo, Charles Hunt

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This paper presents the results of a study on the influence of varying percentages of rock bridges along a basal surface defining a biplanar failure mode. A pseudo-coupled-hydromechanical brittle fracture analysis is adopted using the state-of-the-art code Slope Model. Model results show that rock bridge failure is strongly influenced by the incorporation of groundwater pressures. The models show that groundwater pressure can promote total failure of a 5% rock bridge along the basal surface. Once the percentage of the rock bridges increases to 10 and 15%, although, the rock bridges are broken, full interconnection of the surface defining the basal surface of the biplanar mode does not occur. Increased damage is caused when the rock bridge is located at the daylighting end of the basal surface in proximity to the blast damage zone. As expected, some cracking damage is experienced in the blast damage zone, where properties representing a good quality controlled damage blast technique were assumed. Model results indicate the potential increase of permeability towards the blast damage zone.

Keywords: Slope model, lattice spring, blasting damage zone.

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Authors: Ali H. Mahfouz, Hossam E. M.Sallam, Abdulwali Wazir, Hamod H. Kharezi

Abstract:

The soil profile at site of the bridge project includes soft fine grained soil layer located between 5.0 m to 11.0 m in depth, it has high water content, low SPT no., and low bearing capacity. The clay layer induces high settlement due to surcharge application of earth embankment at ramp T1, ramp T2, and ramp T3 especially at heights from 9m right 3m. Calculated settlement for embankment heights less than 3m may be accepted regarding Saudi Code for soil and foundation. The soil and groundwater at the project site comprise high contents of sulfates and chlorides of high aggressively on concrete and steel bars, respectively. Regarding results of the study, it has been recommended to use stone column piles or new technology named PCC piles as soil improvement to improve the bearing capacity of the weak layer. The new technology is cast in-situ thin wall concrete pipe piles (PCC piles), it has economically advantageous and high workability. The technology can save time of implementation and cost of application is almost 30% of other types of piles.

Keywords: Soft foundation soil, bearing capacity, bridge ramps, soil improvement, PCC piles.

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Authors: Wang Zhulin, Min Fuhong, Peng Guangya, Wang Yaoda, Cao Yi

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In this paper, a magnetron memristor model based on hyperbolic sine function is presented and the correctness proved by studying the trajectory of its voltage and current phase, and then a memristor chaotic system with the memristor model is presented. The phase trajectories and the bifurcation diagrams and Lyapunov exponent spectrum of the magnetron memristor system are plotted by numerical simulation, and the chaotic evolution with changing the parameters of the system is also given. The paper includes numerical simulations and mathematical model, which confirming that the system, has a wealth of dynamic behavior.

Keywords: Memristor, chaotic circuit, dynamical behavior, chaotic system.

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Authors: Neeraj K. Chasta

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This paper presents an idea for analog current comparison which compares input signal and reference currents with high speed and accuracy. Proposed circuit utilizes amplification properties of common gate configuration, where voltage variations of input current are amplified and a compared output voltage is developed. Cascaded inverter stages are used to generate final CMOS compatible output voltage. Power consumption of circuit can be controlled by the applied gate bias voltage. The comparator is designed and studied at 180nm CMOS process technology for a supply voltage of 3V.

Keywords: Current Mode, Comparator, High Resolution, High Speed.

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Authors: J. I. Aguwa, S. Sadiku, M. Abdullahi

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This study examined the structural reliability of the Nigerian grown Opepe timber as bridge beam material. The strength of a particular specie of timber depends so much on some factors such as soil and environment in which it is grown. The steps involved are collection of the Opepe timber samples, seasoning/preparation of the test specimens, determination of the strength properties/statistical analysis, development of a computer programme in FORTRAN language and finally structural reliability analysis using FORM 5 software. The result revealed that the Nigerian grown Opepe is a reliable and durable structural bridge beam material for span of 5000mm, depth of 400mm, breadth of 250mm and end bearing length of 150mm. The probabilities of failure in bending parallel to the grain, compression perpendicular to the grain, shear parallel to the grain and deflection are 1.61 x 10^-7, 1.43 x 10^-8, 1.93 x 10^-4 and 1.51 x 10^-15 respectively. The paper recommends establishment of Opepe plantation in various Local Government Areas in Nigeria for structural applications such as in bridges, railway sleepers, generation of income to the nation as well as creating employment for the numerous unemployed youths.

Keywords: Bending and deflection, Bridge beam, Compression, Nigerian Opepe, Shear, Structural reliability.

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Authors: Amit Kumar Gautam, Sudipta Majumdar

Abstract:

This paper presents parameter estimation of a single-phase rectifier using extended Kalman filter (EKF). The state space model has been obtained using Kirchhoff’s current law (KCL) and Kirchhoff’s voltage law (KVL). The capacitor voltage and diode current of the circuit have been estimated using EKF. Simulation results validate the better accuracy of the proposed method as compared to the least mean square method (LMS). Further, EKF has the advantage that it can be used for nonlinear systems.

Keywords: Extended Kalman filter, parameter estimation, single phase rectifier, state space modelling.

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Authors: Chih Chin Yang, Chih Yu Lee, Jing Yi Wang, Mei Zhen Xue, Chia Yueh Wu

Abstract:

A well-defined frequency multiple dividing (FMD) circuit using a resonant model is presented in this research. The basic component of a frequency multiple divider as used in a resonant model is established by compositing a well-defined resonant effect of negative differential resistance (NDR) characteristics which possesses a wider operational region and high operational current at a bias voltage of about 1.15 V. The resonant model is then applied in the frequency dividing circuit with the above division ratio (R_D) of 200 at the signal input of middle frequency. The division ratio also exists at the input of a low frequency signal.

Keywords: Divider, frequency, resonant model.

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Authors: Cheng Zhang, James Marco, Walid Allafi, Truong Q. Dinh, W. D. Widanage

Abstract:

Equivalent circuit models (ECMs) are widely used in battery management systems in electric vehicles and other battery energy storage systems. The battery dynamics and the model parameters vary under different working conditions, such as different temperature and state of charge (SOC) levels, and therefore online parameter identification can improve the modelling accuracy. This paper presents a way of online ECM parameter identification using a continuous time (CT) estimation method. The CT estimation method has several advantages over discrete time (DT) estimation methods for ECM parameter identification due to the widely separated battery dynamic modes and fast sampling. The presented method can be used for online SOC estimation. Test data are collected using a lithium ion cell, and the experimental results show that the presented CT method achieves better modelling accuracy compared with the conventional DT recursive least square method. The effectiveness of the presented method for online SOC estimation is also verified on test data.

Keywords: Equivalent circuit model, continuous time domain estimation, linear integral filter method, parameter and SOC estimation, recursive least square.

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Authors: Mazhar B. Tayel, Amr H. Yassin

Abstract:

A proposed small-signal model parameters for a pseudomorphic high electron mobility transistor (PHEMT) is presented. Both extrinsic and intrinsic circuit elements of a smallsignal model are determined using genetic algorithm (GA) as a stochastic global search and optimization tool. The parameters extraction of the small-signal model is performed on 200-μm gate width AlGaAs/InGaAs PHEMT. The equivalent circuit elements for a proposed 18 elements model are determined directly from the measured S- parameters. The GA is used to extract the parameters of the proposed small-signal model from 0.5 up to 18 GHz.

Keywords: PHEMT, Genetic Algorithms, small signal modeling, optimization.

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Authors: Joshi Manohar. V., Sujatha. P., Anjaneyulu K. S. R

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The range of the output power is a very important and evident limitation of two-level inverters. In order to overcome this disadvantage, multilevel inverters are introduced. Recently, Cascade H-Bridge inverters have emerged as one of the popular converter topologies used in numerous industrial applications. The modulation switching strategies such as phase shifted carrier based Pulse Width Modulation (PWM) technique and Stair case modulation with Selective Harmonic Elimination (SHE) PWM technique are generally used. NR method is used to solve highly non linear transcendental equations which are formed by SHEPWM method. Generally NR method has a drawback of requiring good initial guess but in this paper a new approach is implemented for NR method with any random initial guess. A three phase CHB 11-level inverter is chosen for analysis. MATLAB/SIMULINK programming environment and harmonic profiles are compared. Finally this paper presents a method at fundamental switching frequency with least % THDV.

Keywords: Cascade H-bridge 11- level Inverter, NR method, Phase shifted carrier based pulse width modulation (PSCPWM), Selective Harmonic Elimination Pulse Width Modulation (SHEPWM), Total Harmonic Distortion (%THDv).

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Authors: Binod Kumar Saha

Abstract:

The objective of the present paper is a numerical analysis of the flow forces acting on spool surfaces of a pressure regulated valve. The transient, compressible and turbulent flow structures inside the valve are simulated using ANSYS FLUENT coupled with a special UDF. Here, valve inlet pressure is varied in a stepwise manner. For every value of inlet pressure, transient analysis leads to a quasi-static flow through the valve. Spool forces are calculated based on different pressures at inlet. From this information of spool forces, pressure characteristic of the passive control circuit has been derived.

Keywords: Pressure Regulating Valve, Spool Opening, Spool Movement, Force Balance, CFD.

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Authors: D. Y. Bawa, M. I. Ribah, I. S. Jega, V. O. Oyedepo

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This study was conducted to determine the physicochemical characteristics and heavy metal concentration (Cadmium (Cd), Copper (Cu), Iron (Fe), Lead (Pb) and Zinc (Zn)) in freshwater from Jega river. 30 water samples were collected in two 1-liter sterile plastic containers from three designated sampling points, namely; Station A (before the bridge; upstream), Station B (at the bridge where human activities such as washing of cars, motorbike, clothes, bathing and other household materials are concentrated), Station C (after the bridge; downstream) fortnightly, between March and July 2014. Results indicated that the highest pH mean value of 7.08 ± 1.12 was observed in station C, the highest conductivity with the mean 58.75 ± 7.87 µs/cm was observed at station A, the highest mean value of the water total hardness was observed at station A (54 ± 16.11 mg/L), the highest mean value of nitrate deposit was observed in station A (1.66 ± 1.33 mg/L), the highest mean value of alkalinity was observed at station B (51.33 ± 6.66 mg/L) and the highest mean (39.56 ± 3.24 mg/L) of total dissolved solids was observed at station A. The highest concentration mean value of Fe was observed in station C (65.33 ± 4.50 mg/L), the highest concentrations of Cd was observed in station C (0.99 ± 0.36 mg/L), the mean value of 2.13 ± 1.99 mg/L was the highest concentration of Zn observed in station B, the concentration of Pb was not detected (ND) and the highest concentration of Cu with the mean value of 0.43 ± 0.16 mg/L was observed in station B, while the lowest concentration was observed at station C (0.27 ± 0.26 mg/L). Statistical analysis shows no significant difference (P > 0.05) among the sampling stations for both the physicochemical characteristics and heavy metal concentrations. The results were found to be within the internationally acceptable standard limits.

Keywords: Assessment, freshwater, heavy metal concentration, physicochemical.

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Authors: Rishikesh Pandey, Maneesha Gupta

Abstract:

A new low-voltage floating gate MOSFET (FGMOS) based squarer using square law characteristic of the FGMOS is proposed in this paper. The major advantages of the squarer are simplicity, rail-to-rail input dynamic range, low total harmonic distortion, and low power consumption. The proposed circuit is biased without body effect. The circuit is designed and simulated using SPICE in 0.25μm CMOS technology. The squarer is operated at the supply voltages of ±0.75V . The total harmonic distortion (THD) for the input signal 0.75Vpp at 25 KHz, and maximum power consumption were found to be less than 1% and 319μW respectively.

Keywords: Analog signal processing, floating gate MOSFETs, low-voltage, Spice, squarer.

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Authors: Muhammad Mujtaba Asad, Razali Bin Hassan, Fahad Sherwani

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This paper explains about the voltage output for DC to DC boost converter between open loop, PID controller and fuzzy logic controller through Matlab Simulink. Simulink input voltage was set at 12V and the voltage reference was set at 24V. The analysis on the deviation of voltage resulted that the difference between reference voltage setting and the output voltage is always lower. Comparison between open loop, PID and FLC shows that, the open loop circuit having a bit higher on the deviation of voltage. The PID circuit boosts for FLC has a lesser deviation of voltage and proved that it is such a better performance on control the deviation of voltage during the boost mode.

Keywords: Boost Convertors, Power Electronics, PID, Fuzzy logic, Open loop.

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Authors: Ali Al-Ataby , Fawzi Al-Naima

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Symbolic Circuit Analysis (SCA) is a technique used to generate the symbolic expression of a network. It has become a well-established technique in circuit analysis and design. The symbolic expression of networks offers excellent way to perform frequency response analysis, sensitivity computation, stability measurements, performance optimization, and fault diagnosis. Many approaches have been proposed in the area of SCA offering different features and capabilities. Numerical Interpolation methods are very common in this context, especially by using the Fast Fourier Transform (FFT). The aim of this paper is to present a method for SCA that depends on the use of Wavelet Transform (WT) as a mathematical tool to generate the symbolic expression for large circuits with minimizing the analysis time by reducing the number of computations.

Keywords: Numerical Interpolation, Sparse Matrices, SymbolicAnalysis, Wavelet Transform.

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