Search results for: Arithmetic circuit
Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 652

Search results for: Arithmetic circuit

472 An Analytical Comparison between Open Loop, PID and Fuzzy Logic Based DC-DC Boost Convertor

Authors: Muhammad Mujtaba Asad, Razali Bin Hassan, Fahad Sherwani

Abstract:

This paper explains about the voltage output for DC to DC boost converter between open loop, PID controller and fuzzy logic controller through Matlab Simulink. Simulink input voltage was set at 12V and the voltage reference was set at 24V. The analysis on the deviation of voltage resulted that the difference between reference voltage setting and the output voltage is always lower. Comparison between open loop, PID and FLC shows that, the open loop circuit having a bit higher on the deviation of voltage. The PID circuit boosts for FLC has a lesser deviation of voltage and proved that it is such a better performance on control the deviation of voltage during the boost mode.

Keywords: Boost Convertors, Power Electronics, PID, Fuzzy logic, Open loop.

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471 Symbolic Analysis of Large Circuits Using Discrete Wavelet Transform

Authors: Ali Al-Ataby , Fawzi Al-Naima

Abstract:

Symbolic Circuit Analysis (SCA) is a technique used to generate the symbolic expression of a network. It has become a well-established technique in circuit analysis and design. The symbolic expression of networks offers excellent way to perform frequency response analysis, sensitivity computation, stability measurements, performance optimization, and fault diagnosis. Many approaches have been proposed in the area of SCA offering different features and capabilities. Numerical Interpolation methods are very common in this context, especially by using the Fast Fourier Transform (FFT). The aim of this paper is to present a method for SCA that depends on the use of Wavelet Transform (WT) as a mathematical tool to generate the symbolic expression for large circuits with minimizing the analysis time by reducing the number of computations.

Keywords: Numerical Interpolation, Sparse Matrices, SymbolicAnalysis, Wavelet Transform.

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470 Studies on the Feasibility of Cow Dung as a Non-Conventional Energy Source

Authors: Raj Kumar Rajak, Bharat Mishra

Abstract:

Bio-batteries represent an entirely new long-term, reasonable, reachable and ecofriendly approach to produce sustainable energy. In the present experimental work, we have studied the effect of generation of power by bio-battery using different electrode pairs. The tests show that it is possible to generate electricity using cow dung as an electrolyte. C-Mg electrode pair shows maximum voltage and SCC (Short Circuit Current) while C-Zn electrode pair shows less OCV (Open Circuit Voltage) and SCC. We have chosen C-Zn electrodes because Mg electrodes are not economical. By the studies of different electrodes and cow dung, it is found that C-Zn electrode battery is more suitable. This result shows that the bio-batteries have the potency to full fill the need of electricity demand for lower energy equipment.

Keywords: Bio-batteries, electricity, cow dung, electrodes, non-conventional.

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469 Optimization of Doubly Fed Induction Generator Equivalent Circuit Parameters by Direct Search Method

Authors: Mamidi Ramakrishna Rao

Abstract:

Doubly-fed induction generator (DFIG) is currently the choice for many wind turbines. These generators, when connected to the grid through a converter, is subjected to varied power system conditions like voltage variation, frequency variation, short circuit fault conditions, etc. Further, many countries like Canada, Germany, UK, Scotland, etc. have distinct grid codes relating to wind turbines. Accordingly, following the network faults, wind turbines have to supply a definite reactive current. To satisfy the requirements including reactive current capability, an optimum electrical design becomes a mandate for DFIG to function. This paper intends to optimize the equivalent circuit parameters of an electrical design for satisfactory DFIG performance. Direct search method has been used for optimization of the parameters. The variables selected include electromagnetic core dimensions (diameters and stack length), slot dimensions, radial air gap between stator and rotor and winding copper cross section area. Optimization for 2 MW DFIG has been executed separately for three objective functions - maximum reactive power capability (Case I), maximum efficiency (Case II) and minimum weight (Case III). In the optimization analysis program, voltage variations (10%), power factor- leading and lagging (0.95), speeds for corresponding to slips (-0.3 to +0.3) have been considered. The optimum designs obtained for objective functions were compared. It can be concluded that direct search method of optimization helps in determining an optimum electrical design for each objective function like efficiency or reactive power capability or weight minimization.

Keywords: Direct search, DFIG, equivalent circuit parameters, optimization.

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468 Simulation Based VLSI Implementation of Fast Efficient Lossless Image Compression System Using Adjusted Binary Code & Golumb Rice Code

Authors: N. Muthukumaran, R. Ravi

Abstract:

The Simulation based VLSI Implementation of FELICS (Fast Efficient Lossless Image Compression System) Algorithm is proposed to provide the lossless image compression and is implemented in simulation oriented VLSI (Very Large Scale Integrated). To analysis the performance of Lossless image compression and to reduce the image without losing image quality and then implemented in VLSI based FELICS algorithm. In FELICS algorithm, which consists of simplified adjusted binary code for Image compression and these compression image is converted in pixel and then implemented in VLSI domain. This parameter is used to achieve high processing speed and minimize the area and power. The simplified adjusted binary code reduces the number of arithmetic operation and achieved high processing speed. The color difference preprocessing is also proposed to improve coding efficiency with simple arithmetic operation. Although VLSI based FELICS Algorithm provides effective solution for hardware architecture design for regular pipelining data flow parallelism with four stages. With two level parallelisms, consecutive pixels can be classified into even and odd samples and the individual hardware engine is dedicated for each one. This method can be further enhanced by multilevel parallelisms.

Keywords: Image compression, Pixel, Compression Ratio, Adjusted Binary code, Golumb Rice code, High Definition display, VLSI Implementation.

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467 Landfill Leachate: A Promising Substrate for Microbial Fuel Cells

Authors: Jayesh M. Sonawane, Prakash C. Ghosh

Abstract:

Landfill leachate emerges as a promising feedstock for microbial fuel cells (MFCs). In the present investigation, direct air-breathing cathode-based MFCs are fabricated to investigate the potential of landfill leachate. Three MFCs that have different cathode areas are fabricated and investigated for 17 days under open circuit conditions. The maximum open circuit voltage (OCV) is observed to be as high as 1.29 V. The maximum cathode area specific power density achieved in the reactor is 1513 mW m-2. Further studies are under progress to understand the origin of high OCV obtained from landfill leachate-based MFCs.

Keywords: Microbial fuel cells, landfill leachate, air-breathing cathode, performance study.

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466 20 GHz Fractional Phased Locked Loop Circuit for the Gbps Wireless Communication

Authors: Ki-Jin Kim, Sanghoon Park, K. H. Ahn

Abstract:

This paper presents the 20-GHz fractional PLL (Phase Locked Loop) circuit for the next generation Wi-Fi by using 90 nm TSMC process. The newly suggested millimeter wave 16/17 pre-scalar is designed and verified by measurement to make the fractional PLL having a low quantization noise. The operational bandwidth of the 60 GHz system is 15 % of the carrier frequency which requires large value of Kv (VCO control gain) resulting in degradation of phase noise. To solve this problem, this paper adopts AFC (Automatic Frequency Controller) controlled 4-bit millimeter wave VCO with small value of Kv. Also constant Kv is implemented using 4-bit varactor bank. The measured operational bandwidth is 18.2 ~ 23.2 GHz which is 25 % of the carrier frequency. The phase noise of -58 and -96.2 dBc/Hz at 100 KHz and 1 MHz offset is measured respectively. The total power consumption of the PLL is only 30 mW.

Keywords: Millimeter Wave Fractional PLL, Wide band VCO, WPAN Transceiver.

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465 An Active Rectifier with Time-Domain Delay Compensation to Enhance the Power Conversion Efficiency

Authors: Shao-Ku Kao

Abstract:

This paper presents an active rectifier with time-domain delay compensation to enhance the efficiency. A delay calibration circuit is designed to convert delay time to voltage and adaptive control on/off delay in variable input voltage. This circuit is designed in 0.18 mm CMOS process. The input voltage range is from 2 V to 3.6 V with the output voltage from 1.8 V to 3.4 V. The efficiency can maintain more than 85% when the load from 50 Ω ~ 1500 Ω for 3.6 V input voltage. The maximum efficiency is 92.4 % at output power to be 38.6 mW for 3.6 V input voltage.

Keywords: Wireless power transfer, active diode, delay compensation, time to voltage converter, PCE.

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464 Performance Analysis of Digital Signal Processors Using SMV Benchmark

Authors: Erh-Wen Hu, Cyril S. Ku, Andrew T. Russo, Bogong Su, Jian Wang

Abstract:

Unlike general-purpose processors, digital signal processors (DSP processors) are strongly application-dependent. To meet the needs for diverse applications, a wide variety of DSP processors based on different architectures ranging from the traditional to VLIW have been introduced to the market over the years. The functionality, performance, and cost of these processors vary over a wide range. In order to select a processor that meets the design criteria for an application, processor performance is usually the major concern for digital signal processing (DSP) application developers. Performance data are also essential for the designers of DSP processors to improve their design. Consequently, several DSP performance benchmarks have been proposed over the past decade or so. However, none of these benchmarks seem to have included recent new DSP applications. In this paper, we use a new benchmark that we recently developed to compare the performance of popular DSP processors from Texas Instruments and StarCore. The new benchmark is based on the Selectable Mode Vocoder (SMV), a speech-coding program from the recent third generation (3G) wireless voice applications. All benchmark kernels are compiled by the compilers of the respective DSP processors and run on their simulators. Weighted arithmetic mean of clock cycles and arithmetic mean of code size are used to compare the performance of five DSP processors. In addition, we studied how the performance of a processor is affected by code structure, features of processor architecture and optimization of compiler. The extensive experimental data gathered, analyzed, and presented in this paper should be helpful for DSP processor and compiler designers to meet their specific design goals.

Keywords: digital signal processors, DSP benchmark, instruction level parallelism, modified cyclomatic complexity, performance analysis.

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463 Jatropha curcas L. Oil Selectivity in Froth Flotation

Authors: André C. Silva, Izabela L. A. Moraes, Elenice M. S. Silva, Carlos M. Silva Filho

Abstract:

In Brazil, most soils are acidic and low in essential nutrients required for the growth and development of plants, making fertilizers essential for agriculture. As the biggest producer of soy in the world and a major producer of coffee, sugar cane and citrus fruits, Brazil is a large consumer of phosphate. Brazilian’s phosphate ores are predominantly from igneous rocks showing a complex mineralogy, associated with carbonites and oxides, typically iron, silicon and barium. The adopted industrial concentration circuit for this type of ore is a mix between magnetic separation (both low and high field) to remove the magnetic fraction and a froth flotation circuit composed by a reverse flotation of apatite (barite’s flotation) followed by direct flotation circuit (rougher, cleaner and scavenger circuit). Since the 70’s fatty acids obtained from vegetable oils are widely used as lower-cost collectors in apatite froth flotation. This is a very effective approach to the apatite family of minerals, being that this type of collector is both selective and efficient (high recovery). This paper presents Jatropha curcas L. oil (JCO) as a renewable and sustainable source of fatty acids with high selectivity in froth flotation of apatite. JCO is considerably rich in fatty acids such as linoleic, oleic and palmitic acid. The experimental campaign involved 216 tests using a modified Hallimond tube and two different minerals (apatite and quartz). In order to be used as a collector, the oil was saponified. The results found were compared with the synthetic collector, Fotigam 5806 produced by Clariant, which is composed mainly by soy oil. JCO showed the highest selectivity for apatite flotation with cold saponification at pH 8 and concentration of 2.5 mg/L. In this case, the mineral recovery was around 95%.

Keywords: Froth flotation, Jatropha curcas L., microflotation, selectivity.

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462 Higher Frequency Modeling of Synchronous Exciter Machines by Equivalent Circuits and Transfer Functions

Authors: Marcus Banda

Abstract:

In this article the influence of higher frequency effects in addition to a special damper design on the electrical behavior of a synchronous generator main exciter machine is investigated. On the one hand these machines are often highly stressed by harmonics from the bridge rectifier thus facing additional eddy current losses. On the other hand the switching may cause the excitation of dangerous voltage peaks in resonant circuits formed by the diodes of the rectifier and the commutation reactance of the machine. Therefore modern rotating exciters are treated like synchronous generators usually modeled with a second order equivalent circuit. Hence the well known Standstill Frequency Response Test (SSFR) method is applied to a test machine in order to determine parameters for the simulation. With these results it is clearly shown that higher frequencies have a strong impact on the conventional equivalent circuit model. Because of increasing field displacement effects in the stranded armature winding the sub-transient reactance is even smaller than the armature leakage at high frequencies. As a matter of fact this prevents the algorithm to find an equivalent scheme. This issue is finally solved using Laplace transfer functions fully describing the transient behavior at the model ports.

Keywords: Synchronous exciter machine, Linear transfer function, SSFR, Equivalent Circuit

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461 A Semi-Cylindrical Capacitive Sensor Used for Soil Moisture Measurement

Authors: Subir Das, Tuhin Subhra Sarkar, Badal Chakraborty

Abstract:

Differing from the structure of traditional parallel plate capacitive sensor a semi cylindrical capacitive sensor has been introduced in this present work to measure the soil moisture conveniently. Here, the numerical analysis method to evaluate the capacitance from the semi-cylindrical capacitive sensor is analyzed and discussed. The changes of capacitance with the variation of soil moisture obtained linear in the nano farad range (nF) and which converted into voltage variation by using proper signal conditioning circuit. Experimental results depict the satisfactory performance of the sensor for measurement of soil moisture in the range of 0 to 70%. We investigated the linearity of 4% of FSO and sensitivity of 70 mV/unit percentage changes in soil moisture level (DB).

Keywords: Semi cylindrical Capacitive Sensor, Capacitance to Voltage converter Circuit, Soil Moisture.

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460 Low Power Circuit Architecture of AES Crypto Module for Wireless Sensor Network

Authors: MooSeop Kim, Juhan Kim, Yongje Choi

Abstract:

Recently, much research has been conducted for security for wireless sensor networks and ubiquitous computing. Security issues such as authentication and data integrity are major requirements to construct sensor network systems. Advanced Encryption Standard (AES) is considered as one of candidate algorithms for data encryption in wireless sensor networks. In this paper, we will present the hardware architecture to implement low power AES crypto module. Our low power AES crypto module has optimized architecture of data encryption unit and key schedule unit which could be applicable to wireless sensor networks. We also details low power design methods used to design our low power AES crypto module.

Keywords: Algorithm, Low Power Crypto Circuit, AES, Security.

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459 Studies on the Feasibility of Cow’s Urine as Non-Conventional Energy Sources

Authors: Raj Kumar Rajak, Bharat Mishra

Abstract:

Bio-batteries represent an entirely new long-term, reasonable, reachable, and eco-friendly approach to generation of sustainable energy. In the present experimental work, we have studied the effect of the generation of power by bio-battery using different electrode pairs. The tests show that it is possible to generate electricity using cow’s urine as an electrolyte. C-Mg electrode pair shows maximum Voltage and Short Circuit Current (SCC), while C-Zn electrode pair shows less Open Circuit Voltage (OCV) and SCC. By the studies of cow urine and different electrodes, it is found that C-Zn electrode battery is more economical. The cow urine battery with C-Zn electrode provides maximum power (707.4 mW) and durability (up to 145 h). This result shows that the bio-batteries have the potency to full fill the need of electricity demand for lower energy equipment.

Keywords: Bio-batteries, cow’s urine, electrodes, non-conventional.

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458 Real Time Force Sensing Mat for Human Gait Analysis

Authors: Darwin Gouwanda, S. M. N. Arosha Senanayake, M. M. Danushka Ranjana Marasinghe, Mervin Chandrapal, Jeya Mithra Kumar, Tung Mun Hon, Yulius

Abstract:

This paper presents a real time force sensing instrument that is designed for human gait analysis purposes. This instrument mainly consists of three main elements: the force sensing mat, signal conditioning and switching circuit and data acquisition device. In order to control and to process the incoming signals from the force sensing mat, Force-Logger and Force-Reloader program are developed using Labview 8.0. This paper describes the architecture of the force sensing mat, signal conditioning and switching circuit and the real time streaming of the incoming data from the force sensing mat.

Keywords: Force platform, Force sensing resistor, human gait analysis

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457 Film Sensors for the Harsh Environment Application

Authors: Wenmin Qu

Abstract:

A capacitance level sensor with a segmented film electrode and a thin-film volume flow sensor with an innovative by-pass sleeve is presented as industrial products for the application in a harsh environment. The working principle of such sensors is well known; however, the traditional sensors show some limitations for certain industrial measurements. The two sensors presented in this paper overcome this limitation and enlarge the application spectrum. The problem is analyzed, and the solution is given. The emphasis of the paper is on developing the problem-solving concepts and the realization of the corresponding measuring circuits. These should give advice and encouragement, how we can still develop electronic measuring products in an almost saturated market.

Keywords: By-pass sleeve, charge transfer circuit, fixed ΔT circuit, harsh environment, industrial application, segmented electrode.

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456 Symbolic Analysis of Power Spectrum of CMOS Cross Couple Oscillator

Authors: Kittipong Tripetch

Abstract:

This paper proposes for the first time symbolic formula of the power spectrum of CMOS Cross Couple Oscillator and its modified circuit. Many principles existed to derived power spectrum in microwave textbook such as impedance, admittance parameters, ABCD, H parameters, etc. It can be compared by graph of power spectrum which methodology is the best from the point of view of practical measurement setup such as condition of impedance parameter which used superposition of current to derived (its current injection at the other port of the circuit is zero, which is impossible in reality). Four graphs of impedance parameters of cross couple oscillator are proposed. After that four graphs of scattering parameters of CMOS cross coupled oscillator will be shown.

Keywords: Optimization, power spectrum, impedance parameter, scattering parameter.

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455 Design Calculation and Performance Testing of Heating Coil in Induction Surface Hardening Machine

Authors: Soe Sandar Aung, Han Phyo Wai, Nyein Nyein Soe

Abstract:

The induction hardening machines are utilized in the industries which modify machine parts and tools needed to achieve high ware resistance. This paper describes the model of induction heating process design of inverter circuit and the results of induction surface hardening of heating coil. In the design of heating coil, the shape and the turn numbers of the coil are very important design factors because they decide the overall operating performance of induction heater including resonant frequency, Q factor, efficiency and power factor. The performance will be tested by experiments in some cases high frequency induction hardening machine.

Keywords: Induction Heating, Resonant Circuit, InverterCircuit, Coil Design, Induction Hardening Machine.

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454 A Novel Application of Network Equivalencing Method in Time Domain to Precise Calculation of Dead Time in Power Transmission Title

Authors: J. Moshtagh, L. Eslami

Abstract:

Various studies have showed that about 90% of single line to ground faults occurred on High voltage transmission lines have transient nature. This type of faults is cleared by temporary outage (by the single phase auto-reclosure). The interval between opening and reclosing of the faulted phase circuit breakers is named “Dead Time” that is varying about several hundred milliseconds. For adjustment of traditional single phase auto-reclosures that usually are not intelligent, it is necessary to calculate the dead time in the off-line condition precisely. If the dead time used in adjustment of single phase auto-reclosure is less than the real dead time, the reclosing of circuit breakers threats the power systems seriously. So in this paper a novel approach for precise calculation of dead time in power transmission lines based on the network equivalencing in time domain is presented. This approach has extremely higher precision in comparison with the traditional method based on Thevenin equivalent circuit. For comparison between the proposed approach in this paper and the traditional method, a comprehensive simulation by EMTP-ATP is performed on an extensive power network.

Keywords: Dead Time, Network Equivalencing, High Voltage Transmission Lines, Single Phase Auto-Reclosure.

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453 A 5-V to 30-V Current-Mode Boost Converter with Integrated Current Sensor and Power-on Protection

Authors: Jun Yu, Yat-Hei Lam, Boris Grinberg, Kevin Chai Tshun Chuan

Abstract:

This paper presents a 5-V to 30-V current-mode boost converter for powering the drive circuit of a micro-electro-mechanical sensor. The design of a transconductance amplifier and an integrated current sensing circuit are presented. In addition, essential building blocks for power-on protection such as a soft-start and clamp block and supply and clock ready block are discussed in details. The chip is fabricated in a 0.18-μm CMOS process. Measurement results show that the soft-start and clamp block can effectively limit the inrush current during startup and protect the boost converter from startup failure.

Keywords: Boost Converter, Current Sensing, Power-on protection, Step-up Converter, Soft-start.

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452 The Frequency Graph for the Traveling Salesman Problem

Authors: Y. Wang

Abstract:

Traveling salesman problem (TSP) is hard to resolve when the number of cities and routes become large. The frequency graph is constructed to tackle the problem. A frequency graph maintains the topological relationships of the original weighted graph. The numbers on the edges are the frequencies of the edges emulated from the local optimal Hamiltonian paths. The simplest kind of local optimal Hamiltonian paths are computed based on the four vertices and three lines inequality. The search algorithm is given to find the optimal Hamiltonian circuit based on the frequency graph. The experiments show that the method can find the optimal Hamiltonian circuit within several trials.

Keywords: Traveling salesman problem, frequency graph, local optimal Hamiltonian path, four vertices and three lines inequality.

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451 Micropower Fuzzy Linguistic-Hedges Circuit in Current-Mode Approach

Authors: E. Farshidi

Abstract:

In this paper, based on a novel synthesis, a set of new simplified circuit design to implement the linguistic-hedge operations for adjusting the fuzzy membership function set is presented. The circuits work in current-mode and employ floating-gate MOS (FGMOS) transistors that operate in weak inversion region. Compared to the other proposed circuits, these circuits feature severe reduction of the elements number, low supply voltage (0.7V), low power consumption (<200nW), immunity from body effect and wide input dynamic range (>60dB). In this paper, a set of fuzzy linguistic hedge circuits, including absolutely, very, much more, more, plus minus, more or less and slightly, has been implemented in 0.18 mm CMOS process. Simulation results by Hspice confirm the validity of the proposed design technique and show high performance of the circuits.

Keywords: Current-mode, Linguistic-Hedge, Fuzzy Logic, lowpower

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450 EEG Correlates of Trait and Mathematical Anxiety during Lexical and Numerical Error-Recognition Tasks

Authors: Alexander N. Savostyanov, Tatiana A. Dolgorukova, Elena A. Esipenko, Mikhail S. Zaleshin, Margherita Malanchini, Anna V. Budakova, Alexander E. Saprygin, Tatiana A. Golovko, Yulia V. Kovas

Abstract:

EEG correlates of mathematical and trait anxiety level were studied in 52 healthy Russian-speakers during execution of error-recognition tasks with lexical, arithmetic and algebraic conditions. Event-related spectral perturbations were used as a measure of brain activity. The ERSP plots revealed alpha/beta desynchronizations within a 500-3000 ms interval after task onset and slow-wave synchronization within an interval of 150-350 ms. Amplitudes of these intervals reflected the accuracy of error recognition, and were differently associated with the three conditions. The correlates of anxiety were found in theta (4-8 Hz) and beta2 (16- 20 Hz) frequency bands. In theta band the effects of mathematical anxiety were stronger expressed in lexical, than in arithmetic and algebraic condition. The mathematical anxiety effects in theta band were associated with differences between anterior and posterior cortical areas, whereas the effects of trait anxiety were associated with inter-hemispherical differences. In beta1 and beta2 bands effects of trait and mathematical anxiety were directed oppositely. The trait anxiety was associated with increase of amplitude of desynchronization, whereas the mathematical anxiety was associated with decrease of this amplitude. The effect of mathematical anxiety in beta2 band was insignificant for lexical condition but was the strongest in algebraic condition. EEG correlates of anxiety in theta band could be interpreted as indexes of task emotionality, whereas the reaction in beta2 band is related to tension of intellectual resources.

Keywords: EEG, brain activity, lexical and numerical error-recognition tasks, mathematical and trait anxiety.

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449 Evaluation of Fuzzy ARTMAP with DBSCAN in VLSI Application

Authors: K. A. Sumithradevi, Vijayalakshmi. M. N., Annamma Abraham., Dr. Vasanta

Abstract:

The various applications of VLSI circuits in highperformance computing, telecommunications, and consumer electronics has been expanding progressively, and at a very hasty pace. This paper describes a new model for partitioning a circuit using DBSCAN and fuzzy ARTMAP neural network. The first step is concerned with feature extraction, where we had make use DBSCAN algorithm. The second step is the classification and is composed of a fuzzy ARTMAP neural network. The performance of both approaches is compared using benchmark data provided by MCNC standard cell placement benchmark netlists. Analysis of the investigational results proved that the fuzzy ARTMAP with DBSCAN model achieves greater performance then only fuzzy ARTMAP in recognizing sub-circuits with lowest amount of interconnections between them The recognition rate using fuzzy ARTMAP with DBSCAN is 97.7% compared to only fuzzy ARTMAP.

Keywords: VLSI, Circuit partitioning, DBSCAN, fuzzyARTMAP.

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448 Three-phases Model of the Induction Machine Taking Account the Stator Faults

Authors: Djalal Eddine Khodja, Aissa Kheldoun

Abstract:

In this work we present the modelling of the induction machine, taking into consideration the stator defects of the induction machine. It is based on the theory of electromagnetic coupling of electrical circuits. In fact, for the modelling of stationary defects such as short circuit between turns in the same phase, we introduce only in the matrix the coefficients of resistance and inductance of stator and in the mutual inductance stator-rotor. These coefficients take account the number of turns in short-circuit deducted from the total number of turns in the same phase; in this way we obtain the number of useful turns. In addition, all these faults involved, will be used for the creation of the database that will be used to develop an automated system failures of the induction machine.

Keywords: Asynchronous machine, Indicatory Values Statorfaults, Multi-turns Model, Three-phases Model.

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447 A Pipelined FSBM Hardware Architecture for HTDV-H.26x

Authors: H. Loukil, A. Ben Atitallah, F. Ghozzi, M. A. Ben Ayed, N. Masmoudi

Abstract:

In MPEG and H.26x standards, to eliminate the temporal redundancy we use motion estimation. Given that the motion estimation stage is very complex in terms of computational effort, a hardware implementation on a re-configurable circuit is crucial for the requirements of different real time multimedia applications. In this paper, we present hardware architecture for motion estimation based on "Full Search Block Matching" (FSBM) algorithm. This architecture presents minimum latency, maximum throughput, full utilization of hardware resources such as embedded memory blocks, and combining both pipelining and parallel processing techniques. Our design is described in VHDL language, verified by simulation and implemented in a Stratix II EP2S130F1020C4 FPGA circuit. The experiment result show that the optimum operating clock frequency of the proposed design is 89MHz which achieves 160M pixels/sec.

Keywords: SAD, FSBM, Hardware Implementation, FPGA.

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446 Central Pattern Generator Incorporating the Actuator Dynamics for a Hexapod Robot

Authors: Valeri A. Makarov, Ezequiel Del Rio, Manuel G. Bedia, Manuel G. Velarde, Werner Ebeling

Abstract:

We proposed the use of a Toda-Rayleigh ring as a central pattern generator (CPG) for controlling hexapodal robots. We show that the ring composed of six Toda-Rayleigh units coupled to the limb actuators reproduces the most common hexapodal gaits. We provide an electrical circuit implementation of the CPG and test our theoretical results obtaining fixed gaits. Then we propose a method of incorporation of the actuator (motor) dynamics in the CPG. With this approach we close the loop CPG – environment – CPG, thus obtaining a decentralized model for the leg control that does not require higher level intervention to the CPG during locomotion in a nonhomogeneous environments. The gaits generated by the novel CPG are not fixed, but adapt to the current robot bahvior.

Keywords: Central pattern generator, electrical circuit, hexapod robot

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445 Comprehensive Nonlinearity Simulation of Different Types and Modes of HEMTs with Respect to Biasing Conditions

Authors: M. M. Karkhanehchi, A. Ammani

Abstract:

A simple analytical model has been developed to optimize biasing conditions for obtaining maximum linearity among lattice-matched, pseudomorphic and metamorphic HEMT types as well as enhancement and depletion HEMT modes. A nonlinear current-voltage model has been simulated based on extracted data to study and select the most appropriate type and mode of HEMT in terms of a given gate-source biasing voltage within the device so as to employ the circuit for the highest possible output current or voltage linear swing. Simulation results can be used as a basis for the selection of optimum gate-source biasing voltage for a given type and mode of HEMT with regard to a circuit design. The consequences can also be a criterion for choosing the optimum type or mode of HEMT for a predetermined biasing condition.

Keywords: Biasing, characteristic, linearity, simulation.

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444 Improved Segmentation of Speckled Images Using an Arithmetic-to-Geometric Mean Ratio Kernel

Authors: J. Daba, J. Dubois

Abstract:

In this work, we improve a previously developed segmentation scheme aimed at extracting edge information from speckled images using a maximum likelihood edge detector. The scheme was based on finding a threshold for the probability density function of a new kernel defined as the arithmetic mean-to-geometric mean ratio field over a circular neighborhood set and, in a general context, is founded on a likelihood random field model (LRFM). The segmentation algorithm was applied to discriminated speckle areas obtained using simple elliptic discriminant functions based on measures of the signal-to-noise ratio with fractional order moments. A rigorous stochastic analysis was used to derive an exact expression for the cumulative density function of the probability density function of the random field. Based on this, an accurate probability of error was derived and the performance of the scheme was analysed. The improved segmentation scheme performed well for both simulated and real images and showed superior results to those previously obtained using the original LRFM scheme and standard edge detection methods. In particular, the false alarm probability was markedly lower than that of the original LRFM method with oversegmentation artifacts virtually eliminated. The importance of this work lies in the development of a stochastic-based segmentation, allowing an accurate quantification of the probability of false detection. Non visual quantification and misclassification in medical ultrasound speckled images is relatively new and is of interest to clinicians.

Keywords: Discriminant function, false alarm, segmentation, signal-to-noise ratio, skewness, speckle.

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443 Active Power Filtering Implementation Using Photovoltaic System with Reduced Energy Storage Capacitor

Authors: Horng-Yuan Wu, Chin-Yuan Hsu, Tsair-Fwu Lee

Abstract:

A novel three-phase active power filter (APF) circuit with photovoltaic (PV) system to improve the quality of service and to reduce the capacity of energy storage capacitor is presented. The energy balance concept and sampling technique were used to simplify the calculation algorithm for the required utility source current and to control the voltage of the energy storage capacitor. The feasibility was verified by using the Pspice simulations and experiments. When the APF mode was used during non-operational period, not only the utilization rate, power factor and power quality could be improved, but also the capacity of energy storage capacitor could sparing. As the results, the advantages of the APF circuit are simplicity of control circuits, low cost, and good transient response.

Keywords: active power filter, sampling, energy-storagecapacitor, harmonic current, energy balance.

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