Search results for: Gate delay

Authors: Hardik Vaghela, Mamta Khosla, Balwindar Raj

Abstract:

In this paper, we present and investigate a double gate PN diode based tunnel field effect transistor (DGPNTFET). The importance of proposed structure is that the formation of different drain doping is not required and ambipolar effect in OFF state is completely removed for this structure. Validation of this structure to behave like a Tunnel Field Effect Transistor (TFET) is carried out through energy band diagrams and transfer characteristics. Simulated result shows point subthreshold slope (SS) of 19.14 mV/decade and ON to OFF current ratio (I_ON / I_OFF) of 2.66 × 10¹⁴ (I_ON at V_GS=1.5V, V_DS=1V and I_OFF at V_GS=0V, V_DS=1V) for gate length of 20nm and HfO₂ as gate oxide at room temperature. Which indicate that the DGPNTFET is a promising candidate for nano-scale, ambipolar free switch.

Keywords: Ambipolar effect, double gate PN diode based tunnel field effect transistor, high-κ dielectric material, subthreshold slope, tunnel field effect transistor.

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Authors: Manas Ranjan Kabat, Manoj Kumar Patel, Chita Ranjan Tripathy

Abstract:

Many multimedia communication applications require a source to transmit messages to multiple destinations subject to quality of service (QoS) delay constraint. To support delay constrained multicast communications, computer networks need to guarantee an upper bound end-to-end delay from the source node to each of the destination nodes. This is known as multicast delay problem. On the other hand, if the same message fails to arrive at each destination node at the same time, there may arise inconsistency and unfairness problem among users. This is related to multicast delayvariation problem. The problem to find a minimum cost multicast tree with delay and delay-variation constraints has been proven to be NP-Complete. In this paper, we propose an efficient heuristic algorithm, namely, Economic Delay and Delay-Variation Bounded Multicast (EDVBM) algorithm, based on a novel heuristic function, to construct an economic delay and delay-variation bounded multicast tree. A noteworthy feature of this algorithm is that it has very high probability of finding the optimal solution in polynomial time with low computational complexity.

Keywords: EDVBM, Heuristic algorithm, Multicast tree, QoS routing, Shortest path.

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Authors: Farid Moshgelani, Dhamin Al-Khalili, Côme Rozon

Abstract:

In this paper, FinFET devices are analyzed with emphasis on sub-threshold leakage current control. This is achieved through proper biasing of the back gate, and through the use of asymmetric work functions for the four terminal FinFET devices. We are also examining different configurations of multiplexers and XOR gates using transistors of symmetric and asymmetric work functions. Based on extensive characterization data for MUX circuits, our proposed configuration using symmetric devices lead to leakage current and delay improvements of 65% and 47% respectively compared to results in the literature. For XOR gates, a 90% improvement in the average leakage current is achieved by using asymmetric devices. All simulations are based on a 25nm FinFET technology using the University of Florida UFDG model.

Keywords: FinFET, logic functions, asymmetric workfunction devices, back gate biasing, sub-threshold leakage current.

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Authors: Zarabizan Zakaria, Syuhaida Ismail, Aminah Md. Yusof

Abstract:

Delay can be defined as time overrun or extension of time to complete the project. There are high possibilities that delay issues in final account closing cannot be avoided especially in construction project in Malaysia which is unique and dynamic in the terms of nature of design and technical skill. Delay in final account closing is a situation when the actual planning (time and budget allocation) of a construction project exceeds the planned schedule or on the other hand, final account closing exceeds the time and other provisions specified in the contract. The causes of delay discussed in this paper are appraised from the literature review. There are two main types of delay: excusable delay and non-excusable delay. The literature reviews on the delay in final account closing which is then translated into a theoretical framework are summarized in the context of construction players and academician perspective. It is anticipated that the finding reported in this paper could assist the planning of future strategies and guidelines of final account closing for the betterment of construction projects in Malaysia.

Keywords: Construction industry, construction contract, final account closing, delay.

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Authors: Qingqing Wang, Shouming Zhong

Abstract:

In this paper, delay-dependent stability analysis for neutral type neural networks with uncertain paramters and time-varying delay is studied. By constructing new Lyapunov-Krasovskii functional and dividing the delay interval into multiple segments, a novel sufficient condition is established to guarantee the globally asymptotically stability of the considered system. Finally, a numerical example is provided to illustrate the usefulness of the proposed main results.

Keywords: Neutral type neural networks, Time-varying delay, Stability, Linear matrix inequality(LMI).

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Authors: N. Hamzah, M.A. Khoiry, I. Arshad, W.H.W. Badaruzzaman, N. M. Tawil

Abstract:

Construction delay is unavoidable in developing countries including Malaysia. It is defined as time overrun or extension of time for completion of a project. The purpose of the study is to determine the causes of delay in Malaysian construction industries based on previous worldwide research. The field survey conducted includes the experienced developers, consultants and contractors in Malaysia. 34 causes of the construction delay have been determined and 24 have been selected using the Rasch model analysis. The analysis result will be used as the baseline for the next research to find the causes of delay in the Malaysian construction industry taking place in Malaysian higher learning institutions.

Keywords: Causes of construction delay, construction projects, Malaysian construction industry, Rasch model analysis.

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Authors: Spyridon Nikolaidis

Abstract:

A modeling approach for CMOS gates is presented based on the use of the equivalent inverter. A new model for the inverter has been developed using a simplified transistor current model which incorporates the nanoscale effects for the planar technology. Parametric expressions for the output voltage are provided as well as the values of the output and supply current to be compatible with the CCS technology. The model is parametric according the input signal slew, output load, transistor widths, supply voltage, temperature and process. The transistor widths of the equivalent inverter are determined by HSPICE simulations and parametric expressions are developed for that using a fitting procedure. Results for the NAND gate shows that the proposed approach offers sufficient accuracy with an average error in propagation delay about 5%.

Keywords: CMOS gate modeling, Inverter modeling, transistor current model, timing model.

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Authors: Rekha V. Dundur , M.V.Latte, S.Y. Kulkarni, M.K.Venkatesha

Abstract:

The advent of multi-million gate Field Programmable Gate Arrays (FPGAs) with hardware support for multiplication opens an opportunity to recreate a significant portion of the front end of a human cochlea using this technology. In this paper we describe the implementation of the cochlear filter and show that it is entirely suited to a single device XC3S500 FPGA implementation .The filter gave a good fit to real time data with efficiency of hardware usage.

Keywords: Cochlea, FPGA, IIR (Infinite Impulse Response), Multiplier.

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Authors: K. Karami, S. Hassan, S. Taking, A. Ofiare, A. Dhongde, A. Al-Khalidi, E. Wasige

Abstract:

We have made a comparative study on the influence of Al2O3 and HfO2 grown using Atomic Layer Deposition (ALD) technique as dielectric in the AlGaN/GaN metal oxide semiconductor high electron mobility transistor (MOS-HEMT) structure. Five samples consisting of 20 nm and 10 nm each of A2lO3 and HfO2 respectively and a Schottky gate HEMT, were fabricated and measured. The threshold voltage shifts towards negative by 0.1 V and 1.8 V for 10 nm thick HfO2 and 10 nm thick Al2O3 gate dielectric layers, respectively. The negative shift for the 20 nm HfO2 and 20 nm Al2O3 were 1.2 V and 4.9 V, respectively. Higher gm/IDS (transconductance to drain current) ratio was also obtained in HfO2 than Al2O3. With both materials as dielectric, a significant reduction in the gate leakage current in the order of 104 was obtained compared to the sample without the dielectric material.

Keywords: AlGaN/GaN HEMTs, Al2O3, HfO2, MOSHEMTs.

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Authors: Myeongjin Park, Ohmin Kwon, Juhyun Park, Sangmoon Lee

Abstract:

This paper proposes improved delay-dependent stability conditions of the linear time-delay systems of neutral type. The proposed methods employ a suitable Lyapunov-Krasovskii’s functional and a new form of the augmented system. New delay-dependent stability criteria for the systems are established in terms of Linear matrix inequalities (LMIs) which can be easily solved by various effective optimization algorithms. Numerical examples showed that the proposed method is effective and can provide less conservative results.

Keywords: Neutral systems, Time-delay, Stability, Lyapunovmethod, LMI.

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Authors: Jonah Gamba

Abstract:

In this paper the problem of estimating the time delay between two spatially separated noisy sinusoidal signals by system identification modeling is addressed. The system is assumed to be perturbed by both input and output additive white Gaussian noise. The presence of input noise introduces bias in the time delay estimates. Normally the solution requires a priori knowledge of the input-output noise variance ratio. We utilize the cascade of a self-tuned filter with the time delay estimator, thus making the delay estimates robust to input noise. Simulation results are presented to confirm the superiority of the proposed approach at low input signal-to-noise ratios.

Keywords: LMS algorithm, Self-tuned filter, Systemidentification, Time delay estimation, .

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Authors: Yingguo Li

Abstract:

In this paper, we consider a discrete Gompertz model with time delay. Firstly, the stability of the equilibrium of the system is investigated by analyzing the characteristic equation. By choosing the time delay as a bifurcation parameter, we prove that Neimark- Sacker bifurcations occur when the delay passes a sequence of critical values. The direction and stability of the Neimark-Sacker are determined by using normal forms and centre manifold theory. Finally, some numerical simulations are given to verify the theoretical analysis.

Keywords: Gompertz system, Neimark-Sacker bifurcation, stability, time delay.

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Authors: Mohsen Maadani, Seyed Ahmad Motamedi

Abstract:

The use of wireless technology in industrial networks has gained vast attraction in recent years. In this paper, we have thoroughly analyzed the effect of contention window (CW) size on the performance of IEEE 802.11-based industrial wireless networks (IWN), from delay and reliability perspective. Results show that the default values of CWmin, CWmax, and retry limit (RL) are far from the optimum performance due to the industrial application characteristics, including short packet and noisy environment. In this paper, an adaptive CW algorithm (payload-dependent) has been proposed to minimize the average delay. Finally a simple, but effective CW and RL setting has been proposed for industrial applications which outperforms the minimum-average-delay solution from maximum delay and jitter perspective, at the cost of a little higher average delay. Simulation results show an improvement of up to 20%, 25%, and 30% in average delay, maximum delay and jitter respectively.

Keywords: Average Delay, Contention Window, Distributed Coordination Function (DCF), Jitter, Industrial Wireless Network (IWN), Maximum Delay, Reliability, Retry Limit.

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Authors: R. Farkh, K. Laabidi, M. Ksouri

Abstract:

In this paper, we consider the control of time delay system by Proportional-Integral (PI) controller. By Using the Hermite- Biehler theorem, which is applicable to quasi-polynomials, we seek a stability region of the controller for first order delay systems. The essence of this work resides in the extension of this approach to second order delay system, in the determination of its stability region and the computation of the PI optimum parameters. We have used the genetic algorithms to lead the complexity of the optimization problem.

Keywords: Genetic algorithm, Hermit-Biehler theorem, optimization, PI controller, second order delay system, stability region.

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Authors: M.J. Park, K.H. Kim, O.M. Kwon

Abstract:

This paper proposes a delay-dependent leader-following consensus condition of multi-agent systems with both communication delay and probabilistic self-delay. The proposed methods employ a suitable piecewise Lyapunov-Krasovskii functional and the average dwell time approach. New consensus criterion for the systems are established in terms of linear matrix inequalities (LMIs) which can be easily solved by various effective optimization algorithms. Numerical example showed that the proposed method is effective.

Keywords: Multi-agent systems, probabilistic self-delay, consensus, Lyapunov method, LMI.

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Authors: Dawit Burusie Abdi, Mamidala Jagadesh Kumar

Abstract:

In this paper, using 2D TCAD simulations, the application of a dual material gate (DMG) for suppressing ambipolar conduction in a tunnel field effect transistor (TFET) is demonstrated. Using the proposed DMG concept, the ambipolar conduction can be effectively suppressed even if the drain doping is as high as that of the source doping. Achieving this symmetrical doping, without the ambipolar conduction in TFETs, gives the advantage of realizing both n-type and p-type devices with the same doping sequences. Furthermore, the output characteristics of the DMG TFET exhibit a good saturation when compared to that of the gate-drain underlap approach. This improved behavior of the DMG TFET makes it a good candidate for inverter based logic circuits.

Keywords: Dual material gate, suppressing ambipolar current, symmetrically doped TFET, tunnel FETs, PNPN TFET.

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Authors: Shao-Ku Kao

Abstract:

This paper presents an active rectifier with time-domain delay compensation to enhance the efficiency. A delay calibration circuit is designed to convert delay time to voltage and adaptive control on/off delay in variable input voltage. This circuit is designed in 0.18 mm CMOS process. The input voltage range is from 2 V to 3.6 V with the output voltage from 1.8 V to 3.4 V. The efficiency can maintain more than 85% when the load from 50 Ω ~ 1500 Ω for 3.6 V input voltage. The maximum efficiency is 92.4 % at output power to be 38.6 mW for 3.6 V input voltage.

Keywords: Wireless power transfer, active diode, delay compensation, time to voltage converter, PCE.

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Authors: P.S.Prakash, S.Selvan

Abstract:

Packet switched data network like Internet, which has traditionally supported throughput sensitive applications such as email and file transfer, is increasingly supporting delay-sensitive multimedia applications such as interactive video. These delaysensitive applications would often rather sacrifice some throughput for better delay. Unfortunately, the current packet switched network does not offer choices, but instead provides monolithic best-effort service to all applications. This paper evaluates Class Based Queuing (CBQ), Coordinated Earliest Deadline First (CEDF), Weighted Switch Deficit Round Robin (WSDRR) and RED-Boston scheduling schemes that is sensitive to delay bound expectations for variety of real time applications and an enhancement of WSDRR is proposed.

Keywords: QoS, Delay-sensitive, Queuing delay, Scheduling

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Authors: Bhavana Prakash Shrivastava, Kavita Khare

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This paper presents a synthesis and simulation of proposed enhanced buffer. The design provides advantages of both buffer and bufferless network for that two cross bar switches are used. The concept of virtual channel (VC) is eliminated from the previous design by using an efficient flow-control scheme that uses the storage already present in pipelined channels in place of explicit input VCBs. This can be addressed by providing enhanced buffers on the bufferless link and creating two virtual networks. With this approach, VCBs act as distributed FIFO buffers. Without VCBs or VCs, deadlock prevention is achieved by duplicating physical channels. An enhanced buffer provides a function of hand shaking by providing a ready valid handshake signal and two bit storage. Through this design the power is reduced to 15.65% and delay is reduced to 97.88% with respect to virtual channel router.

Keywords: Enhanced buffer, Gate delay, NOC, VCs, VCB.

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Authors: Muhibul Haque Bhuyan

Abstract:

This paper reports on the impact study with the variation of the gate insulation material and thickness on different models of pocket implanted sub-100 nm n-MOS device. The gate materials used here are silicon dioxide (SiO₂), aluminum silicate (Al₂SiO₅), silicon nitride (Si₃N₄), alumina (Al₂O₃), hafnium silicate (HfSiO₄), tantalum pentoxide (Ta₂O₅), hafnium dioxide (HfO₂), zirconium dioxide (ZrO₂), and lanthanum oxide (La₂O₃) upon a p-type silicon substrate material. The gate insulation thickness was varied from 2.0 nm to 3.5 nm for a 50 nm channel length pocket implanted n-MOSFET. There are several models available for this device. We have studied and simulated threshold voltage model incorporating drain and substrate bias effects, surface potential, inversion layer charge, pinch-off voltage, effective electric field, inversion layer mobility, and subthreshold drain current models based on two linear symmetric pocket doping profiles. We have changed the values of the two parameters, viz. gate insulation material and thickness gradually fixing the other parameter at their typical values. Then we compared and analyzed the simulation results. This study would be helpful for the nano-scaled MOS device designers for various applications to predict the device behavior.

Keywords: Linear symmetric pocket profile, pocket implanted n-MOS Device, model, impact of gate material, insulator thickness.

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Authors: Muhammad H. Rais,

Abstract:

Truncated multiplier is a good candidate for digital signal processing (DSP) applications including finite impulse response (FIR) and discrete cosine transform (DCT). Through truncated multiplier a significant reduction in Field Programmable Gate Array (FPGA) resources can be achieved. This paper presents for the first time a comparison of resource utilization of Spartan-3AN and Virtex-5 implementation of standard and truncated multipliers using Very High Speed Integrated Circuit Hardware Description Language (VHDL). The Virtex-5 FPGA shows significant improvement as compared to Spartan-3AN FPGA device. The Virtex-5 FPGA device shows better performance with a percentage ratio of number of occupied slices for standard to truncated multipliers is increased from 40% to 73.86% as compared to Spartan- 3AN is decreased from 68.75% to 58.78%. Results show that the anomaly in Spartan-3AN FPGA device average connection and maximum pin delay have been efficiently reduced in Virtex-5 FPGA device.

Keywords: Digital Signal Processing (DSP), FieldProgrammable Gate Array (FPGA), Spartan-3AN, TruncatedMultiplier, Virtex-5, VHDL.

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Authors: Li Xu, Shouming Zhong

Abstract:

The reachable set bounding estimation for distributed delay systems with disturbances is a new problem. In this paper,we consider this problem subject to not only time varying delay and polytopic uncertainties but also distributed delay systems which is not studied fully untill now. we can obtain improved non-ellipsoidal reachable set estimation for neural networks with time-varying delay by the maximal Lyapunov-Krasovskii fuctional which is constructed as the pointwise maximum of a family of Lyapunov-Krasovskii fuctionals corresponds to vertexes of uncertain polytope.On the other hand,matrix inequalities containing only one scalar and Matlabs LMI Toolbox is utilized to give a non-ellipsoidal description of the reachable set.finally,numerical examples are given to illustrate the existing results.

Keywords: Reachable set, Distributed delay, Lyapunov-Krasovskii function, Polytopic uncertainties.

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Authors: Won-Jae Shin, Young-Hwan You

Abstract:

Cyclic delay diversity (CDD) is a simple technique to intentionally increase frequency selectivity of channels for orthogonal frequency division multiplexing (OFDM).This paper proposes a residual carrier frequency offset (RFO) estimation scheme for OFDMbased broadcasting system using CDD. In order to improve the RFO estimation, this paper addresses a decision scheme of the amount of cyclic delay and pilot pattern used to estimate the RFO. By computer simulation, the proposed estimator is shown to benefit form propoerly chosen delay parameter and perform robustly.

Keywords: OFDM, cyclic delay diversity, FM system, synchronization

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Authors: Sachin Bhalekar

Abstract:

In this paper we propose a necessary condition for the existence of chaos in delay differential equations of fractional order. To explain the proposed theory, we discuss fractional order Liu system and financial system involving delay.

Keywords: Caputo derivative, delay, stability, chaos.

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Authors: Xia Zhou, Shouming Zhong

Abstract:

The problem of delay-range-dependent exponential synchronization is investigated for Lur-e master-slave systems with delay feedback control and Markovian switching. Using Lyapunov- Krasovskii functional and nonsingular M-matrix method, novel delayrange- dependent exponential synchronization in mean square criterions are established. The systems discussed in this paper is advanced system, and takes all the features of interval systems, Itˆo equations, Markovian switching, time-varying delay, as well as the environmental noise, into account. Finally, an example is given to show the validity of the main result.

Keywords: Synchronization, delay-range-dependent, Markov chain, generalized Itō's formula, brownian motion, M-matrix.

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Authors: Santanu Santra, Utpal Roy

Abstract:

The most important mathematical operation for any computing system is addition. An efficient adder can be of greater assistance in designing of any arithmetic circuits. Quantum-dot Cellular Automata (QCA) is a promising nanotechnology to create electronic circuits for computing devices and suitable candidate for next generation of computing systems. The article presents a modest approach to implement a novel XOR gate. The gate is simple in structure and powerful in terms of implementing digital circuits. By applying the XOR gate, the hardware requirement for a QCA circuit can be decrease and circuits can be simpler in level, clock phase and cell count. In order to verify the functionality of the proposed device some implementation of Half Adder (HA) and Full Adder (FA) is checked by means of computer simulations using QCA-Designer tool. Simulation results and physical relations confirm its usefulness in implementing every digital circuit.

Keywords: Clock, Computing system, Majority gate, QCA, QCA Designer.

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Authors: Jasmin Velagic

Abstract:

This paper addresses the design of predictive networked controller with adaptation of a communication delay. The networked control system contains random delays from sensor to controller and from controller to actuator. The proposed predictive controller includes an adaptation loop which decreases the influence of communication delay on the control performance. Also, the predictive controller contains a filter which improves the robustness of the control system. The performance of the proposed adaptive predictive controller is demonstrated by simulation results in comparison with PI controller and predictive controller with constant delay.

Keywords: Predictive control, adaptation, communication delay, communication network.

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Authors: Yasunori Sugita, Toshinori Yoshikawa

Abstract:

The design problem of Infinite Impulse Response (IIR) digital filters is usually expressed as the minimization problem of the complex magnitude error that includes both the magnitude and phase information. However, the group delay of the filter obtained by solving such design problem may be far from the desired group delay. In this paper, we propose a design method of stable IIR digital filters with prespecified maximum group delay errors. In the proposed method, the approximation problems of the magnitude-phase and group delay are separately defined, and these two approximation problems are alternately solved using successive projections. As a result, the proposed method can design the IIR filters that satisfy the prespecified allowable errors for not only the complex magnitude but also the group delay by alternately executing the coefficient update for the magnitude-phase and the group delay approximation. The usefulness of the proposed method is verified through some examples.

Keywords: Filter design, Group delay approximation, Stable IIRfilters, Successive projection method.

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Authors: I. Davies, O. L. C. Haas

Abstract:

In this paper, the problem of stability and stabilization for neutral delay-differential systems with infinite delay is investigated. Using Lyapunov method, new delay-independent sufficient condition for the stability of neutral systems with infinite delay is obtained in terms of linear matrix inequality (LMI). Memory-less state feedback controllers are then designed for the stabilization of the system using the feasible solution of the resulting LMI, which are easily solved using any optimization algorithms. Numerical examples are given to illustrate the results of the proposed methods.

Keywords: Infinite delays, Lyapunov method, linear matrix inequality, neutral systems, stability.

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Authors: Hazem M. El-Bakry, Qiangfu Zhao

Abstract:

Here, a new idea to speed up the operation of complex valued time delay neural networks is presented. The whole data are collected together in a long vector and then tested as a one input pattern. The proposed fast complex valued time delay neural networks uses cross correlation in the frequency domain between the tested data and the input weights of neural networks. It is proved mathematically that the number of computation steps required for the presented fast complex valued time delay neural networks is less than that needed by classical time delay neural networks. Simulation results using MATLAB confirm the theoretical computations.

Keywords: Fast Complex Valued Time Delay Neural Networks, Cross Correlation, Frequency Domain

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