Search results for: CMOS analog integrated circuit

Authors: Rahul Bansal, Sudipta Majumdar

Abstract:

This paper presents the closed form nonlinear expressions of bipolar junction transistor (BJT) differential amplifier (DA) using perturbation method. Circuit equations have been derived using Kirchhoff’s voltage law (KVL) and Kirchhoff’s current law (KCL). The perturbation method has been applied to state variables for obtaining the linear and nonlinear terms. The implementation of the proposed method is simple. The closed form nonlinear expressions provide better insights of physical systems. The derived equations can be used for signal processing applications.

Keywords: Differential amplifier, perturbation method, Taylor series.

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Authors: Vijay Janyani, Trevor M. Benson, Ana Vukovic

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A time-domain numerical model within the framework of transmission line modeling (TLM) is developed to simulate electromagnetic pulse propagation inside multiple microcavities forming photonic crystal (PhC) structures. The model developed is quite general and is capable of simulating complex electromagnetic problems accurately. The field quantities can be mapped onto a passive electrical circuit equivalent what ensures that TLM is provably stable and conservative at a local level. Furthermore, the circuit representation allows a high level of hybridization of TLM with other techniques and lumped circuit models of components and devices. A photonic crystal structure formed by rods (or blocks) of high-permittivity dieletric material embedded in a low-dielectric background medium is simulated as an example. The model developed gives vital spatio-temporal information about the signal, and also gives spectral information over a wide frequency range in a single run. The model has wide applications in microwave communication systems, optical waveguides and electromagnetic materials simulations.

Keywords: Computational Electromagnetics, Numerical Simulation, Transmission Line Modeling.

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Authors: P. Prasad Rao, K. Lal Kishore

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Pipeline ADCs are becoming popular at high speeds and with high resolution. This paper discusses the options of number of bits/stage conversion techniques in pipelined ADCs and their effect on Area, Speed, Power Dissipation and Linearity. The basic building blocks like op-amp, Sample and Hold Circuit, sub converter, DAC, Residue Amplifier used in every stage is assumed to be identical. The sub converters use flash architectures. The design is implemented using 0.18

Keywords: 1.5 bits/stage, Conversion Frequency, Redundancy Switched Capacitor Sample and Hold Circuit

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Authors: Shobha Sharma, Amita Dev

Abstract:

This research paper presents highly optimized barrel shifter at 22nm Hi K metal gate strained Si technology node. This barrel shifter is having a unique combination of static and dynamic body bias which gives lowest power delay product. This power delay product is compared with the same circuit at same technology node with static forward biasing at ‘supply/2’ and also with normal reverse substrate biasing and still found to be the lowest. The power delay product of this barrel sifter is .39362X10-17J and is lowered by approximately 78% to reference proposed barrel shifter at 32nm bulk CMOS technology. Power delay product of barrel shifter at 22nm Hi K Metal gate technology with normal reverse substrate bias is 2.97186933X10-17J and can be compared with this design’s PDP of .39362X10-17J. This design uses both static and dynamic substrate biasing and also has approximately 96% lower power delay product compared to only forward body biased at half of supply voltage. The NMOS model used are predictive technology models of Arizona state university and the simulations to be carried out using HSPICE simulator.

Keywords: Dynamic body biasing, highly optimized barrel shifter, PDP, Static body biasing.

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Authors: Kuan-Yu Chiu, Yin-Hsuan Chen, Tung-Han Chuang

Abstract:

Ti/Ni/Ag/Sn-metallized Si chips were bonded to Ni/Pd/Au-surface finished DBC (Direct Bonding Copper) alumina substrate through the formation of an Ag3Sn intermetallic interlayer by solid–liquid interdiffusion bonding method. The results indicated that the holes and gaps at the bonding interface could be effectively prevented. The intermetallic phases at the bonding interface between the Si/Ti/Ni/Ag/Sn wafer and the DBC substrate were identified as Ag3Sn, Ni3Sn4, and Ni3Sn2. The average bonding strength was about 19.75 MPa, and the maximum bonding strength reached 35.24 MPa.

Keywords: BGBM, Backside Grinding and Backside Metallization, SLID bonding, Solid–liquid Interdiffusion Bonding, Si/Ti/Ni/Sn, Si/Ti/Ni/Ag/Sn, intermetallic compound.

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Authors: Shobha Sharma, Amita Dev

Abstract:

Data driven dynamic logic is the high speed dynamic circuit with low area. The clock of the dynamic circuit is removed and data drives the circuit instead of clock for precharging purpose. This data driven dynamic nand gate is given static forward substrate biasing of Vsupply/2 as well as the substrate bias is connected to the input data, resulting in dynamic substrate bias. The dynamic substrate bias gives the shortest propagation delay with a penalty on the power dissipation. Propagation delay is reduced by 77.8% compared to the normal reverse substrate bias Data driven dynamic nand. Also dynamic substrate biased D3nand’s propagation delay is reduced by 31.26% compared to data driven dynamic nand gate with static forward substrate biasing of Vdd/2. This data driven dynamic nand gate with dynamic body biasing gives us the highest speed with no area penalty and finds its applications where power penalty is acceptable. Also combination of Dynamic and static Forward body bias can be used with reduced propagation delay compared to static forward biased circuit and with comparable increase in an average power. The simulations were done on hspice simulator with 22nm High-k metal gate strained Si technology HP models of Arizona State University, USA.

Keywords: Data driven nand gate, dynamic substrate biasing, nand gate, static substrate biasing.

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Authors: S. J. Arif

Abstract:

In the presented technique, a simple method is given for accurate measurement and control of power frequency deviation. The sinusoidal signal for which the frequency deviation measurement is required is transformed to a low voltage level and passed through a zero crossing detector to convert it into a pulse train. Another stable square wave signal of 10 KHz is obtained using a crystal oscillator and decade dividing assemblies (DDA). These signals are combined digitally and then passed through decade counters to give a unique combination of pulses or levels, which are further encoded to make them equally suitable for both control applications and display units. The developed circuit using discrete components has a resolution of 0.5 Hz and completes measurement within 20 ms. The realized circuit is simulated and synthesized using Verilog HDL and subsequently implemented on FPGA. The results of measurement on FPGA are observed on a very high resolution logic analyzer. These results accurately match the simulation results as well as the results of same circuit implemented with discrete components. The proposed system is suitable for accurate measurement and control of power frequency deviation.

Keywords: Digital encoder for frequency measurement, frequency deviation measurement, measurement and control systems, power systems.

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Authors: Mehdi Hosseinzadeh, Somayyeh Jafarali Jassbi, Keivan Navi

Abstract:

Residue Number System (RNS) is a modular representation and is proved to be an instrumental tool in many digital signal processing (DSP) applications which require high-speed computations. RNS is an integer and non weighted number system; it can support parallel, carry-free, high-speed and low power arithmetic. A very interesting correspondence exists between the concepts of Multiple Valued Logic (MVL) and Residue Number Arithmetic. If the number of levels used to represent MVL signals is chosen to be consistent with the moduli which create the finite rings in the RNS, MVL becomes a very natural representation for the RNS. There are two concerns related to the application of this Number System: reaching the most possible speed and the largest dynamic range. There is a conflict when one wants to resolve both these problem. That is augmenting the dynamic range results in reducing the speed in the same time. For achieving the most performance a method is considere named “One-Hot Residue Number System" in this implementation the propagation is only equal to one transistor delay. The problem with this method is the huge increase in the number of transistors they are increased in order m² . In real application this is practically impossible. In this paper combining the Multiple Valued Logic and One-Hot Residue Number System we represent a new method to resolve both of these two problems. In this paper we represent a novel design of an OHRNS-based adder circuit. This circuit is useable for Multiple Valued Logic moduli, in comparison to other RNS design; this circuit has considerably improved the number of transistors and power consumption.

Keywords: Computer Arithmetic, Residue Number System, Multiple Valued Logic, One-Hot, VLSI.

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Authors: Syed Javed Arif, Mohd Ayyub Khan, Saleem Anwar Khan

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In this paper, a simple method is presented for measurement of power frequency deviations. A phase locked loop (PLL) is used to multiply the signal under test by a factor of 100. The number of pulses in this pulse train signal is counted over a stable known period, using decade driving assemblies (DDAs) and flip-flops. These signals are combined using logic gates and then passed through decade counters to give a unique combination of pulses or levels, which are further encoded. These pulses are equally suitable for both control applications and display units. The experimental circuit developed gives a resolution of 1 Hz within the measurement period of 20 ms. The proposed circuit is also simulated in Verilog Hardware Description Language (VHDL) and implemented using Field Programing Gate Arrays (FPGAs). A Mixed signal Oscilloscope (MSO) is used to observe the results of FPGA implementation. These results are compared with the results of the proposed circuit of discrete components. The proposed system is useful for frequency deviation measurement and control in power systems.

Keywords: Frequency measurement, digital control, phase locked loop, encoding, Verilog HDL.

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Authors: Wang Zhulin, Min Fuhong, Peng Guangya, Wang Yaoda, Cao Yi

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In this paper, a magnetron memristor model based on hyperbolic sine function is presented and the correctness proved by studying the trajectory of its voltage and current phase, and then a memristor chaotic system with the memristor model is presented. The phase trajectories and the bifurcation diagrams and Lyapunov exponent spectrum of the magnetron memristor system are plotted by numerical simulation, and the chaotic evolution with changing the parameters of the system is also given. The paper includes numerical simulations and mathematical model, which confirming that the system, has a wealth of dynamic behavior.

Keywords: Memristor, chaotic circuit, dynamical behavior, chaotic system.

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Authors: O. Kurtulus, C. Yavuz

Abstract:

The end of the line controls of the finished products in the automotive industry is important. The control that has been conducted with the manual methods for the sliding doors tracks is not sufficient and faulty products cannot be identified. As a result, the customer has the faulty products. In the scope of this study, the design criteria of the PLC integrated modular end of line control unit has been examined, designed and manufactured to make the control of the 10 different track profile to 2 different vehicles with an objective to minimize the salvage costs by obtaining more sensitive, certain and accurate measurement results. In the study that started with literature and patent review, the design inputs have been specified, the technical concept has been developed, computer supported mechanic design, control system and automation design, design review and design improvement have been made. Laser analog sensors at high sensitivity, probes and modular blocks have been used in the unit. The measurement has been conducted in the system and it is observed that measurement results are more sensitive than the previous methods that we use.

Keywords: Control unit design, end of line, modular design, sliding door system.

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Authors: Amit Kumar Gautam, Sudipta Majumdar

Abstract:

This paper presents parameter estimation of a single-phase rectifier using extended Kalman filter (EKF). The state space model has been obtained using Kirchhoff’s current law (KCL) and Kirchhoff’s voltage law (KVL). The capacitor voltage and diode current of the circuit have been estimated using EKF. Simulation results validate the better accuracy of the proposed method as compared to the least mean square method (LMS). Further, EKF has the advantage that it can be used for nonlinear systems.

Keywords: Extended Kalman filter, parameter estimation, single phase rectifier, state space modelling.

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Authors: Chih Chin Yang, Chih Yu Lee, Jing Yi Wang, Mei Zhen Xue, Chia Yueh Wu

Abstract:

A well-defined frequency multiple dividing (FMD) circuit using a resonant model is presented in this research. The basic component of a frequency multiple divider as used in a resonant model is established by compositing a well-defined resonant effect of negative differential resistance (NDR) characteristics which possesses a wider operational region and high operational current at a bias voltage of about 1.15 V. The resonant model is then applied in the frequency dividing circuit with the above division ratio (R_D) of 200 at the signal input of middle frequency. The division ratio also exists at the input of a low frequency signal.

Keywords: Divider, frequency, resonant model.

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Authors: Jiri Sebesta

Abstract:

Phase locked loops (PLL) and delay locked loops (DLL) play an important role in establishing coherent references (phase of carrier and symbol timing) in digital communication systems. Fully digital receiver including digital carrier synchronizer and symbol timing synchronizer fulfils the conditions for universal multi-mode communication receiver with option of symbol rate setting over several digit places and long-term stability of requirement parameters. Afterwards it is necessary to realize PLL and DLL in synchronizer in digital form and to approach to these subsystems as a discrete representation of analog template. Analysis of discrete phase locked loop (DPLL) or discrete delay locked loop (DDLL) and technique to determine their characteristics based on analog (continuous-time) template is performed in this posed paper. There are derived transmission response and error function for 1st order discrete locked loop and resulting equations and graphical representations for 2nd order one. It is shown that the spectrum translation due to sampling takes effect at frequency characteristics computing for specific values of loop parameters.

Keywords: Carrier synchronization, coherent demodulation, software defined receiver, symbol timing.

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Authors: A.R. Aswatha, T. Basavaraju, S. Sandeep Kumar

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Timing driven physical design, synthesis, and optimization tools need efficient closed-form delay models for estimating the delay associated with each net in an integrated circuit (IC) design. The total number of nets in a modern IC design has increased dramatically and exceeded millions. Therefore efficient modeling of interconnection is needed for high speed IC-s. This paper presents closed–form expressions for RC and RLC interconnection trees in current mode signaling, which can be implemented in VLSI design tool. These analytical model expressions can be used for accurate calculation of delay after the design clock tree has been laid out and the design is fully routed. Evaluation of these analytical models is several orders of magnitude faster than simulation using SPICE.

Keywords: IC design, RC/RLC Interconnection, VLSI Systems.

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Authors: Emilija Miletic, Milos Krstic, Maxim Piz, Michael Methfessel

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In this work we present a solution for DAGC (Digital Automatic Gain Control) in WLAN receivers compatible to IEEE 802.11a/g standard. Those standards define communication in 5/2.4 GHz band using Orthogonal Frequency Division Multiplexing OFDM modulation scheme. WLAN Transceiver that we have used enables gain control over Low Noise Amplifier (LNA) and a Variable Gain Amplifier (VGA). The control over those signals is performed in our digital baseband processor using dedicated hardware block DAGC. DAGC in this process is used to automatically control the VGA and LNA in order to achieve better signal-to-noise ratio, decrease FER (Frame Error Rate) and hold the average power of the baseband signal close to the desired set point. DAGC function in baseband processor is done in few steps: measuring power levels of baseband samples of an RF signal,accumulating the differences between the measured power level and actual gain setting, adjusting a gain factor of the accumulation, and applying the adjusted gain factor the baseband values. Based on the measurement results of RSSI signal dependence to input power we have concluded that this digital AGC can be implemented applying the simple linearization of the RSSI. This solution is very simple but also effective and reduces complexity and power consumption of the DAGC. This DAGC is implemented and tested both in FPGA and in ASIC as a part of our WLAN baseband processor. Finally, we have integrated this circuit in a compact WLAN PCMCIA board based on MAC and baseband ASIC chips designed from us.

Keywords: WLAN, AGC, RSSI, baseband processor

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Authors: Cheng Zhang, James Marco, Walid Allafi, Truong Q. Dinh, W. D. Widanage

Abstract:

Equivalent circuit models (ECMs) are widely used in battery management systems in electric vehicles and other battery energy storage systems. The battery dynamics and the model parameters vary under different working conditions, such as different temperature and state of charge (SOC) levels, and therefore online parameter identification can improve the modelling accuracy. This paper presents a way of online ECM parameter identification using a continuous time (CT) estimation method. The CT estimation method has several advantages over discrete time (DT) estimation methods for ECM parameter identification due to the widely separated battery dynamic modes and fast sampling. The presented method can be used for online SOC estimation. Test data are collected using a lithium ion cell, and the experimental results show that the presented CT method achieves better modelling accuracy compared with the conventional DT recursive least square method. The effectiveness of the presented method for online SOC estimation is also verified on test data.

Keywords: Equivalent circuit model, continuous time domain estimation, linear integral filter method, parameter and SOC estimation, recursive least square.

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Authors: Hyemi Gam, Dae-Sub Oh, Bon-Jun Ku

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This paper addresses the analysis of the interference between complementary ground component (CGC) base station and mobile earth station (MES). In the frequency sharing scenario between CGC base station and MES, the interference from the adjacent beams must be considered. In this paper, we estimated the interference to MES of an integrated satellite system and the result is presented as the carrier to interference ratio(C/I) with respect to the number of CGC base station in the adjacent beam and the ratio of satellite beam center radius to the total beam radius (R1/R). By using these results, we can determine the minimum separation distance between the CGC base stations of adjacent beam and MES for compatibility. This result can be applied to the CGC base station of an integrated satellite system for the effective frequency sharing.

Keywords: Integrated satellite system, interference, frequency reuse pattern, CGC base station, MES, frequency sharing.

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Authors: Chien-Yeh Hsu, Yuan-Ching Chiang, Zi-Jie Chien, Sih-Li Chen

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In this study, a field experiment and performance analysis of air-tunnel heat exchanger integrated with water-filled raft foundation of residential building were performed. In order to obtain better performance, conventional applications of air-tunnel inevitably have high initial cost or issues about insufficient installation space. To improve the feasibility of air tunnel heat exchanger in high-density housing, an integrated system consisting of air pipes immersed in the water-filled raft foundation was presented, taking advantage of immense amount of water and relatively stable temperature in raft foundation of building. The foundation-integrated air tunnel was applied to a residential building located in Yilan, Taiwan, and its thermal performance was measured in the field experiment. The results indicated that the cooling potential of integrated system was close to the potential of soil-based EAHE at 2 m depth or deeper. An analytical model based on thermal resistance method was validated by measurement results, and was used to carry out the dimensioning of foundation-integrated air tunnel. The discrepancies between calculated value and measured data were less than 2.7%. In addition, the return-on-investment with regard to thermal performance and economics of the application was evaluated. Because the installation for air tunnel is scheduled in the building foundation construction, the utilization of integrated system spends less construction cost compare to the conventional earth-air tunnel.

Keywords: Air tunnel, ground heat exchanger, raft foundation, residential building.

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Authors: Mazhar B. Tayel, Amr H. Yassin

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A proposed small-signal model parameters for a pseudomorphic high electron mobility transistor (PHEMT) is presented. Both extrinsic and intrinsic circuit elements of a smallsignal model are determined using genetic algorithm (GA) as a stochastic global search and optimization tool. The parameters extraction of the small-signal model is performed on 200-μm gate width AlGaAs/InGaAs PHEMT. The equivalent circuit elements for a proposed 18 elements model are determined directly from the measured S- parameters. The GA is used to extract the parameters of the proposed small-signal model from 0.5 up to 18 GHz.

Keywords: PHEMT, Genetic Algorithms, small signal modeling, optimization.

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Authors: Binod Kumar Saha

Abstract:

The objective of the present paper is a numerical analysis of the flow forces acting on spool surfaces of a pressure regulated valve. The transient, compressible and turbulent flow structures inside the valve are simulated using ANSYS FLUENT coupled with a special UDF. Here, valve inlet pressure is varied in a stepwise manner. For every value of inlet pressure, transient analysis leads to a quasi-static flow through the valve. Spool forces are calculated based on different pressures at inlet. From this information of spool forces, pressure characteristic of the passive control circuit has been derived.

Keywords: Pressure Regulating Valve, Spool Opening, Spool Movement, Force Balance, CFD.

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Authors: Diana M.L. Wong

Abstract:

This paper presents an integrated case based and rule based reasoning method for car faulty diagnosis. The reasoning method is done through extracting the past cases from the Proton Service Center while comparing with the preset rules to deduce a diagnosis/solution to a car service case. New cases will be stored to the knowledge base. The test cases examples illustrate the effectiveness of the proposed integrated reasoning. It has proven accuracy of similar reasoning if carried out by a service advisor from the service center.

Keywords: component; case based reasoning (CBR), rule basedreasoning (RBR), decision support systems, diagnosis tool.

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Authors: Muhammad Mujtaba Asad, Razali Bin Hassan, Fahad Sherwani

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This paper explains about the voltage output for DC to DC boost converter between open loop, PID controller and fuzzy logic controller through Matlab Simulink. Simulink input voltage was set at 12V and the voltage reference was set at 24V. The analysis on the deviation of voltage resulted that the difference between reference voltage setting and the output voltage is always lower. Comparison between open loop, PID and FLC shows that, the open loop circuit having a bit higher on the deviation of voltage. The PID circuit boosts for FLC has a lesser deviation of voltage and proved that it is such a better performance on control the deviation of voltage during the boost mode.

Keywords: Boost Convertors, Power Electronics, PID, Fuzzy logic, Open loop.

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Authors: Ali Al-Ataby , Fawzi Al-Naima

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Symbolic Circuit Analysis (SCA) is a technique used to generate the symbolic expression of a network. It has become a well-established technique in circuit analysis and design. The symbolic expression of networks offers excellent way to perform frequency response analysis, sensitivity computation, stability measurements, performance optimization, and fault diagnosis. Many approaches have been proposed in the area of SCA offering different features and capabilities. Numerical Interpolation methods are very common in this context, especially by using the Fast Fourier Transform (FFT). The aim of this paper is to present a method for SCA that depends on the use of Wavelet Transform (WT) as a mathematical tool to generate the symbolic expression for large circuits with minimizing the analysis time by reducing the number of computations.

Keywords: Numerical Interpolation, Sparse Matrices, SymbolicAnalysis, Wavelet Transform.

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Authors: Raj Kumar Rajak, Bharat Mishra

Abstract:

Bio-batteries represent an entirely new long-term, reasonable, reachable and ecofriendly approach to produce sustainable energy. In the present experimental work, we have studied the effect of generation of power by bio-battery using different electrode pairs. The tests show that it is possible to generate electricity using cow dung as an electrolyte. C-Mg electrode pair shows maximum voltage and SCC (Short Circuit Current) while C-Zn electrode pair shows less OCV (Open Circuit Voltage) and SCC. We have chosen C-Zn electrodes because Mg electrodes are not economical. By the studies of different electrodes and cow dung, it is found that C-Zn electrode battery is more suitable. This result shows that the bio-batteries have the potency to full fill the need of electricity demand for lower energy equipment.

Keywords: Bio-batteries, electricity, cow dung, electrodes, non-conventional.

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Authors: Edison Muzenda

Abstract:

Gauteng, as the province with the greatest industrial and population density, the economic hub of South Africa also generates the greatest amount of waste, both general and hazardous. Therefore the province has a significant need to develop and apply appropriate integrated waste management policies that ensure that waste is recognised as a serious problem and is managed in an effective integrated manner to preserve both the present and future human health and environment. This paper reflects on Gauteng-s waste outlook in particular the province-s General Waste Minimisation Plan and its Integrated Waste Management Policy. The paper also looks at general waste generation, recyclable waste streams as well as recycling and separation at source initiatives in the province. Both the quantity and nature of solid waste differs considerably across the socio-economic spectrum. People in informal settlements generate an average of 0.16 kg per person per day whereas 2 kg per day is not unusual in affluent areas. For example the amount of waste generated in Johannesburg is approximately 1.2 kg per person per day.

Keywords: General waste, generation, integrated, minimisation, recycling, separation

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Authors: Mamidi Ramakrishna Rao

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Doubly-fed induction generator (DFIG) is currently the choice for many wind turbines. These generators, when connected to the grid through a converter, is subjected to varied power system conditions like voltage variation, frequency variation, short circuit fault conditions, etc. Further, many countries like Canada, Germany, UK, Scotland, etc. have distinct grid codes relating to wind turbines. Accordingly, following the network faults, wind turbines have to supply a definite reactive current. To satisfy the requirements including reactive current capability, an optimum electrical design becomes a mandate for DFIG to function. This paper intends to optimize the equivalent circuit parameters of an electrical design for satisfactory DFIG performance. Direct search method has been used for optimization of the parameters. The variables selected include electromagnetic core dimensions (diameters and stack length), slot dimensions, radial air gap between stator and rotor and winding copper cross section area. Optimization for 2 MW DFIG has been executed separately for three objective functions - maximum reactive power capability (Case I), maximum efficiency (Case II) and minimum weight (Case III). In the optimization analysis program, voltage variations (10%), power factor- leading and lagging (0.95), speeds for corresponding to slips (-0.3 to +0.3) have been considered. The optimum designs obtained for objective functions were compared. It can be concluded that direct search method of optimization helps in determining an optimum electrical design for each objective function like efficiency or reactive power capability or weight minimization.

Keywords: Direct search, DFIG, equivalent circuit parameters, optimization.

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Authors: Jayesh M. Sonawane, Prakash C. Ghosh

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Landfill leachate emerges as a promising feedstock for microbial fuel cells (MFCs). In the present investigation, direct air-breathing cathode-based MFCs are fabricated to investigate the potential of landfill leachate. Three MFCs that have different cathode areas are fabricated and investigated for 17 days under open circuit conditions. The maximum open circuit voltage (OCV) is observed to be as high as 1.29 V. The maximum cathode area specific power density achieved in the reactor is 1513 mW m^-2. Further studies are under progress to understand the origin of high OCV obtained from landfill leachate-based MFCs.

Keywords: Microbial fuel cells, landfill leachate, air-breathing cathode, performance study.

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Authors: A. Harmse, R. Goede

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Students with high level skills are in demand, especially in scare skill environments. If universities wish to be successful and competitive, its students need to be adequately equipped with the necessary tools. Work Integrated Learning (WIL) is an essential component of the education of a student. The relevance of higher education should be assessed in terms of how it meets the needs of society and the world of work in a global economy. This paper demonstrates how to use Habermas's theory of communicative action to reflect on students- perceptions on their integration in the work environment to achieve social integration and financial justification. Interpretive questionnaires are used to determine the students- view of how they are integrated into society, and contributing to the economy. This paper explores the use of Habermas-s theory of communicative action to give theoretical and methodological guidance for the practice of social findings obtained in this inquiry.

Keywords: Discourse, Habermas, Information Systems Education, Theory of Communicative Action, Work Integrated Learning.

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Authors: Ki-Jin Kim, Sanghoon Park, K. H. Ahn

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This paper presents the 20-GHz fractional PLL (Phase Locked Loop) circuit for the next generation Wi-Fi by using 90 nm TSMC process. The newly suggested millimeter wave 16/17 pre-scalar is designed and verified by measurement to make the fractional PLL having a low quantization noise. The operational bandwidth of the 60 GHz system is 15 % of the carrier frequency which requires large value of Kv (VCO control gain) resulting in degradation of phase noise. To solve this problem, this paper adopts AFC (Automatic Frequency Controller) controlled 4-bit millimeter wave VCO with small value of Kv. Also constant Kv is implemented using 4-bit varactor bank. The measured operational bandwidth is 18.2 ~ 23.2 GHz which is 25 % of the carrier frequency. The phase noise of -58 and -96.2 dBc/Hz at 100 KHz and 1 MHz offset is measured respectively. The total power consumption of the PLL is only 30 mW.

Keywords: Millimeter Wave Fractional PLL, Wide band VCO, WPAN Transceiver.

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